JP7162966B2 - 電子部品 - Google Patents
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- JP7162966B2 JP7162966B2 JP2020537612A JP2020537612A JP7162966B2 JP 7162966 B2 JP7162966 B2 JP 7162966B2 JP 2020537612 A JP2020537612 A JP 2020537612A JP 2020537612 A JP2020537612 A JP 2020537612A JP 7162966 B2 JP7162966 B2 JP 7162966B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
- H01L23/53247—Noble-metal alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
・PTC素子
・NTC素子
・バリスタ
・アレスタ
・多層部品
・インダクタ
・キャパシタ
・オーミック抵抗
・ガラス
・金属、特に、例えば焼結層のためのマイクロ銀(μAg)、Ag、例えば超音波熱圧着に基づく接合技術のためのAu、例えば熱圧着に基づく接合技術のためのAuSn、SnAgCu、例えばロウ付けのためのCu-Si3N4-Cuから選択された1つ以上の金属
・例えばSi3N4、有利にはAlNのようなセラミック
・例えばSi3N4及び/又はAlNを充填したエポキシ樹脂のような熱伝導性接着剤
・熱基板としての、特に1つ以上のキャビティと1つ以上の統合された機能性要素とを備える多層基板としての、第1の支持体及び/又は第2の支持体の構築
・機能性要素の、冷却システム、特に1つ以上の冷却要素への、直接的な熱的接続
・機能性要素の気密な封入
・特に、第1の支持体を第2の支持体と組み合わせて用いることによる、及び/又は、第1の支持体の異なる面上に又は2つの支持体の組み合わせの異なる面上に2つの冷却要素を配置することによる、熱機械的な応力を補償するための対称的な構造
・半導体チップの対称的な接続によって、より良好な熱伝導性を利用することができる。
・より高い機械的なロバスト性
・より高いパワー密度
・より低い熱抵抗
・要素と熱基板セラミックとの間の熱膨張差の改善された適合
・冷却システムへのより良好な接続可能性
・簡易化された製造方法
・セラミック-ガラス-セラミック
・セラミック-金属-セラミック、特にμAgを用いた銀焼結、Auを用いた超音波熱圧着、AuSnを用いた熱圧着、Au、AuSnを用いたロウ付け、SnAgCu、Cu-Si3N4-Cu
1’ 第2の支持体
2 冷却要素
3 半導体チップ
4,4-1~4-9 機能性要素
5 キャビティ
6 金属層
7 接合層
8 ビア
9 導電路
10 グラウト
100 電子部品
Claims (13)
- 少なくとも1つの第1の支持体と、第2の支持体と、少なくとも1つの半導体チップと、を備える電子部品であって、
前記第1の支持体はキャビティを備え、前記キャビティ内には前記半導体チップが配置されており、
前記第1の支持体は多層技術で構築されており、
前記第1の支持体の上には前記第2の支持体が配置されており、前記第2の支持体は、前記第1の支持体の前記キャビティ内の前記半導体チップを覆い、プリント基板を備え、及び/又は、多層技術で構築されており、
前記第2の支持体はキャビティを備え、
前記半導体チップは、前記第1の支持体の前記キャビティ内に部分的に埋没して配置されていると共に、前記第1の支持体の前記キャビティから突出する部分を有し、前記突出する部分は、前記第2の支持体の前記キャビティ内に配置されている電子部品。 - 前記第1の支持体の前記キャビティと前記第2の支持体の前記キャビティは、対称的に形成されている、請求項1に記載の電子部品。
- 前記第1の支持体及び前記第2の支持体は、対称である、請求項1又は2に記載の電子部品。
- 前記第1の支持体及び/又は前記第2の支持体は、以下の特徴のうち1つ以上を備える、請求項1~3のいずれか1項に記載の電子部品。
・導電性又は電気絶縁性のセラミック材料
・少なくとも1つの表面上の金属層
・少なくとも1つの電気ビア及び/又はサーマルビア、及び/又は、少なくとも1つの内部電極及び/又は導電路
・少なくとも1つの機能性要素 - 前記セラミック材料は、AlN、BN、Al 2 O 3 、SiC、SiN、ZnO、BeOから選択され、
前記金属層は、Cu、Ag、W、Mo、Ti、Au、Ni、Zn並びにそれらの混合物及び合金から選択された材料を含む、請求項4に記載の電子部品。 - 前記少なくとも1つの機能性要素は、以下の素子のうちの1つ以上を備える、請求項4又は5に記載の電子部品。
・PTC素子
・NTC素子
・バリスタ
・アレスタ
・多層部品
・インダクタ
・キャパシタ
・オーミック抵抗 - 前記第1の支持体及び/又は前記第2の支持体は、少なくとも1つの機能性要素を備え、前記少なくとも1つの機能性要素は、分散した部材の形態でキャビティ内に配置されている、請求項4~6のいずれか1項に記載の電子部品。
- 前記第1の支持体及び/又は前記第2の支持体は、少なくとも1つの機能性要素を備え、前記少なくとも1つの機能性要素は、前記第1及び/又は第2の支持体の部分領域によって形成される、請求項4~7のいずれか1項に記載の電子部品。
- 前記第1及び/又は第2の支持体は、冷却システムへの統合された熱的接続を提供するサーマルビアを備える、請求項1~8のいずれか1項に記載の電子部品。
- 前記第1及び/又は第2の支持体の表面上に冷却要素が配置されている、請求項1~9のいずれか1項に記載の電子部品。
- 前記冷却要素は、一体化された冷却リブを有するヒートシンクを備えた空気冷却器として、ヒートスプレッダとして、及び/又は、水冷却器として形成されている、請求項10に記載の電子部品。
- 少なくとも前記第1及び第2の支持体の間に、及び/又は、少なくとも前記支持体のうちの一方と冷却要素との間に、接合層が配置されている、請求項1~11のいずれか1項に記載の電子部品。
- 前記接合層は、以下の材料のうちの1つ以上を含む、請求項12に記載の電子部品。
・ガラス
・マイクロ銀、Ag、Au、AuSn、SnAgCu、Cu-Si3N4-Cuから選択された1つ以上の金属
・Si3N4及び/又はAlN
・熱伝導性接着剤としての、Si3N4及び/又はAlNを充填したエポキシ樹脂
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102018102144.5A DE102018102144A1 (de) | 2018-01-31 | 2018-01-31 | Elektronisches Bauelement |
DE102018102144.5 | 2018-01-31 | ||
PCT/EP2019/052293 WO2019149778A1 (de) | 2018-01-31 | 2019-01-30 | Elektronisches bauelement |
Publications (2)
Publication Number | Publication Date |
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JP2021509777A JP2021509777A (ja) | 2021-04-01 |
JP7162966B2 true JP7162966B2 (ja) | 2022-10-31 |
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Application Number | Title | Priority Date | Filing Date |
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JP2020537612A Active JP7162966B2 (ja) | 2018-01-31 | 2019-01-30 | 電子部品 |
Country Status (6)
Country | Link |
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US (1) | US11462476B2 (ja) |
EP (1) | EP3747048A1 (ja) |
JP (1) | JP7162966B2 (ja) |
CN (1) | CN111656520A (ja) |
DE (1) | DE102018102144A1 (ja) |
WO (1) | WO2019149778A1 (ja) |
Families Citing this family (8)
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US10881028B1 (en) | 2019-07-03 | 2020-12-29 | Apple Inc. | Efficient heat removal from electronic modules |
DE102019124593A1 (de) * | 2019-09-12 | 2021-03-18 | Tdk Electronics Ag | Kühlsystem |
US11710945B2 (en) | 2020-05-25 | 2023-07-25 | Apple Inc. | Projection of patterned and flood illumination |
DE102020209752A1 (de) | 2020-08-03 | 2022-02-03 | Robert Bosch Gesellschaft mit beschränkter Haftung | Elektronisches Schaltungsmodul |
US11699715B1 (en) | 2020-09-06 | 2023-07-11 | Apple Inc. | Flip-chip mounting of optoelectronic chips |
CN113675158B (zh) * | 2021-07-06 | 2024-01-05 | 珠海越亚半导体股份有限公司 | 循环冷却嵌埋封装基板及其制作方法 |
EP4340014A1 (de) * | 2022-09-15 | 2024-03-20 | Siemens Aktiengesellschaft | Anordnung mit mindestens einem passiven bauelement |
DE102022125554A1 (de) | 2022-10-04 | 2024-04-04 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Package mit Komponententräger mit Hohlraum und elektronischer Komponente sowie funktionellem Füllmedium darin |
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DE102018102144A1 (de) | 2019-08-01 |
EP3747048A1 (de) | 2020-12-09 |
WO2019149778A1 (de) | 2019-08-08 |
US11462476B2 (en) | 2022-10-04 |
JP2021509777A (ja) | 2021-04-01 |
US20210066199A1 (en) | 2021-03-04 |
CN111656520A (zh) | 2020-09-11 |
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