WO2022124895A2

WO2022124895A2 - Integrated circuit comprising improved die attachment layer

Info

Publication number: WO2022124895A2
Application number: PCT/NL2021/050747
Authority: WO
Inventors: John Suman Nakka
Original assignee: Stichting Chip Integration Technology Centre
Priority date: 2020-12-08
Filing date: 2021-12-08
Publication date: 2022-06-16
Also published as: WO2022124895A3; NL2027068B1

Abstract

The present invention is in the field of an integrated circuit (IC) which is attached to a substrate. Thereby an IC-package is formed. Generally, in many IC packages, the devices are situated on top of a substrate. The present invention relates to an integrated circuit comprising a substrate, a die, and an improved die attachment layer, and a method of die bonding, wherein a die is attached to a substrate with a die attachment layer.

Description

Integrated circuit comprising improved die attachment layer

FIELD OF THE INVENTION

BACKGROUND OF THE INVENTION

The present invention is in the field of an integrated circuit (IC) which is attached to a substrate. Thereby an IC-package is formed. Generally, in many IC packages, the devices are situated on top of a substrate. The substrate may serve as a physical interconnection between the devices and a board in a system. Sometimes this is referred to as embedded packaging. The purpose is to embed dies inside or on the substrate using a multi-step manufacturing process. A die, multiple dies, MEMS or passives may be embedded in a side-by-side fashion in the core of an organic laminate substrate. The components can be connected using copper-plated vias. Three broad categories in IC packaging may be mentioned, namely lead-frame, wafer-level packaging (WLP), and substrate. The present invention makes in particular use of a substrate. Substrate-based packages may fall into several categories, such as ceramic and organic laminate packages. Ceramic substrates can be based on aluminium oxide, aluminium nitride and other materials. Ceramic-based packages can be used for surface-mount devices, CMOS image sensors and multi-chip modules. Organic laminate substrates can be used for volumetric devices, flip-chip devices, and system-in-packages (SiPs). For these packages, the devices reside on top of the substrate. Such substrates may use similar or identical materials as a printed-circuit board (PCB). Organic substrates may also be multi-layer technologies, where at least two organic layers are separated by a metal layer. The metal layers act as an electromigration shield in the package.

Typically, in a conventional die-attach process, only one die-attach material is used to attach die on to the substrate. In an alternative solution of wafer level chip scale packaging (WLCSP) technology, a die is connected to a substrate, which is then referred to as leadframe, via. bumps while the free space in between the bumps (solder, Cu, etc.) and the die-edges and corners are filled with a (soft) tough material, which is called underfill.

One of the most common failures of electronic packages is fracture of die and die-attach materials as can be visualized during reliability testing such as by thermal cycling (TMCL). During TMCL, the package may undergo thermal cycling from low temperatures (<0°C) to high temperatures (>100°C), and back. Quite often a fracture (or crack) is found at the corner of the die (or substrate), and it can propagates in different regions within the package. Also, fracture may occur as a consequence of poor package design, and of external factors, such as humidity-

Some documents may be referred to. US 2019/006268 Al recites a die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions., DE 10 2013 226334 Al recites a circuit carrier. The circuit carrier has a particularly solid semiconductor component. The semiconductor module has at least one electrical connection. The electrical connection preferably forms a surface area of the semiconductor module. The connection is connected to an electrical contact by means of at least one sintered electrical connecting means. The contact and the semiconductor component each form a joining partner for the sintered connecting means. According to the invention, the connecting means between the connection and the contact is formed by at least two sintered layers which contact one another in their flat extension. A thermal expansion coefficient of at least one of the sintered layers or all of the sintered layers is preferably between the expansion coefficient of the joining partner and the expansion coefficient of the sintered layer adjacent to the sintered layer. US 2018/204786 Al recites a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semi conductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die. JP 2018 032830 A recites a semiconductor device formed by bonding a semiconductor element to a metal plate through a bonding layer having an optimum shape. The semiconductor device bonds a semiconductor element to a metal plate through a bonding layer. The bonding layer has an outer bonding layer that defines the outer peripheral surface of the bonding layer and an inner bonding layer that fills the inner side of the outer bonding layer. The outer bonding layer has lower thermal conductivity and thermal expansion coefficient than the inner bonding layer. The inner and outer surfaces of the outer bonding layer are inclined toward the outside of the outer bonding layer as approaching to the metal plate, EP 0 712 153 A2 recites a method for soldering a first component having a metal surface to a second component having a metal surface includes holding the metal surface of the first component in a position above a placement area on the metal surface of the second component to establish a gap between the surfaces. The method further includes reflowing solder within the gap. A structure is described including a thermally conductive baseplate, an electrical insulator attached to the baseplate, and a metallic shield mounted on the insulator. The structure also includes an integrated power device having a power-dissipating electronic device, and a first metal layer connected to the shield through a solder joint. A substrate includes an aperture, and the integrated power device is mounted with the powerdissipating device sitting within the aperture. The substrate also includes a conductive run electrically connected to a second metal layer of the integrated power device. A method for use in making a package for electrical circuits includes attaching an electrical insulator within a recess of a first metallic component. The method also includes registering a second metallic component within the recess using a template tool and bonding the second metallic component to the insulator. A third component is soldered to the second metallic component. A structure is disclosed including an electrical conductor and a sheet of conductive material including a punt soldered to the electrical conductor. US 2013/256894 Al recites a sintered porous metallic film as a die attach mechanically connecting a backside of a semiconductor die to a substrate of a package. Another exemplary disclosed embodiment comprises a sintered porous metallic film as an electrical connection between an electrode on an active surface of a semiconductor die and a substrate of a package. The porous metallic film may be integrated as a prefabricated film or may be created at the wafer or substrate level. By providing a conformal bond through the presence of pores in the metallic film, the sintered connection can provide a reliable mechanical connection with a lower effective elastic modulus. Thermal expansion stresses between die and substrate are thereby accommodated for robustness against thermal cycling, which is of particular relevance for high performance power modules and automotive applications. JP 2015 185559 A recites a bonding method of a semiconductor chip and a substrate that can obtain a high reliability. A method of manufacturing a semiconductor module is recited, including: a first step of applying a metal particle paste containing an organic component in a chip area of an insulation substrate where a conductive plate is formed; a second step of putting a metal foam on the insulation substrate on which the metal particle paste is applied so as to abut on the metal particle paste; a third step of drying the insulation substrate on which the foam is put; a fourth step of mounting a semiconductor chip on whose rear face an electrode is formed, on the dried insulation substrate so that the rear face side is directed toward the substrate side; and a fifth step of heating the semiconductor chip mounted on the insulation substrate while applying pressure to bond the insulation substrate with the semiconductor chip. And US 2015/014865 Al recites a connection arrangement which comprises at least one electric and/or electronic component. The at least one electric and/or electronic component has at least one connection face, which is connected in a bonded manner to a join partner by means of a connection layer. The connection layer can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer is arranged adjacent to the connection layer in a bonded manner. The reinforcement layer has a higher modulus of elasticity than the connection layer. A particularly good protective effect is achieved if the reinforcement layer is formed in a frame-like manner by an outer and an inner boundary, and, at least with the outer boundary thereof, encloses the connection face of the at least one electric and/or electronic component.

The present invention therefore relates to an integrated circuit and further aspects there- of, which overcomes one or more of the above disadvantages, without compromising functionality and advantages.

SUMMARY OF THE INVENTION

It is an object of the invention to overcome one or more limitations of the integrated circuits of the prior art and at the very least to provide an alternative thereto. The present invention relates to a new type of integrated circuit comprising a substrate (10), on the substrate an attachment layer (20), and on the attachment layer a die (30), characterized in that the die attachment layer comprises at least one first region (21) comprising a first attachment material and at least one second region (22) comprising a second attachment material different from the first attachment material, wherein the at least one first region is located centrally on the substrate, wherein the at least one second region is located eccentric, such as at a side, at a part of a side, or at a comer. The at least one first region comprises a material with a thermal conductivity of > 100 W/(m*K), the at least one second region preferably comprises a material with a thermal conductivity of > 40 W/(m*K) . The area of the at least one first region is 66-99% with respect to the bottom area of the die. The at least one first region (21) comprises a die-attach material comprising at least one metal. Therewith at least mechanical and material properties, such as (visco)elastic properties, of the respective elements (e.g. substrate, die, and attachment layer), and thermal coefficient of expansion can be matched to one and another much better. It is noted that typically a die attachment layer may have good (visco)elastic properties, which allow to mitigate stresses, but provides limited thermal conductivity, which may cause the die or part thereof to become to warm, or vice versa. By carefully selecting respective attachment materials a much better match in view of the (visco)elastic properties and thermal conductivity properties of the respective elements can be made. It is noted that the inner die attachment material (IDA) and outer die attachment material (ODA) are considered to be viscoplastic/Viscoelastic, which both have a time and temperature dependency, in nature and not being elastic, which is considered time and temperature independent. It is also considered that the die and substrate are elastic in nature. With the present invention stress is mitigated. For instance, in an embodiment the present integrated circuit comprises a substrate 10 with a first thermal coefficient of expansion (TCEi), wherein thermal coefficients relate to linear expansion, on the substrate an attachment layer 20, and on the attachment layer a die 30 with a second thermal coefficient of expansion (TCE2), characterized in that the die attachment layer comprises at least one first region 21 with a third thermal coefficient of expansion (TCE3) and at least one second region 22 with a fourth thermal coefficient of expansion (TCE4), wherein the first region may be considered the inner region and the second region the outer region, wherein the at least one first region is located centrally on the substrate, which may be considered as inner die, wherein the at least one second region is located eccentric, such as at a side, at a part of a side, or at a corner, which may be considered as outer die, wherein the values of the respective third thermal coefficient of expansion (TCE3) and fourth thermal coefficient of expansion (TCE4) are each individually in between the values of the first thermal coefficient of expansion (TCEi) and the second thermal coefficient of expansion (TCE2). It is noted that typically the thermal coefficient of expansion of the substrate TCEi is larger than the thermal coefficient of expansion of the die TCE2, but sometimes TCE2>TCEI). Typically the TCEs are taken at room temperature (about 20 °C). The present invention relate to a combination of at least two die-attach materials to attach the die onto a substrate, which helps in preventing package failures, especially failures occurring close to the die corner, and failures or lack of control that appear over time when the IC is used under operating conditions. The first die-attach material is typically provided under a more central region of the die, such as except under the corner regions thereof. The second die-attach material may then occupy the corner and edges of the die. The second (or corner) die-attach material may further a lower modulus, a TCE closer to that of the substrate (s), and a high toughness. It is thus found that a combination of two die-attach materials to attach the die on to a substrate helps in preventing the package failures especially occurring close to the die corner. The first die-attach material is under the entire region of the die except the corner regions. The second die-attach material occupies the comer and edges of the die. Thermal conductivities may be measured using a standard test, such as ASTM 5334, IEEE 442, such as by using a TEMPOS machine. Some examples of designs of the two die-attach materials are shown in the figures, such as in figs. 5a-e. The figures show application of the die attachment material on the substrate before actual attachment of the die; once the die is attached the attachment material spreads out over a surface of the substrate and likewise die. Dot-like application of the second material is preferred, as a risk of gas entrapment is reduced. In an alternative embodiment, the present integrated circuit may comprise at least one first region (21) with a first elastic modulus (EMi), and at least one second region (22) with a second elastic modulus (EM2), wherein the first elastic modulus (EMi) of the at least one first region is higher than the second elastic modulus (EM2) of the at least one second region, and preferably wherein the first elastic modulus (EMi) of the at least one first region is lower than an elastic modulus of the die, and preferably wherein the second elastic modulus (EM2) of the at least one second region is higher than an elastic modulus of the substrate. The respective elastic moduli each individually are both selected from a Young’s modulus, a bulk modulus, viscoelastic modulus, and/or a volumetric modulus, that is are both of the same type. The elastic modulus, such as the Young’s modulus, is typically expressed in GPa, and may be determined using a standard test, such as EN 10002-1, ASTM E8 and ASTM El 11, e.g. using an Ametek. It is noted that inaccuracies in testing in practice do not matter much, as the present invention is more concerned with relative values (between elements) than absolute values. Even further the two above embodiments may be combined. In view thereof it is noted that the terms “higher” and “larger” typically relate to more than 5% higher or larger (or likewise lower and smaller), in particular 10-250% larger, more in particular 20-150% larger; this is applicable for both the EM and the TCE, in each individual case.

The at least one second region comprises a die-attach material selected from heat assisted attach materials, pressure-based attach materials, pressure-less attach materials, thermohardening attach materials, such as epoxy resins, curing attach materials, polymer based attach materials, resin based attach materials, fibres, nanoparticles, and combinations thereof, in particular wherein the die-attach material comprises a dielectric material, in particular particles of dielec- trie material, embedded in a matrix of polymeric material. The second region comprises a die- attach material which may be considered to be more polymeric based, whereas the first region comprises a die-attach material which is mainly metal based; the two materials are therefore considerably different.

In a second aspect the present invention relates to a method for die bonding comprising providing a substrate with a first thermal coefficient of expansion (TCEi), providing an attachment layer with at least one first region with a third thermal coefficient of expansion (TCE3) and at least one second region with a fourth thermal coefficient of expansion (TCE4) on the substrate, and attaching a die, with a second thermal coefficient of expansion (TCE2), to the attachment layer, wherein the values of the respective third thermal coefficient of expansion (TCE3) and fourth thermal coefficient of expansion (TCE4) are each individually in between the values of the first thermal coefficient of expansion (TCEi) and the second thermal coefficient of expansion (TCE2), and wherein the value of the fourth thermal coefficient of expansion (TCE4) is in between the values of the third thermal coefficient of expansion (TCE3) and the first thermal coefficient of expansion (TCEi). Therewith the present integrated circuit can be obtained. Typically the first inner die-attach material is dispensed, printed (e.g. stencil) or applied as a preform film, and the second outer die-attach is deposited via non-contact deposition technology at the corner areas of the die (e.g. via dispensing). These steps may be interchanged. So typical dispensing and printing processes can be used to achieve any die-attach designs. No special equipment’ s is therefore needed. Then, using e.g. a die-bonder machine, the die may be placed on the two die-attachment materials and pushed such that the two materials will spread out and cover an entire area under the die. The inner die material (IDA) will typically cover the entire area under the die except the die edges and corners, whereas the outer die material (ODA) will then cover the edges and corners. The IDA and ODA regions typically touch one and another, and some, typically minor or no, mixing of the two materials may occur there. It is found that as such the ODA material can absorb the thermo-mechanical stresses while the IDA material provides for thermal and electrical paths. In comparison, for conventional WLCSP technology, the bumps serve as electrical and thermal path while the underfill material absorbs the stresses.

In view of viscoelasticity the following is noted. Unlike purely elastic substances, a viscoelastic substance has an elastic component and a viscous component. The viscosity of a viscoelastic substance gives the substance a strain rate dependence on time. Purely elastic materials do not dissipate energy (heat) when a load is applied, then removed. However, a viscoelastic substance dissipates energy when a load is applied, then removed. Hysteresis is observed in the stress-strain curve, with the area of the loop being equal to the energy lost during the loading cycle. Since viscosity is the resistance to thermally activated plastic deformation, a viscous material will lose energy through a loading cycle. Plastic deformation results in lost energy, which is uncharacteristic of a purely elastic material's reaction to a loading cycle.

The present invention provides a solution to one or more of the above mentioned problems and overcomes drawbacks of the prior art.

Advantages of the present description are detailed throughout the description. DETAILED DESCRIPTION OF THE INVENTION

In an exemplary embodiment of the present integrated circuit the value of the fourth thermal coefficient of expansion (TCE4) is in between the values of the third thermal coefficient of expansion (TCE3) and the first thermal coefficient of expansion (TCEi).

In an exemplary embodiment of the present integrated circuit the value of the fourth thermal coefficient of expansion (TCE4) is in between the values of the third thermal coefficient of expansion (TCE3) and the second thermal coefficient of expansion (TCE2).

As such one can modify and adapt the thermal coefficients in view of thermal properties of die and substrate, respectively, such that problems of the prior art are overcome.

In an exemplary embodiment of the present integrated circuit the at least one first region comprises a material with a thermal conductivity of > 150 W/(m*K).

In an exemplary embodiment of the present integrated circuit the at least one second region comprises a material with a thermal conductivity of > 50 W/(m*K).

It is found important, in particular with special IC’s such as high power IC’s, photonics, and Vertical Cavity Surface Emitting Laser (VCSEL), to have a suited selection of thermal conductivities, in order to remove heat in a well controlled manner.

For better understanding some information is given below:

Die (Si & SiC) : 120 - 450 W/(m*K) Substrate (Cu) :401 W/(m*K)

Ag sinter (centre DA) :50 - 400 W/(m*K) (Depending on the % Sintering); Avg: -250

Ag filled polymer DA :50 W7(m*K)

It is noted that a typical thermal conductivity in W/(m K) range at room temperature, of a die, such as comprising Si, and at least one of silicon oxide, silicon nitride, and silicon carbide, is in the order of 120 - 450, which is a rather large range, that of a substrate, such as Cu, is around 400, whereas the attachment material with a % is in the range 50 - 400, and an Ag filled polymer DA is around 50 (all in W/(m*K)).

In an exemplary embodiment of the present integrated circuit the area of the at least one first region is 66-99% with respect to the bottom area of the die, preferably 75-95% thereof, more preferably 80-92% thereof, such as 85-90% thereof. It is found important, in particular with special IC’s such as high power IC’s, photonics, and Vertical Cavity Surface Emitting Laser (VCSEL), to have a suited selection of areas, in particular those of the at least one first region, in order to remove heat in a well controlled manner.

In an exemplary embodiment of the present integrated circuit the bottom area of the die is from 1 mm²-400 mm², preferably 2 mm²- 100 mm², such as 5 mm²-60 mm².

In an exemplary embodiment of the present integrated circuit a shape (top view) of the at least one second region is selected from circular, rectangular, square, L-shape, and V-shape, series thereof, matrices thereof, and combinations thereof.

In an exemplary embodiment of the present integrated circuit the at least one first region comprises a die-attach material selected from metals, wherein the metal is selected from Ag, Cu, Au. An amount of metal may vary from 1-35%, such as 2-20%, e.g. Ag. In a mass:mass ratio the amount of metal is typically >50 wt.%, in particular >80 wt.%, more in particular > 90 wt.%, such as > 95 wt.%. It is noted that the specific mass of the metal is typically at least ten times larger than that of an optional polymeric matrix.

In an exemplary embodiment of the present integrated circuit the at least one second region comprises a dielectric material, in particular particles of dielectric material, embedded in a matrix of polymeric material, wherein the dielectric material is selected from nitrides, oxides, carbides, sulphides, and combinations thereof, and/or wherein the dielectric material comprises as counterion a metal selected from Si, B, Al, Ga, In, and combinations thereof, such as AIN, BN, and SisN-t, in particular hexagonal BN, cubic BN, and wurtzite BN, and/or wherein the particles of dielectric material have a size of 50 nm-20 pm, in particular 100 nm-5 pm, such as 200 nm-2 pm, and/or wherein the matrix of polymeric material is selected from poly-imides, from Poly benzoxazines, and from polyesters, in particular from polyepoxides.

In an exemplary embodiment of the present integrated circuit the attach material is lead free.

In an exemplary embodiment of the present integrated circuit the attachment layer has a thickness of 5-250 pm, preferably 10-100 pm, more preferably 20-80 pm, such as 30-50 pm.

In an exemplary embodiment of the present integrated circuit the attachment layer extends up to a side of the die, preferably forming a fillet 27 of up to 97%, such as of 75-95%. Therewith the die is well embedded and a good heat dissipation is provided.

In an exemplary embodiment of the present integrated circuit the die an IC with an output power of >50 W, such as > 100 W, such as a Low power die with 80-100W output, a Medium Power die with 110-200W power output, or a high power die with 200-270W output, or wherein the present integrated circuit relates to a photonics application, with an improved heat flow from die to substrate; or wherein the present integrated circuit relates to an IC requiring precise temperature control thereof, such as a VCSEL circuit.

In an exemplary embodiment of the present integrated circuit the substrate comprises a material selected from metals, such as copper, and alloys thereof, dielectric materials, such as metal oxides, laminates, such as epoxy-based laminates, epoxy-blends laminates, tape substrates, preferably comprising a polymer, such as poly-imide, ceramic materials, comprising fibres, such as fibre glass, multi-layers comprising two or more of the aforementioned materials, and combinations thereof.

In an exemplary embodiment of the present integrated circuit the die attach layer comprises a cavity 28 for receiving the die, preferably a cavity adapted to outer dimensions of the die.

In an exemplary embodiment of the present method the at least one first region is provided and thereafter the at least one second region is provided, or vice versa.

In an exemplary embodiment of the present method the at least one first region and the at least one second region each individually are provided by fluid dispensing, or by printing, or by stencilling, or by screen printing, or by depositing, or by preforming, or by a combination thereof.

In an exemplary embodiment of the present method the at least one first region is provided in the form of at least one central bar-shaped volume.

In an exemplary embodiment of the present method the at least one first region is provided with at least one first order side branch, preferably at least one first order side branch in every corner, optionally with at least one further first order side branch at each longitudinal side of the substrate, wherein first order side branches may be oriented in-plane perpendicular to the at least one central bar-shaped volume, or under an in-plane angle therewith, such as under an angle of 30-60 degrees.

In an exemplary embodiment of the present method the at least one first region is provided with at least one second order side branch of the first order side branch.

In an exemplary embodiment of the present method the at least one first region is provided centrally on the substrate, such as over an area of 5-50% of the substrate, preferably 10-40% of the area, such as 20-35%.

In an exemplary embodiment of the present method the at least one second region is provided eccentric, such as at a side, at a part of a side, or at a comer, such as over an area of 1-15% of the substrate, preferably 2-10% of the area, such as 4-8%.

In an exemplary embodiment of the present method the die is attached by applying pressure, or by applying heat, or by applying curing, or sintering, or diffusion, or a combination thereof.

The invention will hereafter be further elucidated through the following examples which are exemplary and explanatory of nature and are not intended to be considered limiting of the invention. To the person skilled in the art it may be clear that many variants, being obvious or not, may be conceivable falling within the scope of protection, defined by the present claims.

FIGURES

Figures 1-3 show a cross-sections of the present device.

Figures 4a, b shows a top view of the present device.

Figures 5a-e show initial patterns of regions 21 and 22 (top view).

Figures 6a-b show ab overview (6a) and zoomed-in section (6b) at the comer of the die) with two die-attach materials (top view).

DETAILED DESCRIPTION OF FIGURES

In the figures:

10 substrate

20 die attachment layer

21 first region

22 second region

27 fillet

28 cavity

30 die

Figure 1 shows a cross-section of the present device, with a substrate 10, a die attachment layer 20, and a die 30.

Figure 2 shows a cross-section of the present device, with a substrate 10, a die attach- ment layer 20, and a die 30. Also a cavity 28 is provided for receiving the die.

Figure 3 shows a cross-section of the present device, with a substrate 10, a die attachment layer 20, and a die 30. Also a fillet 27 is provided for embedding the die, and for dissipating heat. The fillet as shown , from top to bottom, gradually increases in thickness. It also extends exactly to the top surface of the die, and hence is considered to be 100% in height.

In figure 4a an initial die attachment material configuration is shown, prior to attaching the die. On substrate 10 a first region 22 and several second regions 21 of die attachment material are provided. After attaching the die (the die being virtually removed) the first region 21 is spread out over the central region of the substrate, whereas the second regions are slightly increased in surface are size and are position at the sides and corners.

Figures 5a-e show initial patterns of regions 21 and 22, with small and larger dots, and with thin and thick L-shaped corner sections.

Figures 6a-b show ab overview (6a) and zoomed-in section (6b) at the comer of the die) with two die-attach materials. Initially, the double Y shape is stencil printed with IDA (Ag sinter material) and then the ODA material is dispensed in the shape of dots as shown in pic.5c (Note: we can use any shape in 5.a-c). Later, the die is placed on the ODA, IDA patterns and pushed such that both ODA & IDA materials gets squeezed and flow out and cover the entire die area under the die. The IDA material covers the four comers of the die and forms a filled. While, the ODA forms a fillet on the edges of the die. Note: 6b pic. is zoom in of 6a at the ODA material. Then, the sintering/curing is done by increasing the temperature and time. After sintering the IDA & ODA changes from liquid to solid/stiff materials.

A recipe for die attachment is as follows:

Inner die attach application:

Stencil printing Heraeus DA295A (20-46 GPa) and/or Tanaka TS-9853 (14 GPa) Stencil thickness 75 um

Outer die attach application:

Needle dispensing process (contact dispensing) Dupont KA802 (2.5 GPa)

Needle gauge 27 gauge

Dot size controlled or varied by: o Dispense pressure 1 - 2 bars o Dispense time 200 - 500 ms

Inner die attach is applied before outer die attach, this is because of drying behavior of the outer die attach material.

Die Attachment pressure:

Placement pressure of die is approx. 10 to 20 grams of force per mm²

Sintering profile:

A sintering temperature is gradually increased to about 200 C in about 120 minutes, maintained at said temperature during about 60 minutes, and then decreased during about 60 minutes to room temperature.

In a further recipe the following material may be selected: base substrate: copper, silver, gold die attach material: aurofuse, tanaka TS-9853, Heraeus mAgic Paste, ASP338-28 F1510, Heraeus DA295A, KA802 die: silicon, silicon carbide dielectric fillers: AIN, BN, SiN organics: Polyimide, epotek 302-3M

Claims

1. Integrated circuit comprising a substrate (10), on the substrate an attachment layer (20), and on the attachment layer a die (30), the die attachment layer comprises at least one first region (21) comprising a first attachment material and at least one second region (22) comprising a second attachment material different from the first attachment material, wherein the at least one first region (21) is located centrally on the substrate, wherein the at least one second region (22) is located eccentric, such as at a side, at a part of a side, or at a corner, characterized in that the at least one first region (21) comprises a material with a thermal conductivity of > 100 W/(m*K), and wherein the area of the at least one first region (21) is 66-99% with respect to the bottom area of the die, wherein the at least one first region (21) comprises a die-attach material comprises at least one metal, wherein the at least one second region comprises a die-attach material selected from heat assisted attach materials, pressure-based attach materials, pressure-less attach materials, thermohardening attach materials, such as epoxy resins, curing attach materials, polymer based attach materials, resin based attach materials, fibres, nanoparticles, and combinations thereof.

2. Integrated circuit according to claim 1, wherein the substrate (10) has a first thermal coefficient of expansion (TCEi), wherein the die (30) has a second thermal coefficient of expansion (TCE2), wherein the at least one first region (21) has a third thermal coefficient of expansion (TCE3), wherein the at least one second region (22) has a fourth thermal coefficient of expansion (TCE4), and wherein the values of the respective third thermal coefficient of expansion (TCE3) and fourth thermal coefficient of expansion (TCE4) are each individually in between the values of the first thermal coefficient of expansion (TCEi) and the second thermal coefficient of expansion (TCE2).

3. Integrated circuit according to claim 1 or 2, wherein the at least one first region (21) has a first elastic modulus (EMi), and at least one second region (22) has a second elastic modulus (EM2), wherein the first elastic modulus (EMi) of the at least one first region is higher than the second elastic modulus (EM2) of the at least one second region, and preferably wherein the first elastic modulus (EMi) of the at least one first region is lower than an elastic modulus of the die, and preferably wherein the second elastic modulus (EM2) of the at least one second region is higher than an elastic modulus of the substrate, wherein the respective elastic moduli each individually are both selected from a Young’s modulus, a bulk modulus, viscoelastic modulus, and/or a volumetric modulus.

4. Integrated circuit according to claim 2 or3, wherein the value of the fourth thermal coefficient of expansion (TCE4) is in between the values of the third thermal coefficient of expansion (TCE3) and the first thermal coefficient of expansion (TCEi), or wherein the value of the fourth thermal coefficient of expansion (TCE4) is in between the values of the third thermal coefficient of expansion (TCE3) and the second thermal coefficient of expansion (TCE2).

5. Integrated circuit according to any of claims 1-4, wherein the at least one second region (22) comprises a material with a thermal conductivity of > 40 W/(m*K), preferably > 50 W/(m*K).

6. Integrated circuit according to any of claims 1-5, wherein the area of the at least one first region (21) is , 75-95% with respect to the bottom area of the die, preferably 80-92% thereof, such as 85-90% thereof, and/or wherein the bottom area of the die is from 1 mm²-400 mm², preferably 2 mm²-100 mm², such as 5 mm²-60 mm².

7. Integrated circuit according to any of claims 1-6, wherein a shape in a top view of the at least one second region (22) is selected from circular, rectangular, square, L-shape, and V-shape, series thereof, matrices thereof, and combinations thereof.

8. Integrated circuit according to any of claims 1-7, wherein the at least one first region (21) comprises a die-attach material selected metals, wherein the metal is selected from Ag, Cu, Au, and/or wherein the amount of metal in the fie-attach material of the first region on a mass:mass ratio is >50 wt.%, in particular >80 wt.%, more in particular > 90 wt.%, such as > 95 wt.%, and/or wherein the at least one second region comprises particles of dielectric material, embedded in a matrix of polymeric material, wherein the dielectric material is selected from nitrides, oxides, carbides, sulphides, and combinations thereof, and/or wherein the dielectric material comprises as counterion a metal selected from Si, B, Al, Ga, In, and combinations thereof, such as AIN, BN, and Si3N4, and/or wherein the particles of dielectric material have a size of 50 nm-20 pm, in particular 100 nm-5 pm, such as 200 nm-2 pm, and/or wherein the matrix of polymeric material is selected from poly-imides, from poly benzoxazines, and from polyesters, in particular from polyepoxides, and/or wherein the attach material is lead free, and/or wherein the attachment layer has a thickness of 5-250 pm, preferably 10-100 pm, more preferably 20-80 pm, such as 30-50 pm.

9. Integrated circuit according to any of claims 1-8, wherein the attachment layer extends up to a side of the die, preferably forming a fillet (27) of up to 97%, such as of 75-95%.

10. Integrated circuit according to any of claims 1-9, wherein the die is an IC with an output power of >50 W, such as > 100 W, such as a Low power die with 80-100W output, a Medium Power die with 110-200W power output, or a high power die with 200-270W output, or wherein the present integrated circuit relates to a photonics application, with an improved heat flow from die to substrate; or wherein the present integrated circuit relates to an IC requiring precise temperature control thereof, such as a VCSEL circuit.

11. Integrated circuit according to any of claims 1-10, wherein the substrate comprises a material selected from metals, such as copper, and alloys thereof, dielectric materials, such as metal 14 oxides, laminates, such as epoxy-based laminates, epoxy-blends laminates, tape substrates, preferably comprising a polymer, such as poly-imide, ceramic materials, comprising fibres, such as fibre glass, multi-layers comprising two or more of the aforementioned materials, and combinations thereof.

12. Integrated circuit according to any of claims 1-10, wherein the die attach layer comprises a cavity (28) for receiving the die, preferably a cavity adapted to outer dimensions of the die.

13. Method of die bonding comprising providing a substrate, such as with a first thermal coefficient of expansion (TCEi), providing an attachment layer with at least one first region (21) comprising a first attachment material, such as with a third thermal coefficient of expansion (TCE3), and at least one second region (22) comprising a second attachment material different from the first attachment material, such as with a fourth thermal coefficient of expansion (TCE4) on the substrate, wherein the at least one first region is located centrally on the substrate, wherein the at least one second region is located eccentric, and attaching a die, such as with a second thermal coefficient of expansion (TCE2), to the attachment layer, preferably wherein the values of the respective third thermal coefficient of expansion (TCE3) and fourth thermal coefficient of expansion (TCE4) are each individually in between the values of the first thermal coefficient of expansion (TCEi) and the second thermal coefficient of expansion (TCE2), and wherein the value of the fourth thermal coefficient of expansion (TCE4) is in between the values of the third thermal coefficient of expansion (TCE3) and the first thermal coefficient of expansion (TCEi), wherein the at least one first region comprises a material with a thermal conductivity of > 100 W/(m*K), and wherein the at least one second region comprises a material with a thermal conductivity of > 40 W/(m*K), and wherein the area of the at least one first region is 66-99% with respect to the bottom area of the die.

14. Method of die bonding according to claim 13, wherein the at least one first region is provided and thereafter the at least one second region is provided, or vice versa.

15. Method of die bonding according to claim 13 or 14, wherein the at least one first region and the at least one second region each individually are provided by fluid dispensing, or by printing, or by stencilling, or by screen printing, or by depositing, or by preforming, or by a combination thereof.

16. Method of die bonding according to any of claims 13-15, wherein the at least one first region is provided in the form of at least one central bar-shaped volume, optionally with at least one first order side branch, preferably at least one first order side branch in every comer, optionally with at least one further first order side branch at each longitudinal side of the substrate, wherein first order side branches may be oriented in-plane perpendicular to the at least one central barshaped volume, or under an in-plane angle therewith, such as under an angle of 30-60 degrees, and 15 optionally with at least one second order side branch of the first order side branch.

17. Method of die bonding according to any of claims 13-16, wherein the at least one first region is provided centrally on the substrate, such as over an area of 5-50% of the substrate, preferably 10-40% of the area, such as 20-35%, and/or wherein the at least one second region is provided eccentric, such as at a side, at a part of a side, or at a comer, such as over an area of 1-15% of the substrate, preferably 2-10% of the area, such as 4-8%.

18. Method of die bonding according to any of claims 13-17, wherein the die is attached by applying pressure, or by applying heat, or by applying curing, or sintering, or diffusion, or a com- bination thereof.