KR102541854B1 - 양측들에서 냉각되는 회로 - Google Patents

양측들에서 냉각되는 회로 Download PDF

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KR102541854B1
KR102541854B1 KR1020187012687A KR20187012687A KR102541854B1 KR 102541854 B1 KR102541854 B1 KR 102541854B1 KR 1020187012687 A KR1020187012687 A KR 1020187012687A KR 20187012687 A KR20187012687 A KR 20187012687A KR 102541854 B1 KR102541854 B1 KR 102541854B1
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ceramic
circuit
substrate
metallization
component
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KR1020187012687A
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KR20180066133A (ko
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롤란드 딜슈
하랄트 크레스
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세람테크 게엠베하
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Abstract

본 발명은 상부측(1b) 및 하부측(1a)을 갖는 제1 세라믹 기판(1)을 포함하는 컴포넌트(9)에 관한 것이며, 금속화부(2)가 상부측(1b) 상에 적용되고, Si 회로(4)의 하부측이 연결 수단(3)을 통해 금속화부 상에 장착된다. Si 회로(4)가 높은 열 전도성 및 동시에 높은 전기 전도성을 갖는 엘리먼트들에 의해 양측에서 냉각되도록 하기 위해, 그리고 어셈블리의 효율이 증가되도록 하기 위해, 본 발명에 따라, 연결 수단(5)이 Si 회로(4)의 상부측(1b) 상에 적용되고, 세라믹 평면 기판(6)의 하부측이 연결 수단 상에 부착되고, 제2 세라믹 기판(8)은 금속화부(7)를 통해 평면 기판(6) 상에 배열되고, 세라믹 평면 기판(8)은 냉각 수단을 운반하기 위한 금속으로 채워진 열 전기 비아들(11) 및/또는 냉각 덕트들을 포함한다.

Description

양측들에서 냉각되는 회로
본 발명은 상부측 및 하부측을 갖는 제1 세라믹 기판으로 구성되는 컴포넌트에 관한 것이며, 금속화부(metallization)가 상부측에 적용되고, 전자 모듈의 하부측이 연결 수단을 통해 금속화부 상에 장착된다.
Al2O3 또는 AlN의 세라믹 기판들에는 적어도 한 측의 금속화부(DCB-Cu, 두꺼운 막 Cu, Ag, W-Ni-Au)가 붙어 있고(carry), 차례로, Si 회로가 압력, 땜납(solder), 소결된 은(sintered silver), 은 접착제(silver glue) 등에 의해 금속화부 상에 고정되는 구성들이 알려져 있다.
기판의 제2 측 상에서, 예컨대, 알루미늄 등으로 제조된 히트 싱크가 접착되거나 납땜되는 추가의 금속화부 표면들이 존재할 수 있다. 따라서, Si 회로들은 전기 절연 히트 싱크와 최대로(at most) 한 측에서 연결된다. Si 회로의 상부 자유 측은, 최대로, 가스 냉각된다. 'Si 회로'는 또한, 일반적으로, 칩 또는 트랜지스터를 의미한다.
본 발명의 목적은, Si 회로가 양측들, 즉, 자신의 하부측 및 자신의 상부측 둘 모두에서 냉각되는 방식으로, 제1항의 전제부에 따른 컴포넌트를 개선하는 것이다. 더 높은 열 전도성 및 또한 더 높은 전기 전도성을 갖는 엘리먼트들에 의한 양측들 상에서의 Si 회로의 냉각은 어셈블리의 효율을 증가시키도록 의도된다.
본 발명에 따라, 이러한 목적은 제1항의 특징들을 갖는 컴포넌트에 의해 달성된다.
연결 수단이 Si 회로의 상부측 상에 적용되고, 평면 기판의 하부측이 Si 회로의 상부측 상에 적용되고, 제2 세라믹 기판이 금속화부를 통해 평면 기판 상에 배열되고, 세라믹 평면 기판이 금속으로 채워진 열-전기 스루-연결부들(thermo-electric through-connections)(비아들) 및/또는 냉각 수단을 운반하기 위한 냉각 덕트들(cooling ducts)을 포함한다는 사실로 인해, Si 회로는 양측들, 즉, 자신의 하부측 및 자신의 상부측 둘 모두에서 냉각된다. 더 높은 열 전도성 및 또한 더 높은 전기 전도성을 갖는 엘리먼트들에 의한 양측들 상의 Si 회로의 냉각은 Si 회로의 어셈블리의 효율을 증가시키도록 의도된다. 세라믹 평면 기판의 비아들 내의 금속은 제2 기판의 금속화부, 및 Si 회로 상에 위치된 연결 수단 둘 모두 위에 놓인다.
Si 회로는 바람직하게는 칩 또는 트랜지스터이다.
금속화부들은 바람직하게는 DCB-Cu, 두꺼운 막 Cu, Ag 또는 W-Ni-Au로 구성되고 그리고/또는 세라믹 기판과 소결된 금속화부들이다. 소결된 금속화부들은 세라믹과 밀접하게 연결되고, 이로써 Si 회로에서 세라믹으로의 우수한 열 전달을 입증한다.
연결 수단은 바람직하게는 땜납, 소결된 은 또는 은 접착제이다.
본 발명에 따른 실시예에서, 비아들은 Cu 또는 Ag로 제조되고, 기판들은 질화 알루미늄으로 제조된다. 질화 알루미늄은 높은 열 전도성을 갖는다.
일 실시예에서, 핀들(fins) 등과 같은 냉각 엘리먼트들은 제1 세라믹 기판의 하부측 상에 배열된다.
양측들 상에서의 더 양호한 열 발산(heat dissipation)은, 연결 수단을 통해 Si 회로의 자유 상부측과 접촉하는, 금속으로 채워진 비아들을 갖는 세라믹 평면 기판에 의해 달성될 수 있다. 이러한 평면 기판은, 예컨대, Cu 또는 Ag로 채워진 열-전기 스루-연결부들(비아들)을 포함한다. 질화 알루미늄이 기판 재료로서 선택되면, 약 4.7 ppm/K인 질화 알루미늄의 팽창 계수는 약 4.2 ppm/K인, 칩의 실리콘의 팽창 계수에 근접하다.
이러한 비아 세라믹들(평면 기판들)은, 금속화된 세라믹 기판, 비아 땜납, 은 페이스트(silver paste) 또는 제2 세라믹 기판 상의 은 소결된 층을 사용하여, 그리고/또는 구리 페이스트를 금속화된 상부 기판의 구리층으로 직접적으로 버닝(burning)함으로써, Si 회로의 한 측 및 다른 측 둘 모두에 연결될 수 있다.
열 발산을 추가로 증가시키기 위해, 세라믹 평면 기판들 대신에, 액체가 흐르는 세라믹 냉각기들, 또는 세라믹 핀들을 갖는 등가물들이 사용될 수 있다.
도면들은 종래 기술(도 1) 및 본 발명에 따른 컴포넌트(도 2)를 도시한다.
도 1은 종래 기술에 따른 컴포넌트(9)를 도시한다. 컴포넌트는 상부측(1b) 및 하부측(1a)을 갖는 제1 세라믹 기판(1)으로 구성되고, 금속화부(2)가 상부측(1b) 상에 적용되고, Si 회로(4)의 하부측이 연결 수단(3)을 통해 금속화부(2) 상에 장착된다. 본 발명에 따라, 세라믹 평면 기판(6)의 하부측은 연결 수단(5)을 통해 Si 회로(4) 및/또는 그의 상부측 상에 부착되고, 제2 세라믹 기판(8)은 금속화부(7)를 통해 평면 기판(6) 상에 배열되고, 세라믹 평면 기판(6)은 금속으로 채워진 열-전기 스루-연결부들(비아들)(11) 및/또는 냉각 수단을 운반하는데 사용되는 냉각 덕트들을 포함한다.
세라믹 기판들(1, 8)은 바람직하게는 평판-형상이고, 바람직하게는 매우 높은 열 전도성을 갖는 질화 알루미늄으로 제조된다.
금속화부들은 바람직하게는 DCB-Cu, 두꺼운 막 Cu, Ag 또는 W-Ni-Au로 구성되고 그리고/또는 세라믹 기판(1, 8)과 소결된다.
Si 회로(4)는 칩 또는 트랜지스터로서 설계된 실리콘 회로이다.
연결 수단(3, 5)은 바람직하게는 땜납, 소결된 은 또는 은 접착제이다.
스루- 연결부들(11)은 예로서 Cu 또는 Ag로 제조된다.
도 2에 도시되지 않은 냉각 엘리먼트들은 바람직하게는 제1 세라믹 기판(1)의 하부측(1a) 상에 배열된다. 이러한 냉각 엘리먼트들은 공기 냉각을 위해 사용되는 핀들일 수 있다. 그러나, 그들은 또한 액체를 운반하는 냉각 상자들일 수 있다.
세라믹 평면 기판(6)은 Si 회로(4)의 폐열(waste heat)을 세라믹 기판(8)으로 유인하는데 사용되고, 또한 Si 회로(4)를 금속화부(7)에 전기적으로 커플링하는데 사용될 수 있다. 평면 기판(6)은 또한 바람직하게는 질화 알루미늄으로 제조된다. 전기 연결부의 금속으로 채워진 열-전기 스루-연결부들(비아들)(11)에 의해, 폐열이 운반되고, 전기적 연결부가 제조된다. 스루-연결부들(비아들)(11)은 바람직하게는 평면 기판(6)의 표면에 직각으로 이어진다.
참조 번호(10)는 전기 연결부들을 생성하는데 사용되는 본드 와이어들을 나타내기 위해 도면들 둘 모두에서 사용된다.

Claims (6)

  1. 상부측(1b) 및 하부측(1a)을 갖는 제1 세라믹 기판(1)으로 구성된 컴포넌트(9)로서,
    상기 상부측(1b) 상에 금속화부(metallization)(2)가 적용되고, 상기 금속화부(2) 상에 연결 수단(3)을 통해 Si 회로(4)의 하부측이 장착되고,
    상기 Si 회로(4)의 상부측 상에 연결 수단(5)이 적용되고, 상기 연결 수단(5) 상에 세라믹 평면 기판(ceramic flat substrate)(6)의 하부측이 부착되고,
    상기 세라믹 평면 기판(6) 상에 금속화부(7)를 통해 제2 세라믹 기판(8)이 배열되고,
    상기 세라믹 평면 기판(6)은 금속으로 채워진 열-전기 스루-연결부들(thermo-electric through-connections)(11)을 포함하고,
    상기 금속으로 채워진 열-전기 스루-연결부들(11)은 구리로 채워지고, 상기 세라믹 평면 기판(6)은 질화 알루미늄으로 제조되는,
    컴포넌트(9).
  2. 제1항에 있어서,
    상기 Si 회로(4)는 실리콘 회로, 칩 또는 트랜지스터인,
    컴포넌트(9).
  3. 제1항에 있어서,
    상기 금속화부들(2, 7) 모두는 DCB-Cu, 두꺼운 막 Cu, Ag 또는 W-Ni-Au로 제조되는,
    컴포넌트(9).
  4. 제1항에 있어서,
    상기 금속화부들(2, 7) 모두는 상기 제1 세라믹 기판(1) 또는 제2 세라믹 기판(8)과 함께 소결된 금속화부들인,
    컴포넌트(9).
  5. 제1항에 있어서,
    상기 연결 수단(3, 5)은 땜납(solder), 소결된 은(sintered silver) 또는 은 접착제(silver glue)인,
    컴포넌트(9).
  6. 제1항 내지 제5항 중 어느 한 항에 있어서,
    상기 제1 세라믹 기판(1)의 하부측(1a)에 냉각 엘리먼트들이 배열되는,
    컴포넌트(9).
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US20180315679A1 (en) 2018-11-01
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WO2017060224A1 (de) 2017-04-13
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