JP4071204B2 - 多層セラミック基板の製造方法 - Google Patents
多層セラミック基板の製造方法 Download PDFInfo
- Publication number
- JP4071204B2 JP4071204B2 JP2004054271A JP2004054271A JP4071204B2 JP 4071204 B2 JP4071204 B2 JP 4071204B2 JP 2004054271 A JP2004054271 A JP 2004054271A JP 2004054271 A JP2004054271 A JP 2004054271A JP 4071204 B2 JP4071204 B2 JP 4071204B2
- Authority
- JP
- Japan
- Prior art keywords
- green sheet
- ceramic substrate
- multilayer ceramic
- green
- support
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/005—Punching of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
- Y10T156/1056—Perforating lamina
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
- Y10T156/1056—Perforating lamina
- Y10T156/1057—Subsequent to assembly of laminae
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49163—Manufacturing circuit on or in base with sintering of base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
- Y10T428/24322—Composite web or sheet
Description
(1)互いに異なる電気的特性を与えるセラミック材料をそれぞれ含む複数種類のセラミック層を積層する方法。例えば、互いに異なる誘電率を有する誘電体セラミック材料をそれぞれ含む複数種類のセラミック層と磁性体セラミック材料を含むセラミック層とを積層するもの(例えば特許文献1を参照。)。
(実施例2)
2 支持体
3 打ち抜き部分
4 パンチャー(打ち抜き加工機)
5 金型
6 第2グリーンシート
6a 第2グリーンシート(打ち抜き部分の残り部分)
6b 第2グリーンシート(打ち抜き部分)
7 異材質複合グリーンシート
9 ビアホール
10 ビア
11 電極
12 異材質複合グリーンシート(導体ペースト印刷後)
21,30 第1グリーンシートの焼成層
22,31,35 第2グリーンシートの焼成層
23,36 導体層(外電極層)
24,37 内部導体層
32 配線層
33 端子
34 スルーホール
100,200 多層セラミック基板
Claims (9)
- シート状の支持体に載せられた第1グリーンシートの所定部分を打ち抜く工程と、
前記支持体に載せられた第1グリーンシートに第2グリーンシートを重ねて仮接着する工程と、
前記第2グリーンシートを前記支持体に載せられた第1グリーンシートの打ち抜き部分に嵌め込んで異材質複合グリーンシートを形成する工程と、
前記支持体に載せられた第1グリーンシートの表面に仮接着された前記第2グリーンシートを剥がす工程と、
前記支持体に載せられた第1グリーンシートから前記支持体を剥がす工程と、
前記異材質複合グリーンシートを複数重ねてプレスしてグリーンシート積層体を成形する工程と、
前記グリーンシート積層体を焼成する工程と、を有することを特徴とする多層セラミック基板の製造方法。 - 前記第1グリーンシートの表面に仮接着された前記第2グリーンシートを剥がす工程の後に、前記異材質複合グリーンシートを打ち抜き孔の無い支持体に接着させる工程を有することを特徴とする請求項1記載の多層セラミック基板の製造方法。
- 前記第1グリーンシート又は前記第2グリーンシートのいずれか一方若しくはその両方にビアホールを形成する工程を有することを特徴とする請求項1又は2記載の多層セラミック基板の製造方法。
- 前記異材質複合グリーンシートに導体ペーストを印刷する工程を有することを特徴とする請求項1、2又は3記載の多層セラミック基板の製造方法。
- 前記異材質複合グリーンシートに導体ペーストを印刷する工程において、前記第1グリーンシートと前記第2グリーンシートとの境界をまたがって導体ペーストを印刷することを特徴とする請求項4記載の多層セラミック基板の製造方法。
- 前記グリーンシート積層体を形成したときに、前記第2グリーンシート同士が積層方向の上下で重なる部分を有するように前記第1グリーンシートの打ち抜き部分をあわせ、該打ち抜き部分に嵌め込まれた前記第2グリーンシートの表面に導体ペーストを印刷し、前記第2グリーンシート同士の層間に内部導体層を介在させたことを特徴とする請求項1、2、3、4又は5記載の多層セラミック基板の製造方法。
- 前記第1グリーンシートと前記第2グリーンシートとは、焼成後に誘電率が異なる材料で形成していることを特徴とする請求項1、2、3、4、5又は6記載の多層セラミック基板の製造方法。
- 前記第1グリーンシートと前記第2グリーンシートとは、厚みが同じであることを特徴とする請求項1、2、3、4、5、6又は7記載の多層セラミック基板の製造方法。
- 前記第1グリーンシートと前記第2グリーンシートとは、同程度のプレス圧縮率及び焼成縮率を有することを特徴とする請求項1、2、3、4、5、6、7又は8記載の多層セラミック基板の製造方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004054271A JP4071204B2 (ja) | 2004-02-27 | 2004-02-27 | 多層セラミック基板の製造方法 |
US11/059,585 US7243424B2 (en) | 2004-02-27 | 2005-02-17 | Production method for a multilayer ceramic substrate |
EP05003439A EP1581035A3 (en) | 2004-02-27 | 2005-02-17 | Multilayer ceramic substrate and its production method |
TW094105311A TW200529723A (en) | 2004-02-27 | 2005-02-22 | Multilayer ceramic substrate and its production method |
CNB2005100521565A CN100484366C (zh) | 2004-02-27 | 2005-02-25 | 多层陶瓷基板的制造方法 |
KR1020050015725A KR100995791B1 (ko) | 2004-02-27 | 2005-02-25 | 다층 세라믹 기판 및 그의 제조방법 |
US11/622,795 US20070110956A1 (en) | 2004-02-27 | 2007-01-12 | Multilayer ceramic substrate and its production method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004054271A JP4071204B2 (ja) | 2004-02-27 | 2004-02-27 | 多層セラミック基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005244070A JP2005244070A (ja) | 2005-09-08 |
JP4071204B2 true JP4071204B2 (ja) | 2008-04-02 |
Family
ID=34858313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004054271A Expired - Fee Related JP4071204B2 (ja) | 2004-02-27 | 2004-02-27 | 多層セラミック基板の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7243424B2 (ja) |
EP (1) | EP1581035A3 (ja) |
JP (1) | JP4071204B2 (ja) |
KR (1) | KR100995791B1 (ja) |
CN (1) | CN100484366C (ja) |
TW (1) | TW200529723A (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7510619B2 (en) * | 2005-07-08 | 2009-03-31 | International Business Machines Corporation | Greensheet via repair/fill tool |
JP4764729B2 (ja) * | 2006-01-27 | 2011-09-07 | コーア株式会社 | セラミック多層基板の製造方法 |
JP4666161B2 (ja) * | 2006-02-08 | 2011-04-06 | Tdk株式会社 | 積層用セラミック基板の製造方法 |
US20080010798A1 (en) * | 2006-07-14 | 2008-01-17 | Borland William J | Thin film dielectrics with co-fired electrodes for capacitors and methods of making thereof |
JP2011035170A (ja) * | 2009-07-31 | 2011-02-17 | Olympus Corp | 多層積層回路 |
CN103178024B (zh) * | 2011-12-26 | 2015-11-11 | 深圳光启高等理工研究院 | 具有复合介电常数的基板及其制备方法 |
CN103260336B (zh) * | 2012-02-20 | 2016-01-27 | 联想(北京)有限公司 | 一种pcb板及电子设备 |
JP2017183653A (ja) * | 2016-03-31 | 2017-10-05 | スナップトラック・インコーポレーテッド | 高周波用多層配線基板とその製造方法 |
DE102016108604A1 (de) * | 2016-05-10 | 2017-11-16 | Epcos Ag | Vielschichtbauelement und Verfahren zur Herstellung eines Vielschichtbauelements |
CN106426577B (zh) * | 2016-10-07 | 2018-03-23 | 郑州登电银河科技有限公司 | 一种ltcc/htcc自动双面压痕设备 |
CN106273000B (zh) * | 2016-10-07 | 2018-04-20 | 郑州登电银河科技有限公司 | 一种ltcc/htcc自动双面压痕设备 |
CN106239750B (zh) * | 2016-10-07 | 2018-04-20 | 郑州登电银河科技有限公司 | 一种ltcc/htcc自动双面压痕设备 |
CN106273001B (zh) * | 2016-10-07 | 2018-04-20 | 郑州登电银河科技有限公司 | 一种ltcc/htcc自动双面压痕设备 |
CN106217660B (zh) * | 2016-10-07 | 2018-10-30 | 郑州登电银河科技有限公司 | 一种ltcc/htcc自动双面压痕设备 |
CN106273002B (zh) * | 2016-10-07 | 2018-04-20 | 郑州登电银河科技有限公司 | 一种ltcc/htcc自动双面压痕设备 |
DE102018102144A1 (de) * | 2018-01-31 | 2019-08-01 | Tdk Electronics Ag | Elektronisches Bauelement |
TWI785381B (zh) | 2019-09-12 | 2022-12-01 | 美商瓦特洛威電子製造公司 | 陶瓷加熱器及使用暫態液相接合之形成方法 |
KR20220160967A (ko) * | 2021-05-28 | 2022-12-06 | (주)티에스이 | 이종 재질의 다층 회로기판 및 그 제조 방법 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3768144A (en) * | 1971-03-04 | 1973-10-30 | American Lava Corp | Process for ceramic composites |
JPS6464394A (en) * | 1987-09-04 | 1989-03-10 | Fujitsu Ltd | Hybrid integrated circuit substrate |
JPH02239697A (ja) * | 1989-03-13 | 1990-09-21 | Nippon Cement Co Ltd | 回路基板の製造方法 |
JP3166251B2 (ja) * | 1991-12-18 | 2001-05-14 | 株式会社村田製作所 | セラミック多層電子部品の製造方法 |
JPH05174649A (ja) | 1991-12-24 | 1993-07-13 | Tdk Corp | 異質材部を有するセラミックグリーンシート及びその製造方法 |
US5239744A (en) | 1992-01-09 | 1993-08-31 | At&T Bell Laboratories | Method for making multilayer magnetic components |
US5305523A (en) | 1992-12-24 | 1994-04-26 | International Business Machines Corporation | Method of direct transferring of electrically conductive elements into a substrate |
US5386339A (en) * | 1993-07-29 | 1995-01-31 | Hughes Aircraft Company | Monolithic microelectronic circuit package including low-temperature-cofired-ceramic (LTCC) tape dielectric structure and in-situ heat sink |
US5759331A (en) * | 1994-07-15 | 1998-06-02 | Paul J. Dostart | Method of ensuring conductivity in the manufacturing of a multi-layer ceramic component containing interlayer conductive-filled via holes |
JPH08236931A (ja) * | 1995-02-23 | 1996-09-13 | Matsushita Electric Works Ltd | セラミック配線板の製造方法 |
US5661882A (en) * | 1995-06-30 | 1997-09-02 | Ferro Corporation | Method of integrating electronic components into electronic circuit structures made using LTCC tape |
JPH0992983A (ja) * | 1995-07-17 | 1997-04-04 | Sumitomo Kinzoku Electro Device:Kk | セラミック多層基板の製造方法 |
US5708570A (en) * | 1995-10-11 | 1998-01-13 | Hughes Aircraft Company | Shrinkage-matched circuit package utilizing low temperature co-fired ceramic structures |
JP3129261B2 (ja) | 1997-11-25 | 2001-01-29 | 株式会社村田製作所 | 多層セラミック基板の製造方法 |
JP3669404B2 (ja) | 1997-09-08 | 2005-07-06 | 株式会社村田製作所 | 多層セラミック基板の製造方法 |
JP3659284B2 (ja) * | 1997-09-25 | 2005-06-15 | 京セラ株式会社 | 高周波用多層配線基板およびその製造方法 |
US6072690A (en) * | 1998-01-15 | 2000-06-06 | International Business Machines Corporation | High k dielectric capacitor with low k sheathed signal vias |
JPH11284334A (ja) | 1998-03-27 | 1999-10-15 | Kyocera Corp | セラミックグリーンシートの貫通孔への金属ペースト充填方法 |
US6569278B1 (en) * | 1999-09-29 | 2003-05-27 | International Business Machines Corporation | Powder metal polymer organic sheet punching for substrate conductors |
JP3646587B2 (ja) * | 1999-10-27 | 2005-05-11 | 株式会社村田製作所 | 多層セラミック基板およびその製造方法 |
JP2001144438A (ja) | 1999-11-15 | 2001-05-25 | Murata Mfg Co Ltd | 多層セラミック基板およびその製造方法 |
JP2004063728A (ja) | 2002-07-29 | 2004-02-26 | Fujitsu Ltd | 受動素子内蔵セラミック・モジュール基板及びその製造方法 |
JP4412891B2 (ja) | 2002-10-29 | 2010-02-10 | 京セラ株式会社 | 複合体および複合積層体の製造方法、並びにセラミック基板の製造方法 |
US7018494B2 (en) * | 2002-08-28 | 2006-03-28 | Kyocera Corporation | Method of producing a composite sheet and method of producing a laminate by using the composite sheet |
JP2004087990A (ja) * | 2002-08-28 | 2004-03-18 | Kyocera Corp | 複合体およびその製造方法、並びにセラミック基板の製造方法 |
-
2004
- 2004-02-27 JP JP2004054271A patent/JP4071204B2/ja not_active Expired - Fee Related
-
2005
- 2005-02-17 EP EP05003439A patent/EP1581035A3/en not_active Withdrawn
- 2005-02-17 US US11/059,585 patent/US7243424B2/en not_active Expired - Fee Related
- 2005-02-22 TW TW094105311A patent/TW200529723A/zh unknown
- 2005-02-25 CN CNB2005100521565A patent/CN100484366C/zh not_active Expired - Fee Related
- 2005-02-25 KR KR1020050015725A patent/KR100995791B1/ko not_active IP Right Cessation
-
2007
- 2007-01-12 US US11/622,795 patent/US20070110956A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20050189137A1 (en) | 2005-09-01 |
TW200529723A (en) | 2005-09-01 |
CN100484366C (zh) | 2009-04-29 |
KR20060042212A (ko) | 2006-05-12 |
CN1662116A (zh) | 2005-08-31 |
EP1581035A3 (en) | 2007-08-15 |
KR100995791B1 (ko) | 2010-11-22 |
US7243424B2 (en) | 2007-07-17 |
US20070110956A1 (en) | 2007-05-17 |
JP2005244070A (ja) | 2005-09-08 |
EP1581035A2 (en) | 2005-09-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100995791B1 (ko) | 다층 세라믹 기판 및 그의 제조방법 | |
JPH11195873A (ja) | 多層セラミック基板およびその製造方法 | |
JP2003017356A (ja) | 積層型電子部品およびその製法 | |
KR101931108B1 (ko) | 미드-k ltcc 조성물 및 디바이스 | |
JP4821302B2 (ja) | セラミック多層基板及びその製造方法 | |
JP3897472B2 (ja) | 受動部品内蔵多層配線基板およびその製造方法 | |
JP4765330B2 (ja) | 積層型電子部品を内蔵した多層配線基板及び多層配線基板の製造方法 | |
JP3955389B2 (ja) | コンデンサ内蔵基板およびその製造方法 | |
JPS5917232A (ja) | 複合積層セラミツク部品およびその製造方法 | |
JP2006253246A (ja) | 多層セラミック基板の製造方法 | |
JPH11354924A (ja) | 多層セラミック基板の製造方法 | |
JP4475076B2 (ja) | 多層セラミック基板の製造方法 | |
JP5114141B2 (ja) | 電子部品およびその製造方法 | |
JP2803754B2 (ja) | 多層電子回路基板 | |
JP2006093511A (ja) | 多層セラミック基板の製造方法及び多層セラミック基板 | |
JP2004200679A (ja) | 多層回路基板の製造方法 | |
US20060127568A1 (en) | Multi-layer ceramic substrate and method for manufacture thereof | |
JP3898653B2 (ja) | ガラスセラミック多層配線基板の製造方法 | |
JP2008135523A (ja) | 多層基板およびその製造方法 | |
JP2008288225A (ja) | コンデンサ、コンデンサの製造方法、コンデンサ内蔵基板、およびコンデンサ内蔵基板の製造方法 | |
JP2003026472A (ja) | 積層セラミック電子部品の製造方法、積層セラミック電子部品および積層セラミック電子部品製造用の生の複合積層体 | |
JP2004207543A (ja) | 多層配線基板の製造方法 | |
JP2004304150A (ja) | 多層回路基板及びその製造方法 | |
JP2006181738A (ja) | セラミック積層体 | |
JP2005005640A (ja) | 多層セラミック基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050606 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070323 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070327 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070508 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20071016 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20071127 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20071113 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20071221 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080115 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080116 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110125 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110125 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120125 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120125 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130125 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130125 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140125 Year of fee payment: 6 |
|
LAPS | Cancellation because of no payment of annual fees |