TWI722541B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI722541B
TWI722541B TW108129783A TW108129783A TWI722541B TW I722541 B TWI722541 B TW I722541B TW 108129783 A TW108129783 A TW 108129783A TW 108129783 A TW108129783 A TW 108129783A TW I722541 B TWI722541 B TW I722541B
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Taiwan
Prior art keywords
semiconductor element
wiring layer
bonding wire
substrate
resin composition
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TW108129783A
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English (en)
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TW202036834A (zh
Inventor
後藤善秋
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日商東芝記憶體股份有限公司
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Publication of TW202036834A publication Critical patent/TW202036834A/zh
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

根據一實施形態，實施形態之半導體裝置100具有：基板1；第1半導體元件2，其設置於基板1上之第1樹脂組合物3上；第2半導體元件13，其設置於基板1上之第2樹脂組合物14上；第3半導體元件4，其設置於基板1上，且夾於第1半導體元件2與第2半導體元件13之間；第1配線層6，其設置於第1半導體元件2上，與第1半導體元件2連接，且利用第1接合線7與基板1連接；第4半導體元件9，其設置於第1配線層6上，且利用第2接合線10與第1配線層6連接；第2配線層16，其設置於第2半導體元件13上，與第2半導體元件13連接，且利用第3接合線17與基板1連接；及第5半導體元件19，其設置於第2配線層16上，且利用第4接合線20與第2配線層16連接。第1接合線7設置於第1配線層6之與朝向第2配線層16之側為相反側以外之部分。第3接合線17設置於第2配線層16之與朝向第1配線層6之側為相反側以外之部分。

Description

半導體裝置
此處所說明之複數種實施形態全部關於一種半導體裝置。
對於使用有記憶體晶片之半導體裝置，正在研究多種封裝體佈局。記憶體之半導體裝置被要求大容量化、小型化或讀寫高速化等特性。
當欲使利用了記憶體晶片之半導體裝置高速化時，控制器晶片容易變大。當欲將更多記憶體晶片呈階梯狀積層以實現大容量化時，配置控制器晶片及記憶體晶片之平面空間會變寬。於欲嚴格執行記憶體晶片之設計規則(使配線寬度變窄)，而增大平均每一個記憶體晶片之存儲容量之情形時，亦有平均每一個晶片之大小較以往大之情況。
因此，當不使半導體裝置之封裝體大小變大而使晶片大小變大時，有難以將控制器晶片與記憶體晶片平面地配置於基板上之情況。亦想到如下操作：以控制器晶片與記憶體晶片不干涉之方式，將外形尺寸較記憶體晶片小之間隔晶片貼附於基板，將記憶體晶片配置於較控制器晶片高之位置。
然而，上述操作需要於對鏡面晶圓進行BSG(Back Side grinding，背面研磨)加工，並貼附晶粒接合膜之後，將間隔晶片呈所需大小切下，並貼附於基板等之步驟，故而半導體裝置之製造費用提高。於搭載相同記憶體晶片片數之情形時，相應於間隔晶片之高度，半導體裝置變厚，而難以薄型化。控制器晶片由於較記憶體晶片小，故而於使用間隔晶片之情形時，記憶體晶片間會出現空餘空間。空間效率上不利且難以小型化。
本發明之實施形態有助於半導體裝置之小型化、薄型化。
實施形態之半導體裝置具有：基板；第1半導體元件，其設置於基板上之第1樹脂組合物上；第2半導體元件，其設置於基板上之第2樹脂組合物上；第3半導體元件，其設置於基板上，且夾於第1半導體元件與第2半導體元件之間；第1配線層，其設置於第1半導體元件上，與第1半導體元件連接，且利用第1接合線與基板連接；第4半導體元件，其設置於第1配線層上，利用第2接合線與第1配線層連接；第2配線層，其設置於第2半導體元件上，與第2半導體元件連接，且利用第3接合線與基板連接；及第5半導體元件，其設置於第2配線層上，且利用第4接合線與第2配線層連接。第1接合線設置於第1配線層之與朝向第2配線層之側為相反側以外之部分。第3接合線設置於第2配線層之與朝向第1配線層之側為相反側以外之部分。
根據上述構成，可實現半導體裝置之小型化、薄型化。
以下，參照圖式對實施形態進行說明。
於本說明書中，對若干個要素附加複數種表述例。再者，該等表述例僅為例示，並非否定利用其他表述來表達上述要素者。又，對於未附加複數種表述之要素，亦可利用其他表述來表達。
又，圖式係模式圖，有厚度與平面尺寸之關係或各層之厚度之比率等與實物不同之情況。又，亦有於圖式彼此之間包含相互之尺寸關係或比率不同之部分之情況。關於對稱配置之構件，省略一部分共通之說明。
(實施形態) 圖1表示實施形態之半導體裝置100之剖視圖。半導體裝置100係包含例如作為控制器晶片之半導體元件及例如作為半導體記憶體晶片之半導體元件之半導體封裝體。更具體而言，半導體裝置100係例如所謂之BGA-SSD(Ball Grid Array-Solid State Drive，球柵陣列固態驅動器)，複數個半導體記憶體晶片與控制器一體地構成為一個BGA型封裝體。
關於圖1之半導體裝置100，示出基板1、第1半導體元件2、第1樹脂組合物3、第3半導體元件4、接合線5、7、10、11、15、17、20、21、第1配線層6、第3樹脂組合物8、第4半導體元件9、接著層12、22、第2半導體元件13、第2樹脂組合物14、第2配線層16、第4樹脂組合物18、第5半導體元件19及密封材23。
基板1係半導體元件2、4、9、13、19之支持基板。基板1更具體而言為多層配線基板。於基板1之第1面側設置有半導體元件2、4、9、13、19。基板1之與第1面對向之第2面側設置有用於與半導體裝置100之外部連接之圖1中未圖示之焊料球等半球狀之電極。
半導體裝置100例如包含作為記憶體晶片之第1半導體元件2、第2半導體元件13、第4半導體元件9及第5半導體元件19。第1半導體元件2及第2半導體元件13設置於基板1側。第4半導體元件9係例如設置於第1半導體元件2上之1個以上之記憶體晶片。第5半導體元件19係例如設置於第2半導體元件13上之1個以上之記憶體晶片。
記憶體晶片係進行數據讀寫之半導體晶片。作為非揮發性記憶體晶片，可使用NAND(Not And，與非)記憶體晶片、相變記憶體晶片、電阻變化記憶體晶片、鐵電記憶體晶片及磁記憶體晶片等。作為揮發性記憶體晶片，可使用DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)等。實施形態中所使用之記憶體晶片較佳為除個體差異以外為同一電路且同一構造之半導體晶片。又，於本實施形態中，可使用非揮發性記憶體晶片、揮發性記憶體晶片作為記憶體晶片。作為半導體元件，亦可使用除記憶體晶片以外之半導體晶片。
以隔著第3半導體元件4之方式配置記憶體晶片等積層體，從而兼顧大容量與高速化，故而第1半導體元件2、第2半導體元件13、第4半導體元件9及第5半導體元件19之縱橫比(長邊(長度方向之側面之長度)/短邊(寬度方向之側面之長度))較佳為1.5以上3.5以下。第1半導體元件2之朝向第2半導體元件13側之長邊與第2半導體元件13之朝向第1半導體元件2側之長邊對向。
第1半導體元件2係設置於基板1上之半導體晶片。更具體而言，第1半導體元件2係設置於基板1上之第1樹脂組合物3上之記憶體晶片。
第1樹脂組合物3係晶粒接合膜(DAF；Die Attach Film)等接著性樹脂組合物。第1樹脂組合物3設置於基板1上，且與第1半導體元件2接著。第1樹脂組合物3中，存在連接第3半導體元件4與基板1之1群接合線，即1條以上之第5接合線5。由於在第1樹脂組合物3中埋入有導線，故而將第1半導體元件2與第1樹脂組合物3積層所得之構造係被稱作所謂FOW(Film on Wire，膜覆線)之構造。
第3半導體元件4係利用厚度為例如5 μm到20 μm之DAF等接著劑固定於基板1上之半導體晶片。第3半導體元件4例如為記憶體晶片之控制器。第3半導體元件4與半導體裝置100之外部連接，控制記憶體晶片之讀寫，例如進行讀寫高速化或錯誤訂正等。第3半導體元件4並非倒裝晶片，故而第3半導體元件4之電極墊配置於與基板1側為相反側之側(記憶體晶片側)。以下，將第1半導體元件2稱為第1記憶體晶片2，將第2半導體元件13稱為第2記憶體晶片13，將第3半導體元件4稱為控制器晶片4，將第4半導體元件9稱為第3記憶體晶片9，將第5半導體元件19稱為第4記憶體晶片19。
控制器晶片4以夾於第1記憶體晶片2與第2記憶體晶片13之間之方式配置。控制器晶片4之具有電極墊之面朝向與基板1側為相反側之側，存在電極墊之面之至少一部分，更具體而言，存在電極墊之面之至少中央由密封材23密封。於圖1之模式圖中，於第1樹脂組合物3與第2樹脂組合物14之間配置有控制器晶片4，於第1樹脂組合物3與控制器晶片4之間設置有密封材23，於第2樹脂組合物14與控制器晶片4之間亦設置有密封材23。
第1記憶體晶片2與第3記憶體晶片9經由樹脂組合物或接著劑12於Y方向上積層所得之構造和第2記憶體晶片13與第4記憶體晶片19經由樹脂組合物或接著劑22積層所得之構造較佳為以控制器晶片4為中心對稱地配置。
控制器晶片4配置於較第1記憶體晶片2更靠基板1側，且配置於較第2記憶體晶片13更靠基板1側。藉由使控制器晶片4近接於基板1，且配置於基板1之中心側，可效率良好地配置對稱之記憶體晶片之積層構造，且兼顧高容量與讀寫高速化。就上述觀點而言，連接第1記憶體晶片2之中心與第2記憶體晶片13之中心之假想線段之中心較佳為以於基板1與控制器晶片4之積層方向(Y方向)上，與控制器晶片4重疊之方式配置控制器晶片4。
第5接合線5係連接基板1與控制器晶片4之接合線。第5接合線5將圖1中未圖示之基板1上之電極墊與控制器晶片4之電極墊連接。第5接合線5位於第1記憶體晶片2與基板1之間。第5接合線5之基板1側之至少一部分埋入至第1樹脂組合物3中而被密封。於包含第5接合線5之未埋入至第1樹脂組合物3中之部分時，該部分由密封材23密封。
第1配線層6係設置於第1記憶體晶片2上之再配線層。第1配線層6與第1記憶體晶片2連接。第1配線層6與記憶體晶片2直接相接，第1記憶體晶片2之電極墊與第1配線層6之配線電性連接。藉由使用第1配線層6，可設為如下構造：將連接第1記憶體晶片2與基板1之第1接合線7設置於第1配線層6之與朝向第2配線層16之側為相反側以外之部分。第1配線層6之大小、更具體而言為朝向第1記憶體晶片2之面(及相反側之面)之大小較第1記憶體晶片2小。
第1接合線7係連接第1配線層6與基板1之配線。第1接合線7之一部分埋入至第3樹脂組合物8中而被密封。第1接合線7之未埋入至第3樹脂組合物8中之部分由密封材23密封。第1接合線7將第1配線層6之與朝向第1記憶體晶片2之面為相反側之電極墊和基板1上之電極墊連接。
第3樹脂組合物8係設置於第1配線層6與第3記憶體晶片9之間之DAF等接著性樹脂組合物。於第3樹脂組合物8，埋入有第1接合線7之一部分，位於最靠第1記憶體晶片2側之第3記憶體晶片9A與第3樹脂組合物8積層所得之構造被稱作FOW。
自基板1至第3樹脂組合物8之第1記憶體晶片2側之面為止之距離較佳為長於自基板1至控制器晶片4之上表面為止之距離。當第1樹脂組合物3過薄時，第5接合線5與第1記憶體晶片2之基板1側之面接觸。當自基板1至第3樹脂組合物8之第1記憶體晶片2側之面為止之距離過短時，第5接合線5與第3樹脂組合物8之基板1側之面接觸。基板1與控制器晶片4亦可利用自控制器晶片4之上表面於Z方向上延伸之接合線(例如圖2之接合線24)連接，但連接控制器晶片4與基板1之接合線會變得過密。
第3記憶體晶片9(9A、9B、9C、9D)係設置於第3樹脂組合物8上之1個以上之記憶體晶片群。於第3記憶體晶片9之間，設置有接著層12(12A、12B、12C)，將第3記憶體晶片9接著。第1配線層6與第3記憶體晶片9係利用第2接合線10連接。第3記憶體晶片9彼此係利用第7接合線11(11A、11B、11C)連接。
第2接合線10係連接第1配線層6與第3記憶體晶片9之配線。第2接合線10係如下導線：自第1配線層6之與控制器晶片4側為相反側之電極墊連接位於第1配線層6之上側且較第1配線層6更靠半導體裝置100之中心側之第3記憶體晶片9之電極墊。
第7接合線11(11A、11B、11C)係將第3記憶體晶片9間電性連接之配線。第7接合線11之配線之朝向與第2接合線10之配線之朝向相同，但與第1接合線7之配線之朝向不同。
接著層12(12A、12B、12C)係配置於第3記憶體晶片9彼此之間之接著性樹脂層。接著層12例如為DAF。
第2記憶體晶片13係如下半導體晶片：自控制器晶片4觀察，設置於與第1記憶體晶片2為相反側。第2記憶體晶片13設置於基板1上之第2樹脂組合物14上。
第2樹脂組合物14係DAF等接著性樹脂組合物。第2樹脂組合物14設置於基板1上，且與第2記憶體晶片13接著。第2樹脂組合物14自控制器晶片4觀察，設置於與第1樹脂組合物3為相反側。於第2樹脂組合物14中，存在連接控制器晶片4與基板1之1群接合線即1條以上之第6接合線15。於第2樹脂組合物14中埋入有導線，故而將第2記憶體晶片13與第2樹脂組合物14積層所得之構造係被稱作所謂FOW(Film on Wire)之構造。
第6接合線15係連接基板1與控制器晶片4之接合線。第6接合線15自控制器晶片4觀察，設置於與第5接合線5為相反側。第6接合線15將圖1中未圖示之基板1上之電極墊與控制器晶片4之電極墊連接。第6接合線15位於第2記憶體晶片13與基板1之間。第6接合線15之基板1側之至少一部分埋入至第2樹脂組合物14中而被密封。於包含第6接合線15之未埋入至第2樹脂組合物14之部分時，該部分由密封材23密封。
第2配線層16係設置於第2記憶體晶片13上之再配線層。第2配線層16自控制器晶片4觀察，設置於與第1配線層6為相反側。第2配線層16與第2記憶體晶片13連接。第2配線層16與第2記憶體晶片13直接相接，第2記憶體晶片13之電極墊與第2配線層16之配線電性連接。藉由使用第2配線層16，可設為如下構造：將連接第2記憶體晶片13與基板1之第3接合線17設置於第2配線層16之與朝向第1配線層6之側為相反側以外之部分。第2配線層16之大小、更具體而言為朝向第2記憶體晶片13之面(及相反側之面)之大小較第2記憶體晶片13小。
第3接合線17係將第2配線層16與基板1連接之配線。第3接合線17自控制器晶片4觀察，設置於與第1接合線7為相反側。第3接合線17之一部分埋入至第4樹脂組合物18中而被密封。第3接合線17之未埋入至第4樹脂組合物18中之部分由密封材23密封。第3接合線17將第2配線層16之與朝向第2記憶體晶片13之面為相反側之電極墊和基板1上之電極墊連接。
第4樹脂組合物18係設置於第2配線層16與第4記憶體晶片19之間之DAF等接著性樹脂組合物。第4樹脂組合物18自控制器晶片4觀察，設置於與第3樹脂組合物8為相反側。於第4樹脂組合物18，埋入有第3接合線17之一部分，位於最靠第2記憶體晶片13側之第4記憶體晶片19A與第4樹脂組合物18積層所得之構造被稱作FOW。
第4記憶體晶片19(19A、19B、19C、19D)係設置於第4樹脂組合物18上之1個以上之記憶體晶片群。第4記憶體晶片19自控制器晶片4觀察，設置於與第3記憶體晶片9為相反側。於第4記憶體晶片19之間，設置有接著層22(22A、22B、22C)，將第4記憶體晶片19接著。第2配線層16與第4記憶體晶片19由第4接合線20連接。第4記憶體晶片19彼此由第8接合線21(21A、21B、21C)連接。
第4接合線20係將第2配線層16與第4記憶體晶片19連接之配線。第4接合線20自控制器晶片4觀察，設置於與第2接合線10為相反側。第4接合線20係如下導線：自第2配線層16之與控制器晶片4側為相反側之電極墊連接位於第2配線層16之上側且較第2配線層16更靠半導體裝置100之中心側之第4記憶體晶片19之電極墊。
第8接合線21(21A、21B、21C)係將第4記憶體晶片19間電性連接之配線。第8接合線21之配線之朝向與第4接合線20之配線之朝向相同，但與第3接合線17之配線之朝向不同。
接著層22(22A、22B、22C)係配置於第4記憶體晶片19彼此之間之接著性樹脂層。接著層22例如為DAF。
密封材23將設置於基板1上之構件密封。密封材23亦為半導體裝置100之外裝材。密封材23係較硬之樹脂組合物，更具體而言係模具樹脂。
此處，使用圖2之半導體裝置100之配線模式圖，對半導體裝置100內之配線與構成構件之配置進行說明。圖2之模式圖中示出自圖1之模式圖之上側觀察到之配線。於第1配線層6及第2配線層16設置有除電極墊以外之配線，但於圖2之模式圖中，第1配線層6及第2配線層16之配線省略。模式性地示出基板1、第1記憶體晶片2、第2記憶體晶片13、第1配線層6及第2配線層16間之配線。基板1之電極墊係以中空之四方形表示。控制器晶片4之電極墊係以黑色之四方形表示。設置於第1配線層6之與朝向第2配線層16之側為相反側之電極墊係以三角形表示。設置於第2配線層16之與朝向第1配線層6之側為相反側之電極墊係以三角形表示。設置於第1配線層6之與朝向第2配線層16之側為相反側以外之電極墊係以圓表示。設置於第2配線層16之與朝向第1配線層6之側為相反側以外之電極墊係以圓表示。
首先，對控制器晶片4之配線進行說明。控制器晶片4利用接合線(5、15、24)與基板1連接。不存在將控制器晶片4與記憶體晶片直接連接之配線。控制器晶片4與記憶體晶片之配線均經過第1配線層6或第2配線層16、及基板1。第5接合線5自控制器晶片4延伸至第1記憶體晶片2之下側，將控制器晶片4與基板1連接。於第2記憶體晶片13側亦同樣地存在第6接合線15。較佳為於圖1之深度方向(Z方向)上亦設置有連接控制器晶片4與基板1之接合線25。與控制器晶片4連接之接合線亦位於記憶體晶片之下側，故而即便高密度地配置半導體裝置100內之晶片，亦能以佈局上無較大制約之方式進行配線。
其次，對第1配線層6與基板1之配線進行說明。半導體裝置100中所使用之記憶體晶片全部相同，故而若不使用第1配線層6，則第1記憶體晶片2與基板1之配線將自與第2接合線10連接之第1記憶體晶片2之電極墊朝向基板1之外周邊(對向或近接之外周邊)側延伸。於圖1及圖2中，自記憶體晶片之與控制器晶片4側為相反側之長邊側朝向與控制器晶片4側為相反側未形成有接合線。若自記憶體晶片之與控制器晶片4側為相反側之長邊側朝向與控制器晶片4側為相反側形成有接合線，則必須相應於接合線之量，使基板1及半導體裝置100均變大，從而導致半導體裝置100大型化，難以進行控制器晶片4之配線。實施形態中，第1接合線7設置於第1配線層6之與朝向第2配線層16之側為相反側以外之部分。即，連接第1配線6與基板1之第1接合線7未跨及第1記憶體晶片2之與控制器晶片4側為相反側之側面。於圖2中，連接第1配線層6與基板1之第1接合線7形成於三方向。第1接合線7A以自第1配線層6之長邊側朝向第2配線層6側之方式設置。第1接合線7B、7C自第1配線層6之短邊側設置。亦可省略第1接合線7A、7B、7C中之任一條或任兩條。即，僅於第1配線層6之一邊側或兩邊側設置有第1接合線7之形態亦包含於實施形態中。第1配線層6之配線佈局係於滿足上述主要條件之範圍內任意設計。
第2配線層16與基板1之配線和第1配線層6與基板1之配線相同。實施形態中，第2接合線17設置於第2配線層16之與朝向第1配線層6之側為相反側以外之部分。即，連接第2配線層16與基板1之第3接合線17未跨及第2記憶體晶片13之與控制器晶片4側為相反側之側面。
自最下段之記憶體晶片2、13至基板1，無於外側接合之導線，故而與此相應，可使半導體裝置之外形尺寸變小。於不變更外形尺寸之情形時，亦可收納更大之記憶體晶片、及為了實現高速化而更大之控制器晶片4。若將最下段之記憶體晶片之搭載位置以相應於無導線之量配置於靠外側，則最上段之記憶體晶片彼此之間隔可於基本消失之前，供將更多記憶體晶片呈階梯狀積層。實施形態之半導體裝置100有助於半導體裝置之小型化、大容量化及高速化。
藉由採用實施形態之半導體層100之佈局，使用相同晶片之情形將有助於小型化及薄型化。而且，藉由使晶片大小變大或增加記憶體晶片之數量，可實現半導體裝置100之大容量化或高速化。於該情形時，藉由採用實施形態之半導體裝置100之佈局，即便晶片變大或晶片數量增加，亦可有效率地配置晶片並進行配線，故而可構成小型化且薄型之半導體裝置100。
比較形態之半導體裝置存在如下形態：利用例如100 μm以上之較厚之DAF覆蓋控制器晶片與接合線，且於其上設置矽或聚醯亞胺之間隔片，於間隔片上積層記憶體晶片。於此種形態中，相應於DAF或間隔片之厚度，半導體裝置之Y方向之高度變高，而難以薄型化。
於實施形態之半導體裝置100中，由於不使用間隔片而將控制器晶片4與記憶體晶片積層，故而亦可使半導體裝置100之Y方向之高度變低，實施形態之構造亦有助於半導體裝置100之薄型化。
圖3中示出半導體裝置100之變化例之半導體裝置101之剖面模式圖。圖3所示之半導體裝置101將控制器晶片4之一部分埋入至第1樹脂組合物3及第2樹脂組合物14中並密封。藉由將控制器晶片4之一部分埋入，使記憶體晶片配置於較圖1之形態之半導體裝置100更靠控制器晶片4側，藉此可使半導體裝置101之寬度(X方向之距離)變得更窄。即便控制器晶片4大型化，根據該構造，亦會使半導體裝置101之寬度變窄，而有助於半導體裝置101之小型化。第5接合線5之一部分或全部被埋入至第1樹脂組合物3中。第6接合線15之一部分或全部被埋入至第2樹脂組合物14中。
以上，對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提出者，並不意圖限定發明之範圍。該等新穎之實施形態能以其他多種形態實施，可於不脫離發明主旨之範圍內進行各種省略、置換及變更。該等實施形態或其變化例包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
[相關申請] 本申請基於2019年3月22日提出申請之先前之日本專利申請第2019-054415號之優先權利益且追求該利益，其全部內容係藉由引用而包含於本文中。
1:基板 2:第1半導體元件 3:第1樹脂組合物 4:第3半導體元件 5:第5接合線 6:第1配線層 7:第1接合線 7A、7B、7C:第1接合線 8:第3樹脂組合物 9A、9B、9C、9D:第3記憶體晶片 10:第2接合線 11A、11B、11C:第7接合線 12A、12B、12C:接著層 13:第2半導體元件 14:第2樹脂組合物 15:第6接合線 16:第2配線層 17:第3接合線 18:第4樹脂組合物 19A、19B、19C、19D:第4記憶體晶片 20:第4接合線 21A、21B、21C:第8接合線 22A、22B、22C:接著層 23:密封材 24:接合線 100:半導體裝置 101:半導體裝置
圖1係實施形態之半導體裝置之剖視圖。 圖2係實施形態之半導體裝置之配線模式圖。 圖3係實施形態之半導體裝置之剖視圖。
1:基板
2:第1半導體元件
3:第1樹脂組合物
4:第3半導體元件
5:第5接合線
6:第1配線層
7:第1接合線
8:第3樹脂組合物
9A、9B、9C、9D:第3記憶體晶片
10:第2接合線
11A、11B、11C:第7接合線
12A、12B、12C:接著層
13:第2半導體元件
14:第2樹脂組合物
15:第6接合線
16:第2配線層
17:第3接合線
18:第4樹脂組合物
19A、19B、19C、19D:第4記憶體晶片
20:第4接合線
21A、21B、21C:第8接合線
22A、22B、22C:接著層
23:密封材
100:半導體裝置

Claims (6)

  1. 一種半導體裝置，其具有：基板；第1半導體元件，其設置於上述基板上之第1樹脂組合物上；第2半導體元件，其設置於上述基板上之第2樹脂組合物上；第3半導體元件，其設置於上述基板上，且夾於上述第1半導體元件與第2半導體元件之間；第1配線層，其設置於上述第1半導體元件上，與上述第1半導體元件連接，且利用第1接合線與上述基板連接；第4半導體元件，其設置於上述第1配線層上，利用第2接合線與上述第1配線層連接；第2配線層，其設置於上述第2半導體元件上，與上述第2半導體元件連接，且利用第3接合線與上述基板連接；及第5半導體元件，其設置於上述第2配線層上，且利用第4接合線與上述第2配線層連接；且上述第1接合線設置於上述第1配線層之與朝向上述第2配線層之側為相反側以外之部分，上述第3接合線設置於上述第2配線層之與朝向上述第1配線層之側為相反側以外之部分，上述第2接合線之一端部設置於上述第1配線層之與朝向上述第2配線層之側之相反側，上述第4接合線之一端部設置於上述第2配線層之與朝向上述第1配線 層之側之相反側。
  2. 如請求項1之半導體裝置，其中上述第1半導體元件、第2半導體元件、第4半導體元件及第5半導體元件係記憶體晶片，上述第3半導體元件係控制器晶片，連接上述第1半導體元件之中心與上述第2半導體元件之中心之假想線段之中心於上述基板與上述第3半導體元件之積層方向上，與上述第3半導體元件重疊。
  3. 如請求項1之半導體裝置，其中上述第3半導體元件之一部分密封於上述第1樹脂組合物及第2樹脂組合物中。
  4. 如請求項1之半導體裝置，其中上述第3半導體元件進而具有與上述基板連接之第5接合線及第6接合線，上述第5接合線之至少一部分密封於上述第1樹脂組合物中，上述第6接合線之至少一部分密封於上述第2樹脂組合物中。
  5. 如請求項1至4中任一項之半導體裝置，其進而具有：第3樹脂組合物，其設置於上述第1半導體元件與上述第4半導體元件之間；及第4樹脂組合物，其設置於上述第2半導體元件與上述第5半導體元件之間；且上述第1接合線之一部分密封於上述第3樹脂組合物中， 上述第2接合線之一部分密封於上述第4樹脂組合物中。
  6. 如請求項1之半導體裝置，其中上述第2接合線之上述一端部，於上述第1配線層之與朝向上述第2配線層之側之相反側，自上方觀察時與上述第4半導體元件未重疊，上述第4接合線之上述一端部，於上述第2配線層之與朝向上述第1配線層之側之相反側，自上方觀察時與上述第5半導體元件未重疊。
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