CN111725175A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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Publication number
CN111725175A
CN111725175A CN201910802324.XA CN201910802324A CN111725175A CN 111725175 A CN111725175 A CN 111725175A CN 201910802324 A CN201910802324 A CN 201910802324A CN 111725175 A CN111725175 A CN 111725175A
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Prior art keywords
wiring layer
semiconductor element
semiconductor device
semiconductor
sealing material
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CN201910802324.XA
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竹本康男
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Kioxia Corp
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Toshiba Memory Corp
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Publication of CN111725175A publication Critical patent/CN111725175A/zh
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Abstract

本发明涉及一种半导体装置及半导体装置的制造方法。根据一个实施方式，实施方式的半导体装置(100)具备：第一布线层(1)，具有第一面、及与第一面对向的第二面；第一半导体元件(2)，搭载于第一布线层(1)的第一面侧；导电性柱(3)，设置于第一布线层(1)的第一面侧，具有第一半导体元件(2)的厚度以上的高度；第二布线层(5)，具有第三面、及与第三面对向的第四面，设置于导电性柱(3)上，且在第四面侧接合于导电性柱(3)；第二半导体元件(6)，搭载于第二布线层(5)的第三面侧，通过第一接合线(7)与第二布线层(5)连接；第一密封材(4)，将第一布线层(1)的第一面、第一半导体元件(2)、导电性柱(3)及第二布线层(5)的第四面密封；及第二密封材(8)，将第二布线层(5)的第三面、第二半导体元件(6)及第一接合线(7)密封。

Description

半导体装置及半导体装置的制造方法
相关申请案
本申请案以2019年3月20日提出申请的先行的日本专利申请案第2019-053678号的优先权的利益为基础，且要求该利益，其全部内容通过引用包含于此。
技术领域
这里所说明的多个实施方式全部涉及一种半导体装置及半导体装置的制造方法。
背景技术
关于使用非易失性存储器芯片的半导体装置，研究了各种封装布局。非易失性存储器的半导体装置被要求具有大容量化、小型化、读写高速化等特性。
发明内容
本发明的实施方式提供一种能够实现小型化、薄型化的半导体装置及半导体装置的制造方法。
根据实施方式的半导体装置及半导体装置的制造方法，具备：第一布线层，具有第一面、及与第一面对向的第二面；第一半导体元件，搭载于第一布线层的第一面侧；导电性柱，设置于第一布线层的第一面侧，具有第一半导体元件的厚度以上的高度；第二布线层，具有第三面、及与第三面对向的第四面，设置于导电性柱上，且在第四面侧接合于导电性柱；第二半导体元件，搭载于第二布线层的第三面侧，通过第一接合线与第二布线层连接；第一密封材，将第一布线层的第一面、第一半导体元件、导电性柱及第二布线层的第四面密封；及第二密封材，将第二布线层的第三面、第二半导体元件及第一接合线密封。
根据所述构成，能够提供一种得以实现小型化、薄型化的半导体装置及半导体装置的制造方法。
附图说明
图1是实施方式的半导体装置的剖视图。
图2是实施方式的半导体装置的制造方法的流程图。
图3是实施方式的半导体装置的步骤图。
图4是实施方式的半导体装置的步骤图。
图5是实施方式的半导体装置的步骤图。
图6是实施方式的半导体装置的制造方法的流程图。
图7是实施方式的半导体装置的步骤图。
图8是实施方式的半导体装置的步骤图。
图9是实施方式的半导体装置的剖视图。
图10是实施方式的半导体装置的剖视图。
图11是实施方式的半导体装置的剖视图。
具体实施方式
下面，参照附图对实施方式进行说明。
在本说明书中，对若干个要素标注了多种表达例。此外，这些表达例归根到底不过是例示而已，并不否定通过其他表达来表示所述要素的情况。另外，对于未标注多种表达的要素，也可以通过其他表达来表示。
另外，附图是示意性的，存在厚度与平面尺寸的关系、或各层的厚度的比例等与实际不同的情况。另外，也存在附图相互间包含彼此的尺寸关系或比例不同的部分的情况。
(第一实施方式)图1表示实施方式的半导体装置100的剖视图。半导体装置100是半导体封装件。更具体来说，半导体装置100例如是由作为所谓的BGA-SSD(Ball GridArray-Solid State Drive，球栅阵列-固态驱动器)的种类不同的半导体元件按一个BGA类型的封装件一体构成的。
图1的半导体装置100具有第一布线层1、第一半导体元件2、导电性柱3、第一密封材4、第二布线层5、第二半导体元件6、第一接合线7、第二密封材8及电极部9。
第一布线层1设置于半导体装置100，保持有第一半导体元件2等。第一布线层1是所谓的再布线层。第一布线层1在树脂层包含由Cu等导电部件构成的布线。第一布线层1具有第一面、及与第一面对向的第二面。第一布线层1的第一面是搭载有第一半导体元件2的面。在第一布线层1的第一面，还形成有导电性柱3。第一半导体元件2、导电性柱均与第一布线层1的布线直接连接，而电相连。第一布线层1的第一面被密封材4密封。另外，在第一布线层1的第一面，设置有与导电性柱3连接的焊垫部、及与第一半导体元件2连接的焊垫部，在第二面，设置有由多个半球状的电极构成的电极部9。在LGA(land Grid Array，焊盘网格阵列)的情况下，电极部也可以为平坦的电极，只要能够与半导体装置100的外部电连接，可以是任何种类的电极。
第一半导体元件2搭载于第一布线层1的第一面侧。第一半导体元件2配置于第一布线层1与第二布线层5之间。第一半导体元件2是所谓的倒装芯片，第一半导体元件2在第一布线层1的第一面侧具有凸块电极，凸块电极与形成于第一布线层1的布线上的焊垫部连接。第一半导体元件2例如为控制第二半导体元件6的控制器元件。
导电性柱3是将第一布线层1与第二布线层5连接的布线。导电性柱3配置于第一布线层1与第二布线层5之间，与第一布线层1及第二布线层5两者直接连接。如图1所示，至少2个以上导电性柱3包含于半导体装置100，第一半导体元件2位于导电性柱3之间。导电性柱3与第一布线层1的第一面侧的布线接合，且与第二布线层5的第四面接合。导电性柱3例如由Cu等导电性金属构成。导电性柱3的高度(第一布线层1到第二布线层5的距离)为第一半导体元件的厚度以上。当第一布线层1的布线由Cu构成，且导电性柱3由Cu构成时，Cu彼此接合。
第一密封材4将第一布线层1的第一面、第一半导体元件2、导电性柱3、及第二布线层5的朝向第一布线层1侧的面也就是第四面密封。第一密封材4例如为模具树脂。
第二布线层5设置于半导体装置100，保持有第二半导体元件6等。第二布线层5是所谓的再布线层。第二布线层5经由导电性柱3及第一接合线7，将第一半导体元件2与第二半导体元件6连接。第二布线层5也与第一布线层1同样地，具备在树脂层形成有布线的构造。第二布线层5具有第三面、及与第三面对向的第四面。在第二布线层5的第三面侧，搭载有第二半导体元件6。第二布线层5的第四面侧与导电性柱3接合。
通过使第二布线层5与导电性柱3不经由焊料球等而直接连接，能够将高度降低与焊料球等接合部件相应的量。在第一半导体元件侧与第二半导体元件侧分别制造出各自的子封装件后，再将这些子封装件接合的情况下，从强度的观点来看，要对至少任一个子封装件使用例如玻璃环氧衬底。如果对所有子封装件均不使用玻璃环氧衬底等无机系布线衬底，那么会在制作子封装件时强度不足，或在接合子封装件时强度不足。因此，如果不使用玻璃环氧衬底等无机系布线层，那么将子封装件接合而获得1个封装件就不实用了。实施方式的半导体装置100并不是将子封装件接合而获得的，因此第二布线层5与第一密封材4之间未产生间隙。
将第二布线层5与第一半导体元件2覆盖的第一密封材4在它们的积层方向上，以在1条直线上排列的方式配置。另外，将第一布线层1与第二半导体元件5密封的第二密封材在它们的积层方向上，以在1条直线上排列的方式配置。
第二半导体元件6搭载于第二布线层5的第三面侧。第二半导体元件6的与朝向第二布线层5的面对向那侧的面上所设置的电极垫与第二布线层5连接。第二半导体元件6位于第二布线层5与第二密封材8之间。第二半导体元件6例如由设置于第二布线层5上的芯片粘结膜等粘接层所固定。第二半导体元件6与第二布线层5通过第一接合线7而连接。第二半导体元件6例如为存储器元件。作为存储器元件，可以列举非易失性存储器元件、或非易失性存储器元件与易失性存储器元件组合而成的形态。作为非易失性存储器元件，可以使用NAND存储器芯片、相变存储器芯片、阻变存储器芯片、铁电存储器芯片、磁存储器芯片等。作为易失性存储器元件，可以使用DRAM(Dynamic Random Access Memory，动态随机访问存储器)芯片等。
第一接合线7是将第二布线层5与第二半导体元件6连接的布线。第一接合线7与第二布线层5的布线连接。第一接合线7例如为Au等线。
第二密封材8将第二布线层5的第三面、第二半导体元件6及第一接合线7密封。第二密封材8例如为模具树脂。
电极部9是设置于第一布线层1的第二面侧的电极。电极部9例如为球焊垫电极。
接下来，对半导体装置100的制造方法进行说明。在制造方法的说明中，会参照一部分步骤图。半导体装置100的制造方法包含：第一步骤，在衬底上设置第一布线层1、第一半导体元件2、导电性柱3及第一密封材4；第二步骤，第一步骤后，在第一密封材4上形成第二布线层5、第二半导体元件6、第一接合线7及第二密封材8；及如下所述的步骤，第二步骤后，将玻璃衬底剥离，在衬底已被剥离的面形成电极部9。
图2是表示半导体装置100的制造方法的流程图。图2的流程图所示的制造方法是半导体装置100的制造方法的一个例子。如图2所示，半导体装置100的制造方法更具体来说，包含如下步骤：在衬底10上形成第一布线层1；在第一布线层1上设置第一半导体元件2；形成第一密封材4；在第一密封材4形成孔H；向孔H中埋入导电性材料；进行平坦化处理；在第一密封材4上形成第二布线层5；在第二布线层5上设置第二半导体元件6，并通过线接合进行布线；形成第二密封材8；使其反转，将衬底10剥离，而形成电极部9。
首先，在衬底10上形成第一布线层1。在衬底10上形成布线部件，并进行图案化处理，而形成树脂层。将树脂层进一步图案化，进而形成导电部件，并进行图案化处理等，由此获得第一布线层1。布线部件的材料可以使用Al或Cu。布线形成也可以采用溅镀或涂镀。树脂层也可以使用感光性的聚酰亚胺等。在第一布线层1形成要与第一半导体元件2连接的焊垫部、及要与导电性柱3连接的焊垫部。然后，将通过另外的制程所制作出的第一半导体元件2设置于第一布线层1的第一面，并将第一布线层1的焊垫部与第一半导体元件2的凸块电极通过倒装芯片而连接。然后，利用第一密封材4将第一布线层1的第一面与第一半导体元件2密封，并进行激光加工或干式蚀刻加工等，而在第一密封材4形成孔H，由此获得图3的步骤图所示的部件。
然后，向图3的步骤图所示的部件的孔H中埋入作为导电性柱3的材料的导电性材料，并将导电性柱3与第一密封材4平坦化，由此获得图4的步骤图所示的部件。这时，可以通过涂镀形成导电性柱3，也可以通过网版印刷、喷墨等将导电性材料埋入孔洞中而形成导电性柱3。平坦化处理后，孔H内的导电性材料变成导电性柱3。埋入导电性材料，并将导电性柱3与第一布线层1电连接。更具体来说，使第一布线层1的布线材料与导电性柱3接合。
另外，也可以不进行平坦化处理，例如，导电性柱3也可以相对于第一密封材4略微突出或凹陷。在接下来的形成第二布线层5的步骤中，只要导电性柱3与第二布线层5的布线能够电连接即可。
然后，在图4的步骤图所示的部件的第一密封材4上形成第二布线层5，并将导电性柱3与第二布线层5电连接。在导电性柱3与第一密封材4之上形成布线部件，并进行图案化处理，而形成树脂层。将树脂层进一步图案化，进而形成导电部件，并进行图案化处理等，由此获得第二布线层5。布线部件的材料可以使用Al或Cu。布线形成也可以采用溅镀或涂镀。树脂层也可以使用感光性的聚酰亚胺等。在第二布线层5的第三面，形成要与形成于第二半导体元件6的焊垫连接的焊垫部，在第四面，形成要与导电性柱3连接的焊垫部。然后，在第二布线层5上设置第二半导体元件6，并将第二半导体元件6的焊垫部与第二布线层5的焊垫部通过第一接合线7而连接。第二布线层5与第二半导体元件6可以通过芯片粘结膜等粘合性膜而粘接，也可以通过液状粘接剂等而粘接。
然后，利用第二密封材8将第二布线层5的第三面、第二半导体元件6、第一接合线7密封，并任意进行平坦化处理。然后，如图5的步骤图所示，将衬底10剥离。也可以在将衬底10剥离的前后使所得的部件反转。然后，在第一布线层1的衬底10已被剥离的面形成半球状的电极部9，由此获得图1的半导体装置100。
关于衬底10，并不特别限定，只要在所述制程中具有足够的强度即可，较为典型的是，可以使用玻璃板。此外，也可以为硅。另外，也可以预先在衬底10之上涂布剥离剂，以便容易将第一布线层1与衬底10剥离。也可以为在衬底10上形成第一布线层1之前，先形成光吸收性较高的剥离层。这时，也可以为衬底10例如具有透光性，在将衬底10剥离时，隔着衬底10照射激光，而通过剥离层的热分解来进行剥离。
另外，参照图6的流程图与图7、8的步骤图，对半导体装置100的另外一种制造方法的一个例子进行说明。如图2所示，半导体装置100的制造方法更具体来说，包含如下步骤：在衬底10上形成第一布线层1；在第一布线层1上设置第一半导体元件2；形成牺牲层11；在牺牲层11形成孔H；向孔H中埋入导电性材料；去除牺牲层11；形成第一密封材4；进行平坦化处理；在第一密封材4上形成第二布线层5；在第二布线层5上设置第二半导体元件6，并通过线接合进行布线；形成第二密封材8；使其反转，将衬底10剥离，而形成电极部9。
首先，在衬底10上形成第一布线层1。在衬底10上形成布线部件，并进行图案化处理，而形成树脂层。将树脂层进一步图案化，进而形成导电部件，并进行图案化处理等，由此获得第一布线层1。然后，将通过另外的制程所制作出的第一半导体元件2设置于第一布线层1的第一面，并进行第一布线层1与第一半导体元件2的布线。然后，形成牺牲层11。对牺牲层11进行蚀刻等，而在牺牲层11形成孔H，由此获得图7的步骤图所示的部件。
然后，向图7的步骤图所示的部件的孔H中埋入作为导电性柱3的材料的导电性材料。然后，去除牺牲层11，由此获得图8的步骤图所示的部件。这时，可以通过涂镀形成导电性柱3，也可以通过网版印刷、喷墨等将导电性材料埋入孔洞中而形成导电性柱3。
然后，形成第一密封材4，并进行平坦化处理，由此获得图4的步骤图所示的部件。此后与所述相同，由此获得图1的半导体装置100。
(第二实施方式)第二实施方式的半导体装置是第一实施方式的半导体装置的变化例。图9表示第二实施方式的半导体装置101的截面示意图。在图9的半导体装置101中，第一半导体元件2的正面与第二布线层5的第四面相接。在第二实施方式的半导体装置101与第一实施方式的半导体装置100中，第一密封材4的厚度较薄，而且导电性柱3较低。按照第一半导体元件2的第二布线层5侧的面与第二布线层5相接或将要相接的程度，第一密封材4的厚度变薄。除了这些以外，其他方面在第一实施方式与第二实施方式中共通。省略在第一实施方式与第二实施方式中共通的内容的说明。
通过使第一密封材4较薄，能够将半导体装置100的高度抑制得较低。随着存储器元件的大容量化及控制器元件的高功能化，出现存储器的封装尺寸变大的倾向，但封装件本身的大小也有限制，因此能够提供一种既抑制封装尺寸又满足被要求的功能的半导体装置。
(第三实施方式)第三实施方式的半导体装置是第一实施方式的半导体装置的变化例。图10表示第三实施方式的半导体装置102的截面示意图。图10的半导体装置102具有搭载于第二半导体元件6上的1个以上第三半导体元件12。第二半导体元件6与第三半导体元件12通过第二接合线13而连接。除了这些以外，其他方面在第一实施方式与第三实施方式中共通。省略在第一实施方式与第三实施方式中共通的内容的说明。
在图10中，是将1个第三半导体元件12设置于第二半导体元件6上，但也可以设计为将2个以上第三半导体元件12进而积层。第二半导体元件6与第三半导体元件12通过未图示的芯片粘结膜等粘接层而粘接。
第二布线层5的第三面、第三半导体元件12、第二接合线13被第二密封材8密封。第二半导体元件6与第三半导体元件12优选为功能相同的半导体元件。在第二半导体元件6及第三半导体元件12例如为存储器元件的情况下，既能够抑制封装高度，又能够获得大容量的存储器芯片。
(第四实施方式)第四实施方式的半导体装置是第一实施方式的半导体装置的变化例。图11表示第四实施方式的半导体装置103的截面示意图。第四实施方式的半导体装置103具有搭载于第二布线层5的第三面上的第四半导体元件。第四半导体元件14与第二布线层5通过第三接合线15而连接。第二布线层5上的第二半导体元件6与第四半导体元件14并列搭载。第四半导体元件及第三接合线15也被第二密封材8密封。除了这些以外，其他方面在第一实施方式与第四实施方式中共通。省略在第一实施方式与第四实施方式中共通的内容的说明。
第二半导体元件6与第四半导体元件14可以是相同的元件，也可以是不同的元件。例如，可以使用NAND存储器作为第二半导体元件6，使用DRAM作为第四半导体元件14。NAND在读写方面比DRAM慢，因此通过使用DRAM作为高速缓存，能够使半导体装置100的读写高速化。第二半导体元件6、第四半导体元件14均可以如第三实施方式的半导体装置102般积层，这种构造从大容量化的观点来看属于优选。例如，使用NAND存储器作为第二半导体元件6与第四半导体元件14两者，通过向第二半导体元件6与第四半导体元件14交替地写入，能够提高写入速度。第四实施方式的半导体装置103也能够既抑制封装高度又兼具大容量或高速读写等功能。
下面例示多个制作实施方式的半导体装置100～103的方法的变化例。也可以在形成导电性柱3后利用第一密封材4将第一布线层1的第一面、第一半导体元件2、导电性柱3密封，然后进行平坦化处理，由此获得图4的步骤图所示的部件。这时，导电性柱3也可以采用已知的电解镀法来形成。
也可以在应当形成导电性柱3的位置形成牺牲层柱后，利用第一密封材4将第一布线层1的第一面、第一半导体元件2、牺牲层柱密封，然后进行平坦化处理，并将牺牲层溶解，由此获得图3的步骤图所示的部件。
也可以采用除此以外的各种方法来获得图3或图4所示的部件。
导电性柱3除了通过Cu的涂镀以外，也可以通过Ni、Au等的涂镀来形成。另外，也可以通过埋入Ag浆等各种导电性浆来形成。
上面，对本发明的若干个实施方式进行了说明，但这些实施方式只是作为例子提出来的，并不意图限定发明的范围。这些新颖的实施方式可以采用其他各种方式来实施，在不脱离发明主旨的范围内，可以进行各种省略、替换、变更。这些实施方式及其变化例包含于发明的范围及主旨中，并且包含于权利要求书所述的发明及其同等的范围内。

Claims (5)

1.一种半导体装置，具备：第一布线层，具有第一面、及与所述第一面对向的第二面；第一半导体元件，搭载于所述第一布线层的所述第一面侧；导电性柱，设置于所述第一布线层的所述第一面侧，具有所述第一半导体元件的厚度以上的高度；第二布线层，具有第三面、及与所述第三面对向的第四面，设置于导电性柱上，且在所述第四面侧接合于所述导电性柱；第二半导体元件，搭载于所述第二布线层的所述第三面侧，通过第一接合线与所述第二布线层连接；第一密封材，将所述第一布线层的第一面、所述第一半导体元件、所述导电性柱及所述第二布线层的第四面密封；及第二密封材，将所述第二布线层的第三面、所述第二半导体元件及所述第一接合线密封。
2.根据权利要求1所述的半导体装置，其中所述第一半导体元件为控制器元件，所述第二半导体元件为存储器元件。
3.根据权利要求2所述的半导体装置，还具有存储器元件，该存储器元件是在所述第二半导体元件上搭载有1个以上的第三半导体元件；且所述第二半导体元件与所述第三半导体元件通过第二接合线而连接。
4.根据权利要求2所述的半导体装置，还具有存储器元件，该存储器元件是搭载于所述第二布线层的所述第三面上的第四半导体元件；且所述第四半导体元件与所述第二布线层通过第三接合线而连接。
5.一种半导体装置的制造方法，包含：
第一步骤，在玻璃衬底上设置第一布线层、第一半导体元件、导电性柱及第一密封材；第二步骤，第一步骤后，在所述第一密封材上形成第二布线层、第二半导体元件、第一接合线及第二密封材；及如下所述的步骤，第二步骤后，将所述衬底剥离，在所述衬底已被剥离的面形成电极部。
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