JP5769293B2 - 積層チップパッケージの製造方法 - Google Patents
積層チップパッケージの製造方法 Download PDFInfo
- Publication number
- JP5769293B2 JP5769293B2 JP2011062118A JP2011062118A JP5769293B2 JP 5769293 B2 JP5769293 B2 JP 5769293B2 JP 2011062118 A JP2011062118 A JP 2011062118A JP 2011062118 A JP2011062118 A JP 2011062118A JP 5769293 B2 JP5769293 B2 JP 5769293B2
- Authority
- JP
- Japan
- Prior art keywords
- portions
- main body
- semiconductor chip
- forming
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05551—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/821—Forming a build-up interconnect
- H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1432—Central processing unit [CPU]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1437—Static random-access memory [SRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1438—Flash memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1441—Ferroelectric RAM [FeRAM or FRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/145—Read-only memory [ROM]
- H01L2924/1453—PROM
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本体となる部分である本体形成部分を少なくとも1つ備え、本体形成部分は、複数の階層部分と、複数の貫通電極が設けられていない状態の複数の貫通孔とを含む基礎構造物を作製する工程と、
基礎構造物の本体形成部分における複数の貫通孔内に複数の貫通電極を形成する工程とを備えている。
互いに反対側を向いた第1および第2の面を有すると共に、配列された複数の半導体チップ予定部を含むアレイ前ウェハを作製する工程と、
アレイ前ウェハに対して、第1の面において開口し、後に複数の絶縁材充填孔となる複数の溝を形成する工程と、
複数の溝内に絶縁材を充填して、アレイ前ウェハの第1および第2の面に対応する第1および第2の面を有する研磨前アレイを形成する工程と、
複数の溝が複数の絶縁材充填孔となるように、研磨前アレイに対して、複数の溝が露出するまで、研磨前アレイの第2の面から研磨を行う工程とを含んでいてもよい。
以下、本発明の実施の形態について図面を参照して詳細に説明する。始めに、図1ないし図4を参照して、本発明の第1の実施の形態に係る積層チップパッケージの構成について説明する。図1は、本実施の形態に係る積層チップパッケージの斜視図である。図2は、下面側から見た図1の積層チップパッケージを示す斜視図である。図3は、図1における1つの階層部分を示す斜視図である。図4は、図1に示した積層チップパッケージの断面図である。
次に、図21および図22を参照して、本発明の第2の実施の形態について説明する。図21は、本実施の形態に係る積層チップパッケージの斜視図である。図22は、本実施の形態における配線および貫通電極の一部を示す斜視図である。
次に、本発明の第3の実施の形態について説明する。始めに、図23ないし図25を参照して、本実施の形態に係る積層チップパッケージの構成について説明する。図23は、本実施の形態に係る積層チップパッケージの斜視図である。図24は、図23における1つの階層部分を示す斜視図である。図25は、図23に示した積層チップパッケージの断面図である。
Claims (9)
- 積層された複数の階層部分と、それぞれ前記複数の階層部分の全てを貫通する複数の貫通孔とを含む本体と、
前記本体における前記複数の貫通孔内に設けられて前記複数の階層部分の全てを貫通する複数の貫通電極とを備え、
前記複数の階層部分の各々は半導体チップを含み、
前記複数の階層部分のうちの少なくとも1つは、前記半導体チップと前記複数の貫通電極とを電気的に接続する配線を含み、
前記配線は、前記複数の貫通電極にそれぞれ電気的に接続された複数の導体を含み、
前記複数の導体は、それぞれ、前記複数の貫通孔の壁面に現れて前記貫通電極の外面に接触する端面を有する積層チップパッケージを製造する方法であって、
前記本体となる部分である本体形成部分を少なくとも1つ備え、前記本体形成部分は、前記複数の階層部分と、前記複数の貫通電極が設けられていない状態の前記複数の貫通孔とを含む基礎構造物を作製する工程と、
前記基礎構造物の前記本体形成部分における前記複数の貫通孔内に前記複数の貫通電極を形成する工程とを備え、
前記基礎構造物を作製する工程は、
後に前記複数の貫通孔が形成されることによって前記基礎構造物となる初期基礎構造物を作製する工程と、
前記初期基礎構造物に前記複数の貫通孔を形成して、前記基礎構造物を形成する工程とを含み、
前記初期基礎構造物は、前記複数の貫通孔が形成される前の前記複数の階層部分である複数の初期階層部分を含み、
前記複数の初期階層部分の各々は、前記半導体チップを貫通するように形成された複数の絶縁材充填孔と、前記複数の絶縁材充填孔内に充填された絶縁材よりなる絶縁層とを含み、
前記複数の初期階層部分のうちの少なくとも1つは、前記配線を含み、
前記複数の初期階層部分のうちの少なくとも1つにおいて、前記配線が含む前記複数の導体は、それぞれ、一部が前記絶縁層の上に位置するように配置され、
前記基礎構造物を形成する工程において、前記複数の貫通孔は、前記複数の初期階層部分の前記絶縁層を貫通するように形成されることを特徴とする積層チップパッケージの製造方法。 - 前記基礎構造物は、前記少なくとも1つの本体形成部分として、前記複数の階層部分が積層された方向に直交する方向に配列された複数の本体形成部分を備え、
前記積層チップパッケージの製造方法は、更に、前記複数の貫通電極を形成する工程の後で、前記複数の本体形成部分を互いに分離して複数の本体を形成する工程を備えたことを特徴とする請求項1記載の積層チップパッケージの製造方法。 - 前記複数の貫通電極は、めっき法によって形成されることを特徴とする請求項1記載の積層チップパッケージの製造方法。
- 前記複数の導体は、それぞれ、前記複数の貫通電極が通過する電極通過孔を有し、前記電極通過孔の壁面が前記端面を構成することを特徴とする請求項1記載の積層チップパッケージの製造方法。
- 前記絶縁材は、主成分として樹脂を含むことを特徴とする請求項1記載の積層チップパッケージの製造方法。
- 前記絶縁材は、更に、前記樹脂に混合された絶縁性の粒状物を含むことを特徴とする請求項5記載の積層チップパッケージの製造方法。
- 前記基礎構造物は、前記少なくとも1つの本体形成部分として、前記複数の階層部分が積層された方向に直交する方向に配列された複数の本体形成部分を備え、
前記初期基礎構造物を作製する工程は、
それぞれ、各々が前記本体に含まれる半導体チップのいずれかとなる予定の、配列された複数の半導体チップ予定部を含む複数のチップアレイを作製する工程と、
前記複数のチップアレイを積層して前記初期基礎構造物を形成する工程とを含み、
前記積層チップパッケージの製造方法は、更に、前記複数の貫通電極を形成する工程の後で、前記複数の本体形成部分を互いに分離して複数の本体を形成する工程を備えたことを特徴とする請求項1記載の積層チップパッケージの製造方法。 - 前記複数のチップアレイを作製する工程は、1つのチップアレイを作製するための一連の工程として、
互いに反対側を向いた第1および第2の面を有すると共に、前記配列された複数の半導体チップ予定部を含むアレイ前ウェハを作製する工程と、
前記アレイ前ウェハに対して、前記第1の面において開口し、後に前記複数の絶縁材充填孔となる複数の溝を形成する工程と、
前記複数の溝内に前記絶縁材を充填して、前記アレイ前ウェハの第1および第2の面に対応する第1および第2の面を有する研磨前アレイを形成する工程と、
前記複数の溝が前記複数の絶縁材充填孔となるように、前記研磨前アレイに対して、前記複数の溝が露出するまで、前記研磨前アレイの第2の面から研磨を行う工程とを含むことを特徴とする請求項7記載の積層チップパッケージの製造方法。 - 前記複数の本体形成部分のうちの少なくとも1つにおける前記複数の階層部分は、1つ以上の第1の種類の階層部分と、1つ以上の第2の種類の階層部分とを含み、
前記第1の種類の階層部分における半導体チップは正常に動作するものであり、
前記第2の種類の階層部分における半導体チップは正常に動作しないものであり、
前記第1の種類の階層部分は前記配線を含むが、前記第2の種類の階層部分は前記配線を含まず、
前記複数のチップアレイを作製する工程は、
前記複数の半導体チップ予定部について、正常に動作する半導体チップ予定部と正常に動作しない半導体チップ予定部とを判別する工程と、
前記正常に動作しない半導体チップ予定部では前記配線を形成することなく、前記正常に動作する半導体チップ予定部では前記配線を形成する工程とを含むことを特徴とする請求項7記載の積層チップパッケージの製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/769,361 US8455349B2 (en) | 2010-04-28 | 2010-04-28 | Layered chip package and method of manufacturing same |
US12/769,361 | 2010-04-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011233868A JP2011233868A (ja) | 2011-11-17 |
JP5769293B2 true JP5769293B2 (ja) | 2015-08-26 |
Family
ID=44857605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011062118A Expired - Fee Related JP5769293B2 (ja) | 2010-04-28 | 2011-03-22 | 積層チップパッケージの製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8455349B2 (ja) |
JP (1) | JP5769293B2 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5183708B2 (ja) * | 2010-09-21 | 2013-04-17 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
JP2012209424A (ja) * | 2011-03-30 | 2012-10-25 | Tokyo Electron Ltd | 半導体装置の製造方法 |
US8344494B2 (en) * | 2011-04-11 | 2013-01-01 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
US20120319293A1 (en) * | 2011-06-17 | 2012-12-20 | Bok Eng Cheah | Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same, and method of enabling electrical communication between components of a stacked-die package |
US8426981B2 (en) * | 2011-09-22 | 2013-04-23 | Headway Technologies, Inc. | Composite layered chip package |
JP5834907B2 (ja) * | 2011-12-28 | 2015-12-24 | 富士通株式会社 | 半導体装置、半導体装置の製造方法及び電子装置 |
CN108172562A (zh) | 2012-06-29 | 2018-06-15 | 索尼公司 | 半导体装置、半导体装置的制造方法和电子设备 |
US9673183B2 (en) | 2015-07-07 | 2017-06-06 | Micron Technology, Inc. | Methods of making semiconductor device packages and related semiconductor device packages |
CN107305861B (zh) * | 2016-04-25 | 2019-09-03 | 晟碟信息科技(上海)有限公司 | 半导体装置及其制造方法 |
KR102590964B1 (ko) * | 2016-07-20 | 2023-10-18 | 삼성디스플레이 주식회사 | 정전척 |
JP2022138014A (ja) * | 2021-03-09 | 2022-09-22 | キオクシア株式会社 | 半導体装置の製造方法、半導体製造システム、及び半導体装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3750444B2 (ja) * | 1999-10-22 | 2006-03-01 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP4251421B2 (ja) * | 2000-01-13 | 2009-04-08 | 新光電気工業株式会社 | 半導体装置の製造方法 |
JP3875867B2 (ja) * | 2001-10-15 | 2007-01-31 | 新光電気工業株式会社 | シリコン基板の穴形成方法 |
US6750516B2 (en) * | 2001-10-18 | 2004-06-15 | Hewlett-Packard Development Company, L.P. | Systems and methods for electrically isolating portions of wafers |
JP2003163324A (ja) | 2001-11-27 | 2003-06-06 | Nec Corp | ユニット半導体装置及びその製造方法並びに3次元積層型半導体装置 |
JP4795677B2 (ja) * | 2004-12-02 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法 |
KR100743648B1 (ko) * | 2006-03-17 | 2007-07-27 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 시스템 인 패키지의 제조방법 |
JP2008187061A (ja) | 2007-01-31 | 2008-08-14 | Elpida Memory Inc | 積層メモリ |
KR100845006B1 (ko) * | 2007-03-19 | 2008-07-09 | 삼성전자주식회사 | 적층 칩 패키지 및 그 제조 방법 |
KR100895813B1 (ko) * | 2007-06-20 | 2009-05-06 | 주식회사 하이닉스반도체 | 반도체 패키지의 제조 방법 |
US7964976B2 (en) * | 2008-08-20 | 2011-06-21 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
-
2010
- 2010-04-28 US US12/769,361 patent/US8455349B2/en not_active Expired - Fee Related
-
2011
- 2011-03-22 JP JP2011062118A patent/JP5769293B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2011233868A (ja) | 2011-11-17 |
US8455349B2 (en) | 2013-06-04 |
US20110266692A1 (en) | 2011-11-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5769293B2 (ja) | 積層チップパッケージの製造方法 | |
US8618646B2 (en) | Layered chip package and method of manufacturing same | |
JP5102339B2 (ja) | 積層チップパッケージの製造方法 | |
JP5275915B2 (ja) | 積層チップパッケージ | |
JP5461077B2 (ja) | 積層チップパッケージ | |
JP5535560B2 (ja) | メモリデバイスを実現する積層チップパッケージ | |
JP5432604B2 (ja) | 積層チップパッケージの製造方法 | |
JP5451204B2 (ja) | 積層チップパッケージの製造方法 | |
CN103208482B (zh) | 通孔组件模块及其形成方法 | |
JP5004311B2 (ja) | 積層チップパッケージおよびその製造方法 | |
JP5154667B2 (ja) | 積層チップパッケージおよびその製造方法 | |
US20100200959A1 (en) | Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same | |
JP4927194B2 (ja) | 積層チップパッケージの製造方法 | |
JP5228068B2 (ja) | 積層チップパッケージおよびその製造方法 | |
JP4948635B2 (ja) | 積層チップパッケージの製造方法 | |
US8653639B2 (en) | Layered chip package and method of manufacturing same | |
CN107403785A (zh) | 电子封装件及其制法 | |
JP5154253B2 (ja) | 電子部品パッケージ | |
US8344494B2 (en) | Layered chip package and method of manufacturing same | |
US8441112B2 (en) | Method of manufacturing layered chip package | |
US8426979B2 (en) | Composite layered chip package | |
US8358015B2 (en) | Layered chip package and method of manufacturing same | |
US8253257B2 (en) | Layered chip package and method of manufacturing the same | |
US8652877B2 (en) | Method of manufacturing layered chip package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20131015 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20141020 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141028 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141212 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150617 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150619 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5769293 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |