CN111725186A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN111725186A
CN111725186A CN201910773719.1A CN201910773719A CN111725186A CN 111725186 A CN111725186 A CN 111725186A CN 201910773719 A CN201910773719 A CN 201910773719A CN 111725186 A CN111725186 A CN 111725186A
Authority
CN
China
Prior art keywords
semiconductor element
wiring layer
substrate
bonding wire
resin composition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910773719.1A
Other languages
English (en)
Other versions
CN111725186B (zh
Inventor
后藤善秋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Toshiba Memory Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of CN111725186A publication Critical patent/CN111725186A/zh
Application granted granted Critical
Publication of CN111725186B publication Critical patent/CN111725186B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

实施方式的半导体装置具有：衬底；第1半导体元件设置在衬底上的第1树脂组合物上；第2半导体元件设置在衬底上的第2树脂组合物上；第3半导体元件设置在衬底上，且夹于第1半导体元件与第2半导体元件之间；第1配线层设置在第1半导体元件上，与第1半导体元件连接，且利用第1接合线与衬底连接；第4半导体元件设置在第1配线层上，且利用第2接合线与第1配线层连接；第2配线层设置在第2半导体元件上，与第2半导体元件连接，且利用第3接合线与衬底连接。第1接合线设置在第1配线层的除与朝向第2配线层的一侧为相反侧以外的部分。第3接合线设置在第2配线层的除与朝向第1配线层的一侧为相反侧以外的部分。

Description

半导体装置
[相关申请]
本申请基于2019年3月22日提出申请的先前日本专利申请第2019-054415号的优先权利益且追求该利益，其全部内容是通过引用而包含在本文中。
技术领域
此处所说明的多种实施方式全部涉及一种半导体装置。
背景技术
对于使用了存储器芯片的半导体装置，正研究各种封装体布局。存储器的半导体装置被要求大容量化、小型化或读写高速化等特性。
当想要使利用了存储器芯片的半导体装置高速化时，控制器芯片容易变大。当想要将更多存储器芯片呈阶梯状积层以实现大容量化时，配置控制器芯片及存储器芯片的平面空间会变宽。在想要使存储器芯片的设计规则变得严格(使配线宽度变窄)，而增大平均每一个存储器芯片的存储容量的情况下，也有平均每一个芯片大小比以往大的情况。
因此，当不使半导体装置的封装体大小变大而使芯片大小变大时，有难以将控制器芯片与存储器芯片平面地配置于衬底上的情况。也想到如下情况：以控制器芯片与存储器芯片不干涉的方式，将外形尺寸比存储器芯片小的间隔芯片贴附在衬底，将存储器芯片配置在比控制器芯片高的位置。
然而，所述情况需要于对镜面晶圆进行BSG(Back Side grinding，背面研磨)加工，并贴附裸片粘结膜之后，将间隔芯片呈所需大小切下，并贴附于衬底等的步骤，所以半导体装置的制造费用提高。在搭载相同存储器芯片片数的情况下，相应于间隔芯片的高度，半导体装置变厚，而难以薄型化。控制器芯片由于比存储器芯片小，所以在使用间隔芯片的情况下，存储器芯片间会出现空余空间。空间效率上不利且难以小型化。
发明内容
本发明的实施方式有助于半导体装置的小型化、薄型化。
实施方式的半导体装置具有：衬底；第1半导体元件，设置在衬底上的第1树脂组合物上；第2半导体元件，设置在衬底上的第2树脂组合物上；第3半导体元件，设置在衬底上，且夹于第1半导体元件与第2半导体元件之间；第1配线层，设置在第1半导体元件上，与第1半导体元件连接，且利用第1接合线与衬底连接；第4半导体元件，设置在第1配线层上，利用第2接合线与第1配线层连接；第2配线层，设置在第2半导体元件上，与第2半导体元件连接，且利用第3接合线与衬底连接；及第5半导体元件，设置在第2配线层上，且利用第4接合线与第2配线层连接。第1接合线设置在第1配线层的除与朝向第2配线层的一侧为相反侧以外的部分。第3接合线设置在第2配线层的除与朝向第1配线层的一侧为相反侧以外的部分。
根据上述构成，可实现半导体装置的小型化、薄型化。
附图说明
图1是实施方式的半导体装置的剖视图。
图2是实施方式的半导体装置的配线示意图。
图3是实施方式的半导体装置的剖视图。
具体实施方式
以下，参照附图对实施方式进行说明。
在本说明书中，对若干个要素附加多个表达方式的例子。此外，这些表达方式的例子仅为例示，并非否定通过其它表达方式来表达所述要素。另外，对于未附加多个表达方式的要素，也可通过其它表达方式来表达。
另外，附图是示意图，有厚度与平面尺寸的关系或各层的厚度的比率等与实物不同的情况。另外，也有在附图彼此之间包含相互的尺寸关系或比率不同的部分的情况。关于对称配置的构件，省略一部分共通的说明。
(实施方式)图1表示实施方式的半导体装置100的剖视图。半导体装置100是包含例如作为控制器芯片的半导体元件及例如作为半导体存储器芯片的半导体元件的半导体封装体。更具体来说，半导体装置100是例如所谓的BGA-SSD(Ball Grid Array-SolidState Drive，球栅阵列-固态驱动器)，多个半导体存储器芯片与控制器一体地构成为一个BGA型封装体。
关于图1的半导体装置100，示出衬底1、第1半导体元件2、第1树脂组合物3、第3半导体元件4、接合线5、7、10、11、15、17、20、21、第1配线层6、第3树脂组合物8、第4半导体元件9、粘接层12、22、第2半导体元件13、第2树脂组合物14、第2配线层16、第4树脂组合物18、第5半导体元件19及密封材23。
衬底1是半导体元件2、4、9、13、19的支撑衬底。衬底1更具体来说是多层配线衬底。在衬底1的第1面侧设置着半导体元件2、4、9、13、19。衬底1的与第1面对向的第2面侧设置着用来与半导体装置100的外部连接的图1中未图示的焊料球等半球状的电极。
半导体装置100例如包含作为存储器芯片的第1半导体元件2、第2半导体元件13、第4半导体元件9及第5半导体元件19。第1半导体元件2及第2半导体元件13设置在衬底1侧。第4半导体元件9是例如设置在第1半导体元件2上的1个以上的存储器芯片。第5半导体元件19是例如设置在第2半导体元件13上的1个以上的存储器芯片。
存储器芯片是进行数据读写的半导体芯片。作为非易失性存储器芯片，能使用NAND(Not And，与非)存储器芯片、相变存储器芯片、电阻变化存储器芯片、铁电存储器芯片及磁存储器芯片等。作为易失性存储器芯片，能使用DRAM(Dynamic Random AccessMemory，动态随机存储存储器)等。实施方式中所使用的存储器芯片优选除个体差异以外为同一电路且同一构造的半导体芯片。另外，在本实施方式中，能使用非易失性存储器芯片、易失性存储器芯片作为存储器芯片。作为半导体元件，也能够使用除存储器芯片以外的半导体芯片。
以隔着第3半导体元件4的方式配置存储器芯片等积层体，从而兼顾大容量与高速化，所以第1半导体元件2、第2半导体元件13、第4半导体元件9及第5半导体元件19的纵横比(长边(长度方向的侧面的长度)/短边(宽度方向的侧面的长度))优选1.5以上3.5以下。第1半导体元件2的朝向第2半导体元件13侧的长边与第2半导体元件13的朝向第1半导体元件2侧的长边对向。
第1半导体元件2是设置在衬底1上的半导体芯片。更具体来说，第1半导体元件2是设置在衬底1上的第1树脂组合物3上的存储器芯片。
第1树脂组合物3是裸片粘结膜(DAF；Die Attach Film)等粘接性树脂组合物。第1树脂组合物3设置在衬底1上，且与第1半导体元件2粘接。第1树脂组合物3中，存在连接第3半导体元件4与衬底1的1群接合线，也就是1条以上的第5接合线5。由于在第1树脂组合物3中埋入着导线，所以将第1半导体元件2与第1树脂组合物3积层所得的构造是被称作所谓FOW(Film on Wire，膜覆线)的构造。
第3半导体元件4是利用厚度为例如5μm到20μm的DAF等粘接剂固定在衬底1上的半导体芯片。第3半导体元件4例如为存储器芯片的控制器。第3半导体元件4与半导体装置100的外部连接，控制存储器芯片的读写，例如进行读写高速化或错误订正等。第3半导体元件4并非倒装芯片，所以第3半导体元件4的电极垫配置在与衬底1侧为相反侧的一侧(存储器芯片侧)。以下，将第1半导体元件2称为第1存储器芯片2，将第2半导体元件13称为第2存储器芯片13，将第3半导体元件4称为控制器芯片4，将第4半导体元件9称为第3存储器芯片9，将第5半导体元件19称为第4存储器芯片19
控制器芯片4以夹于第1存储器芯片2与第2存储器芯片13之间的方式配置。控制器芯片4的具有电极垫的面朝向与衬底1侧为相反侧的一侧，存在电极垫的面的至少一部分，更具体来说，存在电极垫的面的至少中央由密封材23密封。在图1的示意图中，在第1树脂组合物3与第2树脂组合物14之间配置着控制器芯片4，在第1树脂组合物3与控制器芯片4之间设置着密封材23，在第2树脂组合物14与控制器芯片4之间也设置着密封材23。
第1存储器芯片2与第3存储器芯片9经由树脂组合物或粘接剂12在Y方向上积层所得的构造和第2存储器芯片13与第4存储器芯片19经由树脂组合物或粘接剂22积层所得的构造优选以控制器芯片4为中心对称地配置。
控制器芯片4配置在比第1存储器芯片2更靠衬底1侧，且配置在比第2存储器芯片13更靠衬底1侧。通过使控制器芯片4近接于衬底1，且配置在衬底1的中心侧，能够效率良好地配置对称的存储器芯片的积层构造，且兼顾高容量与读写高速化。从所述观点来看，连接第1存储器芯片2的中心与第2存储器芯片13的中心的假想线段的中心优选以在衬底1与控制器芯片4的积层方向(Y方向)上，与控制器芯片4重叠的方式配置控制器芯片4。
第5接合线5是连接衬底1与控制器芯片4的接合线。第5接合线5将图1中未图示的衬底1上的电极垫与控制器芯片4的电极垫连接。第5接合线5位于第1存储器芯片2与衬底1之间。第5接合线5的衬底1侧的至少一部分埋入到第1树脂组合物3中而被密封。在包含第5接合线5的未埋入到第1树脂组合物3中的部分时，该部分由密封材23密封。
第1配线层6是设置在第1存储器芯片2上的再配线层。第1配线层6与第1存储器芯片2连接。第1配线层6与存储器芯片2直接相接，第1存储器芯片2的电极垫与第1配线层6的配线电连接。通过使用第1配线层6，能够设为如下构造：将连接第1存储器芯片2与衬底1的第1接合线7设置在第1配线层6的除与朝向第2配线层16的一侧为相反侧以外的部分。第1配线层6的大小、更具体来说为朝向第1存储器芯片2的面(及相反侧的面)的大小比第1存储器芯片2小。
第1接合线7是连接第1配线层6与衬底1的配线。第1接合线7的一部分埋入到第3树脂组合物8中而被密封。第1接合线7的未埋入到第3树脂组合物8中的部分由密封材23密封。第1接合线7将第1配线层6的除与朝向第1存储器芯片2的面为相反侧的电极垫和衬底1上的电极垫连接。
第3树脂组合物8是设置在第1配线层6与第3存储器芯片9之间的DAF等粘接性树脂组合物。在第3树脂组合物8，埋入着第1接合线7的一部分，位于最靠第1存储器芯片2侧的第3存储器芯片9A与第3树脂组合物8积层所得的构造被称作FOW。
从衬底1到第3树脂组合物8的第1存储器芯片2侧的面为止的距离优选比从衬底1到控制器芯片4的上表面为止的距离长。当第1树脂组合物3过薄时，第5接合线5与第1存储器芯片2的衬底1侧的面接触。当从衬底1到第3树脂组合物8的第1存储器芯片2侧的面为止的距离过短时，第5接合线5与第3树脂组合物8的衬底1侧的面接触。衬底1与控制器芯片4也能够利用从控制器芯片4的上表面在Z方向上延伸的接合线(例如图2的接合线24)连接，但连接控制器芯片4与衬底1的接合线会变得过密。
第3存储器芯片9(9A、9B、9C、9D)是设置在第3树脂组合物8上的1个以上的存储器芯片群。在第3存储器芯片9之间，设置着粘接层12(12A、12B、12C)，将第3存储器芯片9粘接。第1配线层6与第3存储器芯片9是利用第2接合线10连接。第3存储器芯片9彼此是利用第7接合线11(11A、11B、11C)连接。
第2接合线10是连接第1配线层6与第3存储器芯片9的配线。第2接合线10是如下导线：从第1配线层6的与控制器芯片4侧为相反侧的电极垫连接位于第1配线层6的上侧且比第1配线层6更靠半导体装置100的中心侧的第3存储器芯片9的电极垫。
第7接合线11(11A、11B、11C)是将第3存储器芯片9间电连接的配线。第7接合线11的配线的朝向与第2接合线10的配线的朝向相同，但与第1接合线7的配线的朝向不同。
粘接层12(12A、12B、12C)是配置在第3存储器芯片9彼此之间的粘接性树脂层。粘接层12例如为DAF。
第2存储器芯片13是如下半导体芯片：从控制器芯片4观察，设置在与第1存储器芯片2为相反侧。第2存储器芯片13设置在衬底1上的第2树脂组合物14上。
第2树脂组合物14是DAF等粘接性树脂组合物。第2树脂组合物14设置在衬底1上，且与第2存储器芯片13粘接。第2树脂组合物14从控制器芯片4观察，设置在与第1树脂组合物3为相反侧。在第2树脂组合物14中，存在连接控制器芯片4与衬底1的1群接合线也就是1条以上的第6接合线15。在第2树脂组合物14中埋入着导线，所以将第2存储器芯片13与第2树脂组合物14积层所得的构造是被称作所谓FOW(Film on Wire)的构造。
第6接合线15是连接衬底1与控制器芯片4的接合线。第6接合线15从控制器芯片4观察，设置在与第5接合线5为相反侧。第6接合线15将图1中未图示的衬底1上的电极垫与控制器芯片4的电极垫连接。第6接合线15位于第2存储器芯片13与衬底1之间。第6接合线15的衬底1侧的至少一部分埋入到第2树脂组合物14中而被密封。在包含第6接合线15的未埋入到第2树脂组合物14的部分时，该部分由密封材23密封。
第2配线层16是设置在第2存储器芯片13上的再配线层。第2配线层16从控制器芯片4观察，设置在与第1配线层6为相反侧。第2配线层16与第2存储器芯片13连接。第2配线层16与第2存储器芯片13直接相接，第2存储器芯片13的电极垫与第2配线层16的配线电连接。通过使用第2配线层16，能够设为如下构造：将连接第2存储器芯片13与衬底1的第3接合线17设置在第2配线层16的除与朝向第1配线层6的一侧为相反侧以外的部分。第2配线层16的大小、更具体来说为朝向第2存储器芯片13的面(及相反侧的面)的大小比第2存储器芯片13小。
第3接合线17是将第2配线层16与衬底1连接的配线。第3接合线17从控制器芯片4观察，设置在与第1接合线7为相反侧。第3接合线17的一部分埋入到第4树脂组合物18中而被密封。第3接合线17的未埋入到第4树脂组合物18中的部分由密封材23密封。第3接合线17将第2配线层16的与朝向第2存储器芯片13的面为相反侧的电极垫和衬底1上的电极垫连接。
第4树脂组合物18是设置在第2配线层16与第4存储器芯片19之间的DAF等粘接性树脂组合物。第4树脂组合物18从控制器芯片4观察，设置在与第3树脂组合物8为相反侧。在第4树脂组合物18，埋入着第3接合线17的一部分，位于最靠第2存储器芯片13侧的第4存储器芯片19A与第4树脂组合物18积层所得的构造被称作FOW。
第4存储器芯片19(19A、19B、19C、19D)是设置在第4树脂组合物18上的1个以上的存储器芯片群。第4存储器芯片19从控制器芯片4观察，设置在与第3存储器芯片9为相反侧。在第4存储器芯片19之间，设置着粘接层22(22A、22B、22C)，将第4存储器芯片19粘接。第2配线层16与第4存储器芯片19由第4接合线20连接。第4存储器芯片19彼此由第8接合线21(21A、21B、21C)连接。
第4接合线20是将第2配线层16与第4存储器芯片19连接的配线。第4接合线20从控制器芯片4观察，设置在与第2接合线10为相反侧。第4接合线20是如下导线：从第2配线层16的与控制器芯片4侧为相反侧的电极垫连接位于第2配线层16的上侧且比第2配线层16更靠半导体装置100的中心侧的第4存储器芯片19的电极垫。
第8接合线21(21A、21B、21C)是将第4存储器芯片19间电连接的配线。第8接合线21的配线的朝向与第4接合线20的配线的朝向相同，但与第3接合线17的配线的朝向不同。
粘接层22(22A、22B、22C)是配置在第4存储器芯片19彼此之间的粘接性树脂层。粘接层22例如为DAF。
密封材23将设置在衬底1上的构件密封。密封材23也为半导体装置100的外装材。密封材23是较硬的树脂组合物，更具体来说是模具树脂。
此处，使用图2的半导体装置100的配线示意图，对半导体装置100内的配线与构成构件的配置进行说明。图2的示意图中示出从图1的示意图的上侧观察到的配线。在第1配线层6及第2配线层16设置着除电极垫以外的配线，但在图2的示意图中，第1配线层6及第2配线层16的配线省略。示意性地示出衬底1、第1存储器芯片2、第2存储器芯片13、第1配线层6及第2配线层16间的配线。衬底1的电极垫是以中空的四方形表示。控制器芯片4的电极垫是以黑色的四方形表示。设置在第1配线层6的与朝向第2配线层16的一侧为相反侧的电极垫是以三角形表示。设置在第2配线层16的与朝向第1配线层6的一侧为相反侧的电极垫是以三角形表示。设置在第1配线层6的除与朝向第2配线层16的一侧为相反侧以外的电极垫是以圆表示。设置在第2配线层16的除与朝向第1配线层6的一侧为相反侧以外的电极垫是以圆表示。
首先，对控制器芯片4的配线进行说明。控制器芯片4利用接合线(5、15、24)与衬底1连接。不存在将控制器芯片4与存储器芯片直接连接的配线。控制器芯片4与存储器芯片的配线均经过第1配线层6或第2配线层16、及衬底1。第5接合线5从控制器芯片4延伸到第1存储器芯片2的下侧，将控制器芯片4与衬底1连接。在第2存储器芯片13侧也同样地存在第6接合线15。优选在图1的深度方向(Z方向)上也设置着连接控制器芯片4与衬底1的接合线25。与控制器芯片4连接的接合线也位于存储器芯片的下侧，所以即使高密度地配置半导体装置100内的芯片，也能够以布局上无较大制约的方式进行配线。
其次，对第1配线层6与衬底1的配线进行说明。半导体装置100中所使用的存储器芯片全部相同，所以如果不使用第1配线层6，那么第1存储器芯片2与衬底1的配线将从与第2接合线10连接的第1存储器芯片2的电极垫朝向衬底1的外周边(对向或近接的外周边)侧延伸。在图1及图2中，从存储器芯片的与控制器芯片4侧为相反侧的长边侧朝向与控制器芯片4侧为相反侧未形成有接合线。如果从存储器芯片的与控制器芯片4侧为相反侧的长边侧朝向与控制器芯片4侧为相反侧形成有接合线，那么必须相应于接合线的量，使衬底1及半导体装置100均变大，从而导致半导体装置100大型化，难以进行控制器芯片4的配线。实施方式中，第1接合线7设置在第1配线层6的与朝向第2配线层16的一侧为相反侧以外的部分。也就是说，连接第1配线6与衬底1的第1接合线7未跨及第1存储器芯片2的与控制器芯片4侧为相反侧的侧面。在图2中，连接第1配线层6与衬底1的第1接合线7形成在三方向。第1接合线7A以从第1配线层6的长边侧朝向第2配线层6侧的方式设置。第1接合线7B、7C从第1配线层6的短边侧设置。也能够省略第1接合线7A、7B、7C的任一个或任两个。也就是说，仅在第1配线层6的一边侧或两边侧设置着第1接合线7的方式也包含在实施方式中。第1配线层6的配线布局是在满足所述主要条件的范围内任意设计。
第2配线层16与衬底1的配线和第1配线层6与衬底1的配线相同。实施方式中，第2接合线17设置在第2配线层16的除与朝向第1配线层6的一侧为相反侧以外的部分。也就是说，连接第2配线层16与衬底1的第3接合线17未跨及第2存储器芯片13的与控制器芯片4侧为相反侧的侧面。
从最下段的存储器芯片2、13到衬底1，无在外侧接合的导线，所以与此相应，能够使半导体装置的外形尺寸变小。在不变更外形尺寸的情况下，也能够收纳更大的存储器芯片、及为了实现高速化而更大的控制器芯片4。如果将最下段的存储器芯片的搭载位置以相应于无导线的量配置在靠外侧，那么最上段的存储器芯片彼此之间隔能够在基本消失之前，供将更多存储器芯片呈阶梯状积层。实施方式的半导体装置100有助于半导体装置的小型化、大容量化及高速化。
通过采用实施方式的半导体层100的布局，使用相同芯片的情况将有助于小型化及薄型化。而且，通过使芯片大小变大或增加存储器芯片的数量，能够实现半导体装置100的大容量化或高速化。在该情况下，通过采用实施方式的半导体装置100的布局，即使芯片变大或芯片数量增加，也能够有效率地配置芯片并进行配线，所以能够构成小型化且薄型的半导体装置100。
比较方式的半导体装置存在如下方式：利用例如100μm以上的较厚的DAF覆盖控制器芯片与接合线，且在其上设置硅或聚酰亚胺的间隔片，在间隔片上积层存储器芯片。在这种方式中，相应于DAF或间隔片的厚度，半导体装置的Y方向的高度变高，而难以薄型化。
在实施方式的半导体装置100中，由于不使用间隔片而将控制器芯片4与存储器芯片积层，所以也能够使半导体装置100的Y方向的高度变低，实施方式的构造也有助于半导体装置100的薄型化。
图3中示出半导体装置100的变化例的半导体装置101的剖面示意图。图3所示的半导体装置101将控制器芯片4的一部分埋入到第1树脂组合物3及第2树脂组合物14中并密封。通过将控制器芯片4的一部分埋入，使存储器芯片配置在比图1的方式的半导体装置100更靠控制器芯片4侧，由此能够使半导体装置101的宽度(X方向的距离)变得更窄。即使控制器芯片4大型化，根据该构造，也会使半导体装置101的宽度变窄，而有助于半导体装置101的小型化。第5接合线5的一部分或全部被埋入到第1树脂组合物3中。第6接合线15的一部分或全部被埋入到第2树脂组合物14中。
以上，对本发明的若干个实施方式进行了说明，但这些实施方式是作为例子提出的，并不意图限定发明的范围。这些新颖的实施方式能以其它多种方式实施，能在不脱离发明主旨的范围内进行各种省略、置换及变更。这些实施方式或其变化例包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。

Claims (5)

1.一种半导体装置，具有：
衬底；
第1半导体元件，设置在所述衬底上的第1树脂组合物上；
第2半导体元件，设置在所述衬底上的第2树脂组合物上；
第3半导体元件，设置在所述衬底上，且夹于所述第1半导体元件与第2半导体元件之间；
第1配线层，设置在所述第1半导体元件上，与所述第1半导体元件连接，且利用第1接合线与所述衬底连接；
第4半导体元件，设置在所述第1配线层上，利用第2接合线与所述第1配线层连接；
第2配线层，设置在所述第2半导体元件上，与所述第2半导体元件连接，且利用第3接合线与所述衬底连接；及
第5半导体元件，设置在所述第2配线层上，且利用第4接合线与所述第2配线层连接；且
所述第1接合线设置在所述第1配线层的除与朝向所述第2配线层的一侧为相反侧以外的部分，
所述第3接合线设置在所述第2配线层的除与朝向所述第1配线层的一侧为相反侧以外的部分。
2.根据权利要求1所述的半导体装置，其中所述第1半导体元件、第2半导体元件、第4半导体元件及第5半导体元件是存储器芯片，
所述第3半导体元件是控制器芯片，
连接所述第1半导体元件的中心与所述第2半导体元件的中心的假想线段的中心在所述衬底与所述第3半导体元件的积层方向上，与所述第3半导体元件重叠。
3.根据权利要求1所述的半导体装置，其中所述第3半导体元件的一部分密封在所述第1树脂组合物及第2树脂组合物中。
4.根据权利要求1所述的半导体装置，其中所述第3半导体元件还具有与所述衬底连接的第5接合线及第6接合线，
所述第5接合线的至少一部分密封在所述第1树脂组合物中，
所述第6接合线的至少一部分密封在所述第2树脂组合物中。
5.根据权利要求1至4中任一项所述的半导体装置，还具有：第3树脂组合物，设置在所述第1半导体元件与所述第4半导体元件之间；及
第4树脂组合物，设置在所述第2半导体元件与所述第5半导体元件之间；且
所述第1接合线的一部分密封在所述第3树脂组合物中，
所述第2接合线的一部分密封在所述第4树脂组合物中。
CN201910773719.1A 2019-03-22 2019-08-21 半导体装置 Active CN111725186B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019054415A JP7242366B2 (ja) 2019-03-22 2019-03-22 半導体装置
JP2019-054415 2019-03-22

Publications (2)

Publication Number Publication Date
CN111725186A true CN111725186A (zh) 2020-09-29
CN111725186B CN111725186B (zh) 2023-11-24

Family

ID=72514827

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910773719.1A Active CN111725186B (zh) 2019-03-22 2019-08-21 半导体装置

Country Status (4)

Country Link
US (1) US10840220B2 (zh)
JP (1) JP7242366B2 (zh)
CN (1) CN111725186B (zh)
TW (1) TWI722541B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112582286B (zh) * 2020-12-10 2022-10-11 青岛信芯微电子科技股份有限公司 一种封装方法、装置、设备及介质
JP2022135727A (ja) * 2021-03-05 2022-09-15 キオクシア株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111062A (ja) * 2007-10-29 2009-05-21 Toshiba Corp 半導体装置及びその製造方法
US20100270689A1 (en) * 2009-04-27 2010-10-28 Samsung Electronics Co., Ltd. Semiconductor packages and electronic systems including the same
CN103178054A (zh) * 2011-12-22 2013-06-26 三星电子株式会社 包括堆叠半导体芯片和再分布层的半导体封装件
US20180277529A1 (en) * 2017-03-23 2018-09-27 Toshiba Memory Corporation Semiconductor package

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101563630B1 (ko) * 2009-09-17 2015-10-28 에스케이하이닉스 주식회사 반도체 패키지
JP5918664B2 (ja) 2012-09-10 2016-05-18 株式会社東芝 積層型半導体装置の製造方法
KR102116979B1 (ko) * 2013-10-28 2020-06-05 삼성전자 주식회사 적층 반도체 패키지
KR102247916B1 (ko) 2014-01-16 2021-05-04 삼성전자주식회사 계단식 적층 구조를 갖는 반도체 패키지
JP2017055052A (ja) 2015-09-11 2017-03-16 株式会社東芝 半導体装置および半導体装置の製造方法
US10109617B2 (en) 2016-07-21 2018-10-23 Samsung Electronics Co., Ltd. Solid state drive package
KR102576764B1 (ko) * 2016-10-28 2023-09-12 에스케이하이닉스 주식회사 비대칭 칩 스택들을 가지는 반도체 패키지
US9899347B1 (en) * 2017-03-09 2018-02-20 Sandisk Technologies Llc Wire bonded wide I/O semiconductor device
KR20180130043A (ko) 2017-05-25 2018-12-06 에스케이하이닉스 주식회사 칩 스택들을 가지는 반도체 패키지
JP2020053655A (ja) * 2018-09-28 2020-04-02 キオクシア株式会社 半導体装置及び半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111062A (ja) * 2007-10-29 2009-05-21 Toshiba Corp 半導体装置及びその製造方法
US20100270689A1 (en) * 2009-04-27 2010-10-28 Samsung Electronics Co., Ltd. Semiconductor packages and electronic systems including the same
CN103178054A (zh) * 2011-12-22 2013-06-26 三星电子株式会社 包括堆叠半导体芯片和再分布层的半导体封装件
US20180277529A1 (en) * 2017-03-23 2018-09-27 Toshiba Memory Corporation Semiconductor package

Also Published As

Publication number Publication date
US20200303345A1 (en) 2020-09-24
JP7242366B2 (ja) 2023-03-20
JP2020155683A (ja) 2020-09-24
TWI722541B (zh) 2021-03-21
US10840220B2 (en) 2020-11-17
CN111725186B (zh) 2023-11-24
TW202036834A (zh) 2020-10-01

Similar Documents

Publication Publication Date Title
US10811387B2 (en) Methods of operating microelectronic devices including a controller
JP4921937B2 (ja) 半導体集積回路
JP4498403B2 (ja) 半導体装置と半導体記憶装置
JP4489100B2 (ja) 半導体パッケージ
JP2001217383A (ja) 半導体装置およびその製造方法
US20130114323A1 (en) Semiconductor device and data storage apparatus
US7745932B2 (en) Semiconductor package, semiconductor package module including the semiconductor package, and methods of fabricating the same
US20110115100A1 (en) Semiconductor device
CN111725186B (zh) 半导体装置
US20210074679A1 (en) Semiconductor package including stacked semiconductor chips
KR102628536B1 (ko) 적층 칩 구조를 가지는 반도체 패키지
TWI529918B (zh) 半導體記憶卡
US7030489B2 (en) Multi-chip module having bonding wires and method of fabricating the same
JP2011222807A (ja) 半導体装置
US20030015803A1 (en) High-density multichip module and method for manufacturing the same
JP2009111062A (ja) 半導体装置及びその製造方法
US11830849B2 (en) Semiconductor device with unbalanced die stackup
US11721671B2 (en) Semiconductor package
JP2008187076A (ja) 回路装置およびその製造方法
CN111725175A (zh) 半导体装置及半导体装置的制造方法
US11756918B2 (en) Semiconductor device
US20230223327A1 (en) Package base substrate and semiconductor package including the same
JP2023183142A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: Tokyo

Applicant after: Kaixia Co.,Ltd.

Address before: Tokyo

Applicant before: TOSHIBA MEMORY Corp.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant