TWI697074B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI697074B
TWI697074B TW104112256A TW104112256A TWI697074B TW I697074 B TWI697074 B TW I697074B TW 104112256 A TW104112256 A TW 104112256A TW 104112256 A TW104112256 A TW 104112256A TW I697074 B TWI697074 B TW I697074B
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Taiwan
Prior art keywords
metal layer
electrode
semiconductor device
semiconductor element
bump
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TW104112256A
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English (en)
Chinese (zh)
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TW201541558A (zh
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脇山悟
中村卓矢
清水完
林利彦
城直樹
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日商新力股份有限公司
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    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/018—Manufacture or treatment of image sensors covered by group H10F39/12 of hybrid image sensors
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    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
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    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/809—Constructional details of image sensors of hybrid image sensors
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    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
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    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01933—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01935—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01938—Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
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    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H10W72/01953—Changing the shapes of bond pads by etching
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07255—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in materials
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/251—Materials
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/874—On different surfaces
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    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
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    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
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    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
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    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
TW104112256A 2014-04-23 2015-04-16 半導體裝置及其製造方法 TWI697074B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2014-088804 2014-04-23
JP2014088804 2014-04-23
JP2014256186A JP6424610B2 (ja) 2014-04-23 2014-12-18 半導体装置、および製造方法
JP2014-256186 2014-12-18

Publications (2)

Publication Number Publication Date
TW201541558A TW201541558A (zh) 2015-11-01
TWI697074B true TWI697074B (zh) 2020-06-21

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Application Number Title Priority Date Filing Date
TW104112256A TWI697074B (zh) 2014-04-23 2015-04-16 半導體裝置及其製造方法

Country Status (6)

Country Link
US (3) US10600838B2 (https=)
JP (1) JP6424610B2 (https=)
KR (3) KR20220030314A (https=)
CN (2) CN105981160B (https=)
TW (1) TWI697074B (https=)
WO (1) WO2015162872A1 (https=)

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JP6424610B2 (ja) 2014-04-23 2018-11-21 ソニー株式会社 半導体装置、および製造方法
US9564418B2 (en) * 2014-10-08 2017-02-07 Micron Technology, Inc. Interconnect structures with intermetallic palladium joints and associated systems and methods
KR102720747B1 (ko) * 2015-03-12 2024-10-23 소니그룹주식회사 촬상 장치, 제조 방법 및 전자 기기
US9812555B2 (en) * 2015-05-28 2017-11-07 Semiconductor Components Industries, Llc Bottom-gate thin-body transistors for stacked wafer integrated circuits
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JP6639188B2 (ja) * 2015-10-21 2020-02-05 ソニーセミコンダクタソリューションズ株式会社 半導体装置、および製造方法
CN106057692B (zh) * 2016-05-26 2018-08-21 河南工业大学 一种三维集成电路堆栈集成方法及三维集成电路
MX387378B (es) * 2016-11-22 2025-03-18 Senju Metal Industry Co Metodo de soldadura.
JP6685470B2 (ja) * 2017-03-30 2020-04-22 三菱電機株式会社 半導体装置およびその製造方法、ならびに電力変換装置
KR102380823B1 (ko) 2017-08-16 2022-04-01 삼성전자주식회사 발열체를 포함하는 칩 구조체
US11257745B2 (en) * 2017-09-29 2022-02-22 Intel Corporation Electroless metal-defined thin pad first level interconnects for lithographically defined vias
CN110660809B (zh) * 2018-06-28 2023-06-16 西部数据技术公司 包含分支存储器裸芯模块的垂直互连的半导体装置
US10622321B2 (en) 2018-05-30 2020-04-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structures and methods of forming the same
KR102830541B1 (ko) 2020-09-23 2025-07-07 삼성전자주식회사 반도체 칩의 접속 구조물 및 접속 구조물을 포함하는 반도체 패키지
US11824037B2 (en) * 2020-12-31 2023-11-21 International Business Machines Corporation Assembly of a chip to a substrate
US20230135057A1 (en) * 2021-10-28 2023-05-04 Skyworks Solutions, Inc. Dual sided molded package with varying interconnect pad sizes and uniform exposed solderable area
US20250015117A1 (en) * 2023-07-06 2025-01-09 Semiconductor Components Industries, Llc Pads for image sensors and related methods
US20250192099A1 (en) * 2023-12-06 2025-06-12 Qualcomm Incorporated Integrated circuit(ic) package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce die-substrate clearance

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