TWI697074B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI697074B
TWI697074B TW104112256A TW104112256A TWI697074B TW I697074 B TWI697074 B TW I697074B TW 104112256 A TW104112256 A TW 104112256A TW 104112256 A TW104112256 A TW 104112256A TW I697074 B TWI697074 B TW I697074B
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Taiwan
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metal layer
electrode
semiconductor device
semiconductor element
bump
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TW104112256A
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TW201541558A (zh
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脇山悟
中村卓矢
清水完
林利彦
城直樹
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日商新力股份有限公司
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Abstract

本發明提供半導體裝置及其形成方法，該等半導體裝置包含：一第一半導體元件，其具有一第一電極；一第二半導體元件，其具有一第二電極；一Sn基微焊料凸塊，其形成於該第二電極上；及一凹形凸塊墊，其包含相對於該微焊料凸塊之該第一電極，其中該第一電極經由該微焊料凸塊及該凹形凸塊墊而連接至該第二電極。

Description

半導體裝置及其製造方法 [相關申請案之交叉參考]
本申請案主張2014年4月23日申請之日本優先專利申請案JP 2014-088804及2014年12月18日申請之日本優先專利申請案JP 2014-256186之權利，該等案之各者之全文以引用的方式併入本文中。
本發明係關於一種半導體裝置及其製造方法，特定言之，本發明係關於一種半導體裝置(其中堆疊半導體元件之各自電極經由Sn基焊料而彼此電連接)及其製造方法。
在相關技術中，在經由使半導體元件堆疊而組態之一半導體裝置之製程中，使用Sn基(SnAg或其類似者)微焊料凸塊之一形成技術來連接堆疊半導體元件之各自電極。
圖1係示意性地繪示在相關技術中用於使半導體元件堆疊之Sn基微焊料凸塊之一形成技術的一視圖。
如圖1中所繪示，暴露一第一半導體元件1(即，一半導體元件)上之一Al墊2之一部分，且使Ni或其類似者形成為該部分上之一障壁金屬3。使一Sn基微焊料凸塊6形成於一第二半導體元件4(即，另一半導體元件)上，且使障壁金屬3及Sn基微焊料凸塊6經由甲酸還原而彼此擴散連接。
圖2係繪示各種金屬之各者之理論擴散距離(在攝氏200度處)對時間的一圖形，該等金屬可自Sn及障壁金屬獲得。如自圖2所明白，在經由上述甲酸還原而實現擴散連接之一情況中，鑑於一Sn基焊料之擴散率，需要形成具有約1微米之一厚度，具體言之，等於或大於3微米之一厚度之障壁金屬3。
然而，難以在半導體裝置之製程中之一晶圓程序中使具有約1微米之一厚度之障壁金屬3流體化。
在PTL 1所揭示之一情況中，採用Ti作為一Sn基焊料之一障壁金屬，且使用作為一晶粒接合技術之一濺鍍技術來形成具有約200奈米之一厚度之Ti，可在一晶圓程序中使Ti流體化。
[引用列表] [專利文獻] [PTL 1]
日本未審查專利申請公開案第2006-108604號
然而，在PTL 1所揭示之方法中，當半導體元件僅經由晶粒接合技術而彼此實體地連接且經受由申請人執行之一高溫暴露測試時，Sn基焊料與鈦之間之邊界之電阻歸因於合金生長、氧化或其類似者而增大。相應地，根據PTL 1中所揭示之方法，堆疊半導體元件之各自電極可彼此實體地連接；然而，堆疊半導體元件之各自電極可不彼此電連接。
鑑於此問題而提出本發明，且根據本發明，可電連接堆疊半導體元件之各自電極。
根據本發明之一實施例，提供一種半導體裝置，其包含：一第 一半導體元件，其具有一第一電極；一第二半導體元件，其具有一第二電極；一Sn基微焊料凸塊，其形成於該第二電極上；及一凹形凸塊墊，其形成於相對於該微焊料凸塊之該第一電極上，其中該第一電極經由該微焊料凸塊及該凹形凸塊墊而連接至該第二電極。
一第三金屬層(其擴散至該微凸塊且接近於該微凸塊)及一第二金屬層(其由一釩族金屬製成)可依序形成於該凸塊墊上。
該第一半導體元件上可具有複數個凸塊墊，該等凸塊墊之直徑彼此不同。
該等凸塊墊之直徑可取決於連接至該等凸塊墊之各自電極之使用。
該第二半導體元件之該微凸塊之直徑可對應於該對應第一半導體元件之該凸塊墊之直徑。
接近於該微凸塊之該第三金屬層、該第二金屬層、及一第一金屬層可依序形成於該凸塊墊上，該第一金屬層由用於該第二金屬層中之該釩族金屬之氮化物膜形成。
該第二金屬層可具有等於或大於30奈米之一平均厚度。
該第一金屬層可具有等於或大於10奈米之一平均厚度。
該第二金屬層可由Ta製成，且該第一金屬層由TaN製成。
該第三金屬層可由Cu、Co、Ni、Pd、Au或Pt製成。
可藉由提供自該第一半導體元件之表面至該第一半導體元件中之一貫穿電極之一開口部分而形成該凸塊墊。
可藉由提供自該第一半導體元件之表面至該第一半導體元件中之一金屬佈線之一開口部分而形成該凸塊墊。
該半導體裝置可為一堆疊CMOS影像感測器，其中等效於該第二半導體元件之一邏輯晶片CoW連接至等效於該第一半導體元件之一像素基板。
根據本發明之一第二實施例，提供一種製造一半導體裝置之方法，該半導體裝置包含與具有一第二電極之一第二半導體元件堆疊之具有一第一電極之一第一半導體元件，該方法包含：使一Sn基微焊料凸塊形成於該第二電極上；及使一凹形凸塊墊形成於相對於該微焊料凸塊之該第一電極上，其中該第一電極經由該微焊料凸塊及該凹形凸塊墊而連接至該第二電極。
在該凸塊墊之形成中，可使由一釩族金屬製成之一第二金屬層形成於該第一半導體元件(其係該等相對半導體元件之另一者)之電極上，該電極經由該微凸塊而連接至該第二半導體元件之電極，且可使擴散至該微凸塊之一第三金屬層形成於該第二金屬層上，且可使該微凸塊與該第三金屬層接觸，且該微凸塊及該第三金屬層可經受與一還原氛圍相關聯之一加熱處理，且藉此可使該第三金屬層及該微凸塊之表面上之氧化物膜還原，且歸因於該第三金屬層擴散至該微凸塊，該微凸塊及該第二金屬層可彼此接觸，且該第一半導體元件及該第二半導體元件之各自電極可彼此電連接。
在該凸塊墊之形成中，可使一鈍化層形成於該第一半導體元件之該第三金屬層上，且可經由蝕刻該鈍化層以使該第三金屬層暴露而提供一開口部分。
在該凸塊墊之形成中，在形成該第二金屬層之前，可使一第一金屬層形成於該第一半導體元件(其係該等相對半導體元件之另一者)之電極上，該電極經由該微凸塊而連接至該第二半導體元件，且該第一金屬層可由用於該第二金屬層中之該釩族金屬之氮化物膜形成。
在該凸塊墊之形成中，可藉由提供自該第一半導體元件之一表面至該第一半導體元件中之一貫穿電極之一開口部分而形成該凸塊墊。
在該凸塊墊之形成中，可藉由提供自該第一半導體元件之一表 面至該第一半導體元件中之一金屬佈線之一開口部分而形成該凸塊墊。
根據本發明之第一實施例，可獲得該半導體裝置，其中該第一半導體元件及該第二半導體元件之各自電極彼此電連接。
根據本發明之第二實施例，可製造該半導體裝置，其中該第一半導體元件及該第二半導體元件之各自電極彼此電連接。
2:Al墊
3:障壁金屬
4:第二半導體元件
6:Sn基微焊料凸塊
10:第一半導體元件
11:Al墊
12:SiO2層
13:第一金屬層
14:第二金屬層
15:第三金屬層
16:SiN層
21:開口部分/凸塊墊
21-1:凸塊墊
21-2:凸塊墊
23:第二半導體元件
24:Sn基微焊料凸塊
31:電力供應單元
32:信號處理單元
33:電力供應單元
34:信號處理單元
35:電力供應線
36:信號線
37:信號線
51:像素基板
52:邏輯晶片
71:WB墊
72:I/O
81:貫穿電極
91:金屬佈線/Cu佈線
S1:步驟
S2:步驟
S3:步驟
S4:步驟
S5:步驟
S6:步驟
S7:步驟
圖1係示意性地繪示使用Sn基微焊料凸塊來連接堆疊半導體元件之各自電極之一技術的一視圖。
圖2係繪示各種金屬之各者之理論擴散距離對時間的一圖形，該等金屬可自Sn及障壁金屬獲得。
圖3係繪示本發明應用於其之一半導體裝置之組態之一實例的一橫截面圖。
圖4係繪示圖3中所繪示之半導體裝置之一製造方法的一流程圖。
圖5A係繪示半導體裝置之製程的該半導體裝置之一橫截面圖。
圖5B係繪示半導體裝置之製程的該半導體裝置之一橫截面圖。
圖5C係繪示半導體裝置之製程的該半導體裝置之一橫截面圖。
圖5D係繪示半導體裝置之製程的該半導體裝置之一橫截面圖。
圖5E係繪示半導體裝置之製程的該半導體裝置之一橫截面圖。
圖6A係繪示半導體裝置之製程的該半導體裝置之一橫截面圖。
圖6B係繪示半導體裝置之製程的該半導體裝置之一橫截面圖。
圖6C係繪示半導體裝置之製程的該半導體裝置之一橫截面圖。
圖7係Sn與Ta之間之一相關圖。
圖8係繪示由攝氏125度處之一暴露測試所致之電阻值之變化的 一圖形。
圖9係繪示第一金屬層至第三金屬層之各者之材料及厚度之實例的一表。
圖10係繪示本發明應用於其之半導體裝置之一第一修改實例的一橫截面圖。
圖11係繪示本發明應用於其之半導體裝置之一第二修改實例的一橫截面圖。
圖12係繪示一凸塊之容量與一凸塊墊及一微凸塊之各者之直徑之間之一關係的一圖形。
圖13係繪示一電阻值與凸塊墊及微凸塊之各者之直徑之間之一關係的一圖形。
圖14係繪示半導體裝置之第二修改實例之一應用實例的一方塊圖。
圖15係繪示應用於一堆疊CMOS影像感測器之本發明之半導體裝置彼此堆疊之前之一狀態的一橫截面圖。
圖16係繪示應用於堆疊CMOS影像感測器之本發明之半導體裝置彼此堆疊之後之一狀態的一橫截面圖。
圖17係繪示其中一I/O連接至形成於一邏輯晶片上之一WB墊之一狀態的一橫截面圖。
圖18係繪示與凸塊墊之形成相關之一修改實例的一橫截面圖。
圖19係繪示與凸塊墊之形成相關之一修改實例的一橫截面圖。
圖20係繪示與凸塊墊之形成相關之一修改實例的一橫截面圖。
在下文中，將參考附圖來詳細地描述用於實現本發明之最佳形式(下文中指稱一實施例)。
<半導體裝置之組態之實例>
圖3係繪示一半導體裝置(其係本發明之一實施例)之組態之一實例的一橫截面圖。圖3僅繪示一第一半導體元件(其上未形成來自該第一半導體元件之一微凸塊)及一第二半導體元件，該第一半導體元件及該第二半導體元件彼此堆疊且經由一Sn基焊料而彼此電連接。
一Sn基焊料可為一SnAg基、SnBi基、SnCu基、SnIn基或SnAgCu基焊料或其類似者。
如圖3中所繪示，提供一Al墊11作為一第一半導體元件10上之一電極，Al墊11之一部分變為用於連接第一半導體元件10及第二半導體元件之一微凸塊之一開口部分21(參考圖5A至圖5E)，且一第一金屬層13、一第二金屬層14及一第三金屬層15依序形成於開口部分21上。SiO2層12形成於除開口部分21之外之部分上，且一SiN層16形成於SiO2層上。
充當一障壁金屬之第一金屬層13由用於第二金屬層14中之金屬之氮化物膜形成。例如，TaN用於圖3中所繪示之實例中。第一金屬層13具有等於或大於約10奈米之一平均厚度。相應地，特定言之，可在晶圓程序中形成第一金屬層13，藉此可降低顆粒風險。
由於提供第一金屬層(障壁金屬)13，所以可防止Al墊11與第二金屬層14之間之反應及Al墊11與一合金層(其可歸因於第二半導體元件之Sn基微焊料凸塊與第二金屬層14之間之反應而形成)之間之反應。相應地，可預期半導體裝置之可靠性及電特性之改良。可不提供第一金屬層13。
例如，Ta用於第二金屬層14中，且具有相對於Sn基焊料之一相關性及低擴散率。第二金屬層14具有等於或大於約30奈米之一平均厚度。相應地，特定言之，可在晶圓程序中形成第二金屬層14，藉此可降低顆粒風險。除Ta之外之釩族金屬(V、Nb及其類似者)可用於第二金屬層14中，該等金屬具有相對於Sn基焊料之低擴散率。
例如，Cu用於第三金屬層15中，Cu具有相對於Sn之高擴散率，且可使用一免清洗助焊劑、還原性氣體或其類似者來使第二金屬層14之氧化物表面膜還原。將第三金屬層15之一平均厚度設定為等於或大於約80奈米以防止第二金屬層14氧化。第三金屬層15中可使用除Cu之外之Co、Ni、Pd、Au、Pt或其類似者。
由於採用上述組態，所以即使使用極易氧化且不易還原之Ta、Ti或其類似者作為第二金屬層14之材料，仍易於使Sn基焊料及第二金屬層14彼此接觸(反應)。由於Ta用於第二金屬層14中，所以可改良半導體裝置之可靠性及電特性。
[製造設備製造半導體裝置之製造方法]
隨後，將參考圖4至圖6C來描述圖3中所繪示之半導體裝置之一製造方法。
圖4係繪示圖3中所繪示之半導體裝置之製造方法的一流程圖。圖5A至6C係繪示半導體裝置之製程的該半導體裝置之橫截面圖。
如圖5A中所繪示，在步驟S1中，使SiO2層12形成於其上提供Al墊11作為一電極之第一半導體元件10上。隨後，根據稍後將描述之開口部分21之位置及直徑，將用於保護除開口部分21之外之部分之光阻圖案(圖中未繪示)施加至SiO2層12之表面。另外，如圖5B中所繪示，藉由經由乾式蝕刻刮削SiO2層12而提供開口部分21，直至暴露Al墊11。
如圖5C中所繪示，在步驟S2中，經由一濺鍍方法而形成第一金屬層(TaN)13、第二金屬層(Ta)14及第三金屬層(Cu)15。隨後，如圖5D中所繪示，在步驟S3中，使用相同於第三金屬層15之材料之材料(在情況中為Cu)來使第三金屬層15經受一電鍍程序，且藉此增大第三金屬層15之厚度，且使用第三金屬層15來填塞開口部分21之凹腔。
如圖5E中所繪示，在步驟S4中，經由化學機械拋光(CMP)而移除 開口部分21外之第三金屬層15及第二金屬層14。在步驟S5中，使作為一鈍化層之一SiN層16形成於整個表面上，且將光阻圖案(圖中未繪示)施加至SiN層16之表面。另外，如圖6A中所繪示，經由乾式蝕刻而刮削SiN層16，直至暴露開口部分21之第三金屬層15。相應地，開口部分21具有一凹形結構，且藉此易於使開口部分21之位置與形成於第二半導體元件23上之一Sn基微焊料凸塊24之位置對準。在下文中，相對於Sn基微焊料凸塊24之開口部分21亦指稱一凸塊墊21。
如圖6B中所繪示，在步驟S6中，使第二半導體元件23上之Sn基微焊料凸塊24及凸塊墊21上之第三金屬層15彼此接觸，且使第二半導體元件23上之Sn基微焊料凸塊24及凸塊墊21上之第三金屬層15經受與一還原氛圍(諸如甲酸氛圍)相關聯之一加熱處理，且藉此使第三金屬層15及Sn基微焊料凸塊24之表面上之氧化物膜還原。其後，如圖6C中所繪示，在步驟S7中，使第三金屬層15擴散至Sn基焊料，且藉此使Sn基焊料及第二金屬層14彼此接觸(反應)，且在第二半導體元件23之電極與Al墊11(其係第一半導體元件10之電極)之間建立連接。至此，已描述製造方法。
[第二金屬層14與Sn基微焊料凸塊24之間之相關圖]
圖7係用於第二金屬層14中之Ta與含於Sn基微焊料凸塊24中之Sn之間之一相關圖。如圖7中所繪示，當在攝氏250度之一溫度處建立凸塊連接時，可推斷：在Ta與Sn之間之邊界處形成Ta3Sn之一合金或Ta2Sn3之一合金。
[開耳芬電阻對高溫暴露時間之測量結果]
圖8係繪示TaN、Ta及Cu分別用於第一金屬層13、第二金屬層14及第三金屬層15中且第二金屬層14連接至Sn基微焊料凸塊24時之開耳芬電阻對攝氏125度處之高溫暴露時間之測量結果的一圖形。如圖8中所繪示，即使在已逝去168小時之後，電阻值仍無改變。相應地，應 瞭解，即使在已逝去時間之後，仍維持第一半導體元件10及第二半導體元件23之各自電極之間之電連接。
[關於第一金屬層13、第二金屬層14及第三金屬層15之材料及厚度]
隨後，圖9係繪示改變第二金屬層14之厚度及第三金屬層15之材料及厚度時之第一實例至第五實例及一比較實例(PTL 1中所揭示之組態)之評估的一表。
在第一實例中，TaN、Ta及Cu分別用於具有15奈米之一厚度之第一金屬層13、具有100奈米之一厚度之第二金屬層14、及具有80奈米之一厚度之第三金屬層15中。在第二實例中，TaN、Ta及Co分別用於具有15奈米之一厚度之第一金屬層13、具有100奈米之一厚度之第二金屬層14、及具有110奈米之一厚度之第三金屬層15中。在第三實例中，TaN、Ta及Cu分別用於具有15奈米之一厚度之第一金屬層13、具有100奈米之一厚度之第二金屬層14、及具有360奈米之一厚度之第三金屬層15中。在第四實例中，TaN、Ta及Cu分別用於具有15奈米之一厚度之第一金屬層13、具有50奈米之一厚度之第二金屬層14、及具有80奈米之一厚度之第三金屬層15中。在第五實例中，TaN、Ta及Cu分別用於具有15奈米之一厚度之第一金屬層13、具有30奈米之一厚度之第二金屬層14、及具有80奈米之一厚度之第三金屬層15中。在第一實例至第五實例之任何者中，金屬層之間之連接性及高溫暴露測試之結果不存在問題，且在第一半導體元件10及第二半導體元件23之各自電極之間建立實體連接及電連接。在比較實例中，在電極之間建立實體連接；然而，電阻值隨時間流逝而增大，且無法維持電極之間之電連接。
<半導體裝置之第一修改實例>
圖10係繪示根據本發明之實施例之半導體裝置之一第一修改實 例的一橫截面圖。該第一修改實例具有一組態，其中自圖3中所繪示之組態省略第一金屬層13。相應地，可減少程序節拍時間及成本。
<半導體裝置之第二修改實例>
隨後，圖11係繪示根據本發明之實施例之半導體裝置之一第二修改實例的一橫截面圖。
在第二修改實例之組態中，根據連接至凸塊墊21之一電極(電線)之使用而改變第一半導體元件10上之凸塊墊21之直徑。將兩個凸塊墊21提供於第一半導體元件10上，且形成具有大於一凸塊墊21-1之直徑之一直徑的一凸塊墊21-2。
易於藉由改變在上述製程之步驟S1中施加至SiO2層12之光阻圖案及在上述製程之步驟S5中施加至SiN層16之光阻圖案而改變相同基板(在此情況中為第一半導體元件10)上之複數個凸塊墊21之直徑。
相比而言，第二半導體元件之Sn基微焊料凸塊24之直徑經改變以對應於對應凸塊墊21之直徑。
[凸塊之容量變化對凸塊墊21及Sn基微焊料凸塊24之各者之直徑變化]
圖12係繪示一凸塊之容量變化對凸塊墊21(開口部分)及Sn基微焊料凸塊之各者之直徑變化的一圖形。
如圖12中所繪示，凸塊墊21及Sn基微焊料凸塊24之各者之直徑較小時之凸塊之容量小於凸塊墊21及Sn基微焊料凸塊24之各者之直徑較大時之凸塊之容量。相應地，當經由具有一小直徑之凸塊墊21及具有一小直徑之Sn基微焊料凸塊24而建立一信號線之連接時，可預期電信信號之信號特性之改良。另外，易於在此時執行選路。
[電阻值之變化對凸塊墊21及Sn基微焊料凸塊24之各者之直徑變化]
圖13係繪示電阻值之變化對凸塊墊21(開口部分)及Sn基微焊料 凸塊24之各者之直徑變化的一圖形。
如圖13中所繪示，一電阻值隨著凸塊墊21及Sn基微焊料凸塊24之各者之直徑逐漸增大而逐漸減小。相應地，當經由具有一大直徑之凸塊墊21及具有一大直徑之Sn基微焊料凸塊24而建立一信號線之連接時，可防止出現一電力供應相關之缺陷，諸如IR壓降。
[半導體裝置之第二修改實例之應用實例]
隨後，圖14繪示圖11中所繪示之第二組態實例之一應用實例。
在此應用實例中，一電力供應線35連接第一半導體元件10之一電力供應單元31及第二半導體元件23之一電力供應單元33，且經由具有一大直徑之凸塊墊21-2及具有一大直徑之Sn基微焊料凸塊24而建立電力供應線35之連接。信號線36及37連接第一半導體元件10之一信號處理單元32及第二半導體元件23之一信號處理單元34，且經由具有一小直徑之凸塊墊21-1及具有一小直徑之Sn基微焊料凸塊24而建立信號線36及37之各者之連接。
使用圖14中所繪示之應用實例之組態，可改良第一半導體元件10與第二半導體元件23之間之電信信號之信號特性，且可防止出現一電力供應相關之缺陷，諸如IR壓降。
[半導體裝置之應用實例]
隨後，將描述一組態實例，其中將本發明之半導體裝置應用於一堆疊CMOS影像感測器(下文中指稱一堆疊CIS)。
圖15繪示應用於一堆疊CIS之本發明之半導體裝置彼此堆疊之前之一狀態，且圖16繪示半導體裝置彼此堆疊之後之一狀態。
即，在堆疊CIS之組態中，經由晶圓上晶片(CoW)連接而使用於處理自一像素基板51輸出之像素信號之一邏輯晶片52堆疊於像素基板51上，像素基板51具有用於執行光電轉換之一像素單元。
像素基板51等效於第一半導體元件10，且連接至邏輯晶片52之 Sn基微焊料凸塊24之凸塊墊21形成於像素基板51之一表面上，光入射於該表面上。相比而言，邏輯晶片52等效於第二半導體元件23，且Sn基微焊料凸塊24形成於邏輯晶片52之一表面上，該表面連接至像素基板51。
當依使得凸塊墊21及Sn基微焊料凸塊24彼此接觸之一方式使凸塊墊21及Sn基微焊料凸塊24彼此堆疊時，像素基板51及邏輯晶片52經受一加熱處理，且藉此使像素基板51及邏輯晶片52彼此電連接。如圖17中所繪示，一WB墊71形成於邏輯晶片52之表面(該表面連接至像素基板51)之相對側上之另一表面上，且一I/O 72連接至WB墊71。
如圖17中所繪示，由於將本發明之半導體裝置應用於堆疊CMOS影像感測器，所以可防止出現損壞，諸如像素單元之灰塵污染，其可出現於一微墊亦形成於像素基板51上時。另外，可在使邏輯晶片52及像素基板51彼此堆疊時實現一低堆疊高度，且可防止CF清洗時之變動。
[與凸塊墊之形成相關之修改實例]
隨後，將描述與凸塊墊之形成相關之一修改實例。
在圖18所繪示之修改實例中，當一貫穿電極81形成於像素基板51中時，開口部分21提供於貫穿電極81之位置處，且一貫穿電極81用作為對應於邏輯晶片52之Sn基微焊料凸塊24之凸塊墊。由於貫穿電極81用作為凸塊墊，所以可省略第一金屬層13至第三金屬層15之形成。
在圖19及圖20所繪示之修改實例之各者中，省略像素基板51(第一半導體元件10)及Al墊11，開口部分21經形成以到達像素基板51中之一金屬佈線(Cu佈線)91，且像素基板中之金屬佈線91用作為對應於邏輯晶片52之Sn基微焊料凸塊24之凸塊墊。
由於省略Al墊11且像素基板51中之金屬佈線91用作為凸塊墊，所以可在一客製程序中實現清洗之更小變動，且可達成晶片縮小。另 外，可實現邏輯晶片52之一低堆疊高度。
本發明之半導體裝置可應用於除堆疊CIS(其中堆疊半導體裝置之各自電極彼此連接)之外之各種類型之電子裝置。
本發明不限於上述實施例，而是可對該實施例作出各種修改，只要該等修改不背離本發明之精神。
本發明可具有以下組態。
(1)一種半導體裝置，其經由使半導體元件堆疊而組態，且其中該等相對半導體元件之各自電極彼此電連接，其中一Sn基微焊料凸塊形成於一第二半導體元件之一電極上，該第二半導體元件係該等相對半導體元件之一者，且其中相對於該Sn基微焊料凸塊之一凹形凸塊墊形成於一第一半導體元件之一電極上，該第一半導體元件係該等相對半導體元件之另一者，該電極經由該Sn基微焊料凸塊而連接至該第二半導體元件之該電極。
(2)在如(1)之半導體裝置中，擴散至該Sn基微焊料凸塊且接近於該Sn基微焊料凸塊之一第三金屬層、及由一釩族金屬製成之一第二金屬層依序形成於該凸塊墊上。
(3)在如(1)或(2)之半導體裝置中，該第一半導體元件上具有複數個凸塊墊，該等凸塊墊之直徑彼此不同。
(4)在如(1)至(3)中任一項之半導體裝置中，該等凸塊墊之直徑因連接至該等凸塊墊之各自電極之使用而不同。
(5)在如(1)至(4)中任一項之半導體裝置中，該第二半導體元件之該Sn基微焊料凸塊之直徑對應於該對應第一半導體元件之該凸塊墊之直徑。
(6)在如(1)至(5)中任一項之半導體裝置中，接近於該Sn基微焊料凸塊之該第三金屬層、該第二金屬層、及一第一金屬層依序形成於該凸塊墊上，該第一金屬層由用於該第二金屬層中之該釩族金屬之氮 化物膜形成。
(7)在如(1)至(6)中任一項之半導體裝置中，該第二金屬層具有等於或大於30奈米之一平均厚度。
(8)在如(1)至(6)中任一項之半導體裝置中，該第一金屬層具有等於或大於10奈米之一平均厚度。
(9)在如(1)至(6)中任一項之半導體裝置中，該第二金屬層由Ta製成，且該第一金屬層由TaN製成。
(10)在如(1)至(6)中任一項之半導體裝置中，該第三金屬層由Cu、Co、Ni、Pd、Au或Pt製成。
(11)在如(1)之半導體裝置中，藉由提供自該第一半導體元件之表面至該第一半導體元件中之一貫穿電極之一開口部分而形成該凸塊墊。
(12)在如(1)之半導體裝置中，藉由提供自該第一半導體元件之表面至該第一半導體元件中之一金屬佈線之一開口部分而形成該凸塊墊。
(13)在如(1)之半導體裝置中，該半導體裝置係一堆疊CMOS影像感測器，其中等效於該第二半導體元件之一邏輯晶片CoW連接至等效於該第一半導體元件之一像素基板。
(14)一種一製造設備製造一半導體裝置之製造方法，該半導體裝置經由使半導體元件堆疊而組態且其中該等相對半導體元件之各自電極彼此電連接，該方法包含：一微凸塊形成步驟，其使一Sn基微焊料凸塊形成於一第二半導體元件之一電極上，該第二半導體元件係該等相對半導體元件之一者；及一凸塊墊形成步驟，其使相對於該Sn基微焊料凸塊之一凹形凸塊墊形成於一第一半導體元件之一電極上，該第一半導體元件係該等相對半導體元件之另一者，該電極經由該Sn基微焊料凸塊而連接至該第二半導體元件之該電極。
(15)在如(14)之製造方法中，在該凸塊墊形成步驟中，使由一釩族金屬製成之一第二金屬層形成於該第一半導體元件之該電極上，該第一半導體元件係該等相對半導體元件之另一者，該電極經由該Sn基微焊料凸塊而連接至該第二半導體元件之該電極，且使擴散至該Sn基微焊料凸塊之一第三金屬層形成於該第二金屬層上，且使該Sn基微焊料凸塊與該第三金屬層接觸，且該Sn基微焊料凸塊及該第三金屬層經受與一還原氛圍相關聯之一加熱處理，且藉此使該第三金屬層及該Sn基微焊料凸塊之表面上之氧化物膜還原，且歸因於該第三金屬層擴散至該Sn基微焊料凸塊，使該Sn基微焊料凸塊及該第二金屬層彼此接觸，且使該第一半導體元件及該第二半導體元件之各自電極彼此電連接。
(16)在如(15)之製造方法中，在該凸塊墊形成步驟中，使一鈍化層形成於該第一半導體元件之該第三金屬層上，且經由蝕刻該鈍化層以使該第三金屬層暴露而提供一開口部分。
(17)在如(15)之製造方法中，在該凸塊墊形成步驟中，在形成該第二金屬層之前，使一第一金屬層形成於該第一半導體元件之該電極上，該第一半導體元件係該等相對半導體元件之另一者，該電極經由該Sn基微焊料凸塊而連接至該第二半導體元件，且該第一金屬層由用於該第二金屬層中之該釩族金屬之氮化物膜形成。
(18)在如(14)之製造方法中，在該凸塊墊形成步驟中，藉由提供自該第一半導體元件之一表面至該第一半導體元件中之一貫穿電極之一開口部分而形成該凸塊墊。
(19)在如(14)之製造方法中，在該凸塊墊形成步驟中，藉由提供自該第一半導體元件之一表面至該第一半導體元件中之一金屬佈線之一開口部分而形成該凸塊墊。
(20)一種半導體裝置，其包含：一第一半導體元件，其具有一 第一電極；一第二半導體元件，其具有一第二電極；一Sn基微焊料凸塊，其形成於該第二電極上；及一凹形凸塊墊，其位於相對於該微焊料凸塊之該第一電極上，其中該第一電極經由該微焊料凸塊及該凹形凸塊墊而連接至該第二電極。
(21)如(20)之半導體裝置，其進一步包含依序形成於該凹形凸塊墊上之一第二金屬層及一第三金屬層，其中該第三金屬層擴散至該微焊料凸塊，且該第二金屬層由一釩族金屬製成。
(22)如(20)至(21)中任一項之半導體裝置，其中該第一半導體元件上具有複數個凹形凸塊墊，該等凹形凸塊墊之直徑彼此不同。
(23)如(20)至(22)中任一項之半導體裝置，其中該等凹形凸塊墊之直徑因連接至該等凹形凸塊墊之各自電極之使用而不同。
(24)如(20)至(23)中任一項之半導體裝置，其中該微焊料凸塊之一直徑對應於該凹形凸塊墊之一直徑。
(25)如(20)至(21)中任一項之半導體裝置，其進一步包含與該第二金屬層及該第三金屬層一起依序形成於該凹形凸塊墊上之一第一金屬層，其中該第三金屬層最接近於該微焊料凸塊，且其中該第一金屬層係用於該第二金屬層中之該釩族金屬之氮化物膜。
(26)如(20)至(25)中任一項之半導體裝置，其中該第二金屬層具有等於或大於30奈米之一平均厚度。
(27)如(20)至(26)中任一項之半導體裝置，其中該第一金屬層具有等於或大於10奈米之一平均厚度。
(28)如(20)至(27)中任一項之半導體裝置，其中該第二金屬層係Ta，且該第一金屬層係TaN。
(29)如(20)至(28)中任一項之半導體裝置，其中該第三金屬層係Cu、Co、Ni、Pd、Au及Pt之一者。
(30)如(20)至(29)中任一項之半導體裝置，其中該第一電極係一 貫穿電極。
(31)如(20)至(30)中任一項之半導體裝置，其進一步包含自該第一半導體元件之一表面延伸至該第一半導體元件中之一金屬佈線之一開口部分，其中該開口部分形成該凹形凸塊墊。
(32)如(20)至(31)中任一項之半導體裝置，其中該半導體裝置係一堆疊CMOS影像感測器，其包含等效於該第二半導體元件之一邏輯晶片，該邏輯晶片CoW連接至等效於該第一半導體元件之一像素基板。
(33)一種一半導體裝置之製造方法，該半導體裝置包含與具有一第二電極之一第二半導體元件堆疊之具有一第一電極之一第一半導體元件，該方法包含：使一Sn基微焊料凸塊形成於該第二電極上；及使一凹形凸塊墊形成於相對於該微焊料凸塊之該第一電極上，其中該第一電極經由該微焊料凸塊及該凹形凸塊墊而連接至該第二電極。
(34)如(33)之製造方法，其中在該凹形凸塊墊之形成期間，使由一釩族金屬製成之一第二金屬層形成於該第一電極上且使一第三金屬層形成於該第二金屬層上，其中使該第三金屬層擴散至該微焊料凸塊，且該微焊料凸塊及該第三金屬層經受與一還原氛圍相關聯之一加熱處理，且藉此使該第三金屬層及該微焊料凸塊之表面上之氧化物膜還原，且歸因於該第三金屬層擴散至該微焊料凸塊，使該微焊料凸塊及該第二金屬層彼此接觸，且使該第一電極及該第二電極彼此電連接。
(35)如(33)至(34)中任一項之製造方法，其中在該凹形凸塊墊之形成期間，使一鈍化層形成於該第一半導體元件之該第三金屬層上，且經由蝕刻該鈍化層以暴露該第三金屬層而形成一開口部分。
(36)如(33)至(35)中任一項之製造方法，其中在該凹形凸塊墊之形成期間，在形成該第二金屬層之前，使一第一金屬層形成於該第一 電極上，且其中該第一電極經由該微焊料凸塊而連接至該第二半導體元件，且該第一金屬層係用於該第二金屬層中之該釩族金屬之氮化物膜。
(37)如(33)至(36)中任一項之製造方法，其中該第一電極係一貫穿電極。
(38)如(33)至(37)中任一項之製造方法，其中在該凹形凸塊墊之形成期間，藉由提供自該第一半導體元件之一表面至該第一半導體元件中之一金屬佈線之一開口部分而形成該凹形凸塊墊。
(39)如(33)至(38)中任一項之製造方法，其中該半導體裝置係一堆疊CMOS影像感測器，其包含等效於該第二半導體元件之一邏輯晶片及等效於該第一半導體元件之一像素基板，且其中當該凹形凸塊墊及該微焊料凸塊接觸時，該邏輯晶片及該像素基板經受一加熱處理。
熟習技術者應瞭解，可根據設計要求及其他因數而進行各種修改、組合、子組合及變更，只要該等修改、組合、子組合及變更係在附屬申請專利範圍或其等效物之範疇內。
10‧‧‧第一半導體元件
11‧‧‧Al墊
12‧‧‧SiO2層
13‧‧‧第一金屬層
14‧‧‧第二金屬層
15‧‧‧第三金屬層
16‧‧‧SiN層

Claims (27)

  1. 一種半導體裝置，其包括：一第一半導體元件，其具有一第一電極；一第二半導體元件，其具有一第二電極；一Sn基微焊料凸塊，其形成於該第二電極上；一凹形凸塊墊，其形成於相對於該微焊料凸塊之該第一電極上；一第二金屬層及一第三金屬層，其等依序形成於該凹形凸塊墊上；及一第一金屬層，其與該第二金屬層及該第三金屬層一起依序形成於該凹形凸塊墊上；其中該第一電極經由該微焊料凸塊及該凹形凸塊墊而連接至該第二電極；該第三金屬層擴散至該微焊料凸塊；該第二金屬層由一釩族金屬製成；該第三金屬層最接近該微焊料凸塊；且該第一金屬層係於該第二金屬層中採用之該釩族金屬之一氮化物膜。
  2. 如請求項1之半導體裝置，其中該第二金屬層具有等於或大於30奈米之一平均厚度。
  3. 如請求項1之半導體裝置，其中該第一金屬層具有等於或大於10奈米之一平均厚度。
  4. 如請求項1之半導體裝置，其中該第二金屬層係Ta，且該第一金屬層係TaN。
  5. 如請求項1之半導體裝置，其中該第三金屬層係Cu、Co、Ni、 Pd、Au及Pt之一者。
  6. 一種製造一半導體裝置之方法，該半導體裝置包含與具有一第二電極之一第二半導體元件堆疊之具有一第一電極之一第一半導體元件，該方法包括：使一Sn基微焊料凸塊形成於該第二電極上；及使一凹形凸塊墊形成於相對於該微焊料凸塊之該第一電極上，其中該第一電極經由該微焊料凸塊及該凹形凸塊墊而連接至該第二電極，其中在形成該凹形凸塊墊期間，由一釩族金屬製成之一第二金屬層形成於該第一電極上且一第三金屬層形成於該第二金屬層上，其中該第三金屬層擴散至該微焊料凸塊，且該微焊料凸塊及該第三金屬層經受與一還原氛圍(reducing atmosphere)相關聯之一加熱處理，且藉此使該第三金屬層及該微焊料凸塊之表面上之一氧化物膜還原，且歸因於該第三金屬層擴散至該微焊料凸塊，使該微焊料凸塊及該第二金屬層彼此接觸，且該第一電極及該第二電極彼此電性連接。
  7. 如請求項6之製造方法，其中在形成該凹形凸塊墊期間，使一鈍化層形成於該第一半導體元件之該第三金屬層上，且經由蝕刻該鈍化層以暴露該第三金屬層而形成一開口部分。
  8. 如請求項6之製造方法，其中在形成該凹形凸塊墊期間，在形成該第二金屬層之前，使一第一金屬層形成於該第一電極上，且其中該第一電極經由該微焊料凸塊而連接至該第二半導體元件，且該第一金屬層係用於該第二金屬層中之該釩族金屬之一氮化物膜。
  9. 一種半導體裝置，其包括：一第一半導體元件，其具有一第一電極、設置於該第一電極之上的一第一金屬層、設置於該第一金屬層之上的一第二金屬層、及一鈍化層；一第二半導體元件，其具有一第二電極；及一微凸塊，其設置於該第一半導體元件與該第二半導體元件之間；其中該鈍化層係：於俯視時，覆蓋該第一金屬層及該第二金屬層之各者之至少一部份。
  10. 如請求項9之半導體裝置，其中該微凸塊包含Sn。
  11. 如請求項9或10之半導體裝置，其中該微凸塊與該鈍化層之截面相接。
  12. 如請求項9或10之半導體裝置，其中該第二金屬層包含一釩族金屬。
  13. 如請求項12之半導體裝置，其中該第一金屬層包含於該第二金屬層採用之該釩族金屬之氮化物膜。
  14. 如請求項13之半導體裝置，其中該第二金屬層係Ta，該第一金屬層係TaN。
  15. 如請求項9或10之半導體裝置，其中該第二金屬層之平均厚度係30奈米以上。
  16. 如請求項9或10之半導體裝置，其中該第一金屬層之平均厚度係10奈米以上。
  17. 如請求項9或10之半導體裝置，其中於該第一半導體元件之該第一電極，形成與該微凸塊對向之一凹形之凸塊墊，且該凸塊墊之表面被該第一金屬層及該第二金屬層被覆。
  18. 如請求項17之半導體裝置，其中在該第一半導體元件上形成有 直徑不同的複數個該凸塊墊。
  19. 如請求項17之半導體裝置，其中該凸塊墊之直徑對應於連接之該第一電極之用途而不同。
  20. 如請求項17之半導體裝置，其中該第二半導體元件之該微凸塊之直徑與對應之該第一半導體元件之該凸塊墊之直徑相對應。
  21. 如請求項9之半導體裝置，其係一堆疊CMOS影像感測器，其中等效於該第二半導體元件之一邏輯晶片CoW連接至等效於該第一半導體元件之一像素基板。
  22. 一種半導體裝置之製造方法，其包括以下步驟：形成具有一第一電極、設置於該第一電極之上的一第一金屬層、設置於該第一金屬層之上的一第二金屬層及一鈍化層的一第一半導體元件，該鈍化層係：於形成該第一金屬層及該第二金屬層後，以於俯視時被覆該第一金屬層及該第二金屬層之各者之至少一部份方式而形成；及藉由一微凸塊連接該第一半導體元件與具有一第二電極之一第二半導體元件。
  23. 如請求項22之半導體裝置之製造方法，其中該微凸塊包含Sn。
  24. 如請求項22或23之半導體裝置之製造方法，其中該微凸塊與該鈍化層之截面相接。
  25. 如請求項24之半導體裝置之製造方法，其更包括以下步驟：於該第二半導體元件之該第二電極形成該微凸塊，及於該第一半導體元件之該第一電極形成與該微凸塊對向之一凹形之凸塊墊。
  26. 如請求項25之半導體裝置之製造方法，其中形成該凸塊墊之步驟中，包括以下步驟： 於該第一半導體元件之該第一電極上，形成該第一金屬層，該第一金屬層包含於該第二金屬層採用之一釩族金屬之一氮化物膜，於該第一半導體元件之該第一金屬層上，形成包含該釩族金屬之該第二金屬層，於該第二金屬層上，形成擴散至該微凸塊之一第三金屬層，及使該微凸塊接觸於該第三金屬層，且藉由與一還原氛圍相關聯之一加熱處理，將該第三金屬層及該微凸塊之表面之一氧化物膜還原，使該第三金屬層擴散至該微凸塊，藉而使該第二金屬層與該微凸塊接觸，而將該第一半導體元件之該第一電極與該第二半導體元件之該第二電極電性連接。
  27. 如請求項26之半導體裝置之製造方法，其中形成該凸塊墊之步驟中，更包括以下步驟：於該第一半導體元件之該第三金屬層之上形成該鈍化層，及藉由蝕刻該鈍化層而設置暴露該第三金屬層之開口部分。
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