JP2015216350A - 半導体装置、および製造方法 - Google Patents

半導体装置、および製造方法 Download PDF

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Publication number
JP2015216350A
JP2015216350A JP2014256186A JP2014256186A JP2015216350A JP 2015216350 A JP2015216350 A JP 2015216350A JP 2014256186 A JP2014256186 A JP 2014256186A JP 2014256186 A JP2014256186 A JP 2014256186A JP 2015216350 A JP2015216350 A JP 2015216350A
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Japan
Prior art keywords
metal layer
semiconductor element
semiconductor
bump
semiconductor device
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
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JP2014256186A
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English (en)
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JP6424610B2 (ja
JP2015216350A5 (ja
Inventor
悟 脇山
Satoru Wakiyama
悟 脇山
直樹 城
Naoki Jo
直樹 城
完 清水
Kan Shimizu
完 清水
卓矢 中村
Takuya Nakamura
卓矢 中村
利彦 林
Toshihiko Hayashi
利彦 林
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Sony Corp
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Sony Corp
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Priority to JP2014256186A priority Critical patent/JP6424610B2/ja
Application filed by Sony Corp filed Critical Sony Corp
Priority to CN201811352193.1A priority patent/CN109637992B/zh
Priority to KR1020227006069A priority patent/KR20220030314A/ko
Priority to US15/118,575 priority patent/US10600838B2/en
Priority to KR1020167021519A priority patent/KR102370046B1/ko
Priority to KR1020237005687A priority patent/KR102619737B1/ko
Priority to PCT/JP2015/002071 priority patent/WO2015162872A1/en
Priority to CN201580006909.0A priority patent/CN105981160B/zh
Priority to TW104112256A priority patent/TWI697074B/zh
Publication of JP2015216350A publication Critical patent/JP2015216350A/ja
Publication of JP2015216350A5 publication Critical patent/JP2015216350A5/ja
Application granted granted Critical
Publication of JP6424610B2 publication Critical patent/JP6424610B2/ja
Priority to US16/503,062 priority patent/US11476291B2/en
Priority to US17/939,796 priority patent/US20230005979A1/en
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Abstract

【課題】 積層する半導体素子の電極どうしを接続するに際して、一方の半導体素子にSn系はんだのマイクロバンプを形成し、他方の半導体素子に形成するバリアメタルとしてウエハプロセスにて流動可能なｎｍオーダのメタルを採用する。
【解決手段】 本開示の半導体装置は、対向する半導体素子の一方である第２半導体素子の電極には、Sn系はんだからなるマイクロバンプが形成され、前記マイクロバンプを介して前記第２半導体素子の電極と接続されている、前記対向する半導体素子の他方である第１半導体素子の電極には、前記マイクロバンプに対向する凹形状のバンプパッドが形成されている。本開示は、半導体素子が積層されて構成される半導体装置に適用できる。
【選択図】 図３

Description

本開示は、半導体装置、および製造方法に関し、特に、積層する半導体素子の電極どうしをSn系はんだにより電気的に接続するようにした半導体装置、および製造方法に関する。
従来、半導体素子を積層して構成する半導体装置の製造工程において、積層する半導体素子の電極どうしを接続する場合には、Sn系はんだ（SnAgなど）のマイクロバンプを形成する手法が用いられている。
図１は、半導体素子どうしを積層するに際して従来用いられているSn系はんだから成るマイクロバンプを形成する手法の概要を示している。
同図に示されるように、一方の第１半導体素子１側には、Al PAD２の位置が開口され、そこにバリアメタル３としてNiなどが形成される。他方の第２半導体素子４側には、Sn系はんだから成るマイクロバンプ６が形成され、ギ酸還元によってバリアメタル３とSn系はんだ６が拡散接続される。
図２は、Snとバリアメタルとされ得る各種のメタルとの時間に対する理論拡散距離（２００℃の場合）を示している。同図から明らかなように、上述したギ酸還元による拡散接続を実行する場合、Sn系はんだとの拡散性を考慮すると、バリアメタル３の厚みをｕｍ（マイクロメートル）オーダで、具体的には３ｕｍ以上で形成する必要が生じる。
ただし、半導体装置の製造工程におけるウエハプロセスでは、バリアメタル３をｕｍオーダで流動させることは困難である。
なお、特許文献１には、ダイボンド技術として、Sn系はんだのバリアメタルとしてTiを採用し、スッパタ技法を用いることによりウエハプロセスにて流動させることができる２００ｎｍ（ナノメートル）程度のTiを形成することが記載されている。
特開２００６−１０８６０４号公報
しかしながら、特許文献１に記載の方法は、ダイボンド技術として半導体素子を物理的に接続しているに過ぎず、本出願人側で高温放置試験を実施した結果、Sn系はんだとTiとの境界には合金成長や酸化などによる高抵抗化が生じてしまうことが分かった。よって、特許文献１の方法では、積層する半導体素子それぞれの電極どうしを物理的に接続できるものの電気的には接続できないことが分かっている。
本開示はこのような状況に鑑みてなされたものであり、積層する半導体素子の電極どうしを電気的に接続できるようにするものである。
本開示の第１の側面によれば、半導体素子が積層されて構成され、対向する前記半導体素子の電極どうしが電気的に接続されている半導体装置において、前記対向する半導体素子の一方である第２半導体素子の電極には、Sn系はんだからなるマイクロバンプが形成され、前記マイクロバンプを介して前記第２半導体素子の電極と接続されている、前記対向する半導体素子の他方である第１半導体素子の電極には、前記マイクロバンプに対向する凹形状のバンプパッドが形成されている。
前記バンプパッドには、前記マイクロバンプ側から順に、前記マイクロバンプに拡散された第３金属層、およびバナジウム族に属する金属からなる第２金属層が形成されているようにすることができる。
前記第１半導体素子上には、径が異なる複数の前記バンプパッドが設けられているようにすることができる。
前記バンプパッドの径は、接続する前記電極の用途に応じて異なるようにすることができる。
前記第２半導体素子の前記マイクロバンプの径は、対応する前記第１半導体素子の前記バンプパッドの径に対応しているようにすることができる。
前記バンプパッドには、前記マイクロバンプ側から順に、前記第３金属層、前記第２金属層、および前記第２金属層に採用されたバナジウム族に属する前記金属の窒化膜からなる第１金属層が形成されているようにすることができる。
前記第２金属層の平均厚みは３０ｎｍ以上とすることができる。
前記第１金属層の平均厚みは１０ｎｍ以上とすることができる。
前記第２金属層はTa、前記第１金属層はTaNとすることができる。
前記第３金属層はCu，Co，Ni，Pd，AuまたはPtとすることができる。
前記バンプパッドは、前記第１半導体素子の表面から前記第１半導体素子内の貫通電極まで設けられた開口部により形成することができる。
前記バンプパッドは、前記第１半導体素子の表面から前記第１半導体素子内の金属配線まで設けられた開口部により形成することができる。
前記半導体装置は、前記第１半導体素子に相当する画素基板に、前記第２半導体素子に相当するロジックチップがCoW接続されている積層型CMOSイメージセンサとすることができる。
本開示の第２の側面である製造方法は、半導体素子が積層されて構成され、対向する前記半導体素子の電極どうしが電気的に接続されている半導体装置を製造する製造装置の製造方法において、前記製造装置による、前記対向する半導体素子の一方である第２半導体素子の電極にSn系はんだからなるマイクロバンプを形成するマイクロバンプ形成ステップと、前記マイクロバンプを介して前記第２半導体素子の電極と接続される、前記対向する半導体素子の他方である第１半導体素子の電極に前記マイクロバンプに対向する凹形状のバンプパッドを形成するバンプパッド形成ステップとを含む。
前記バンプパッド形成ステップは、前記マイクロバンプを介して前記第２半導体素子の電極と接続される、前記対向する半導体素子の他方である第１半導体素子の電極上に、バナジウム族に属する金属からなる第２金属層を形成し、前記第２金属層上に、前記マイクロバンプに拡散される第３金属層を形成し、第３金属層に前記マイクロバンプを接触させ、還元雰囲気化による加熱処理により、前記第３金属層と前記マイクロバンプの表面の酸化膜を還元し、前記第３金属層を前記マイクロバンプに拡散させることにより前記マイクロバンプと前記第２金属層を接触させて、前記第１半導体素子と前記第２半導体素子の電極どうしを電気的に接続することができる。
前記バンプパッド形成ステップは、さらに、前記第１半導体素子の前記第３金属層の上にパシベーション層を形成し、前記パシベーション層をエッチングすることにより、前記第３金属層が露出する開口部を設けることができる。
前記バンプパッド形成ステップは、さらに、前記第２金属層を形成する前に、前記マイクロバンプを介して前記第２半導体素子の電極と接続される、前記対向する半導体素子の他方である第１半導体素子の電極上に、前記第２金属層に採用されるバナジウム族に属する前記金属の窒化膜からなる第１金属層を形成することができる。
前記バンプパッド形成ステップは、前記第１半導体素子の表面から前記第１半導体素子内の貫通電極まで開口部を設けることにより前記バンプパッドを形成することができる。
前記バンプパッド形成ステップは、前記第１半導体素子の表面から前記第１半導体素子内の金属配線まで開口部を設けることにより前記バンプパッドを形成することができる。
本開示の第１の側面によれば、第１半導体素子と第２半導体素子の電極どうしが電気的に接続された半導体装置を得ることができる。
本開示の第２の側面によれば、第１半導体素子と第２半導体素子の電極どうしが電気的に接続された半導体装置を製造できる。
積層する半導体素子の電極どうしの接続にSn系はんだからなるマイクロバンプを用いる手法の概要を説明するための図である。 Snとバリアメタルとされ得る各種のメタルとの時間に対する理論拡散距離を示す図である。 本開示を適用した半導体装置の構成例を示す断面図である。 図３の半導体装置の製造方法を説明するフローチャートである。 製造工程における半導体装置の断面図を示す図である。 製造工程における半導体装置の断面図を示す図である。 SnとTaとの相図である。 １２５℃放置試験での抵抗値変化を示す図である。 第１乃至第３金属層の材質および厚さの例を示す図である。 本開示を適用した半導体装置の第１の変形例を示す断面図である。 本開示を適用した半導体装置の第２の変形例を示す断面図である。 バンプパッドおよびマイクロバンプの径とバンプ容量の関係を示す図である。 バンプパッドとマイクロバンプの径と、抵抗値の関係を示す図である。 半導体装置の第２の変形例の応用例を示すブロック図である。 本開示を適用した半導体装置を積層型CMOSイメージセンサに適用した場合の積層前の状態を示す断面図である。 本開示を適用した半導体装置を積層型CMOSイメージセンサに適用した場合の積層後の状態を示す断面図である。 ロジックチップに形成されたＷＢパッドにI/Oを接続した状態を示す断面図である。 バンプパッドの形成に関する変形例を示す断面図である。 バンプパッドの形成に関する変形例を示す断面図である。 バンプパッドの形成に関する変形例を示す断面図である。
以下、本開示を実施するための最良の形態（以下、実施の形態と称する）について、図面を参照しながら詳細に説明する。
＜半導体装置の構成例＞
図３は、本開示の実施の形態である半導体装置の構成例を示す断面図である。ただし、同図は、積層されてSn系はんだにより電気的に接続される第１半導体素子と第２半導体素子のうち、マイクロバンプが形成されない方の第１半導体素子側のみを図示している。
なお、はんだの材料を示すSn系とは、SnAg系、SnBi系、SnCu系、SnIn系、SnAgCu系などを含むものとする。
図示するように、第１半導体素子１０上には、電極としてのAl PAD１１が設けられ、Al PAD１１の一部が、第２半導体素子のマイクロバンプと接続するための開口部２１（図５）とされて、開口部２１の上層に順に、第１金属層１３、第２金属層１４、および第３金属層１５が形成される。開口部２１以外には、SiO2層１２が形成され、その上層側にSiN層１６が形成される。
バリアメタルとしての第１金属層１３は、第２金属層１４に採用される金属の窒化膜として形成される。同図の場合、例えばTaNが採用される。第１金属層１３の平均厚みは、１０ｎｍ以上程度とする。これにより、特にパーティクルリスクを低減できるウエハプロセスラインにて、第１金属層１３の形成が可能となる。
第１金属層（バリアメタル）１３を設けることにより、Al PAD１１と第２金属層１４、および、第２半導体素子のマイクロバンプを成すSn系はんだと第２金属層１４との反応で生成し得る合金層とAl PAD１１が反応することを防止できる。これにより半導体装置の信頼性と電気特性の向上が期待できる。なお、第１金属層１３は省略してもよい。
第２金属層１４には、Sn系はんだと相図を持ち拡散性が低い、例えばTaが採用される。第２金属層１４の平均厚みは３０ｎｍ以上程度とする。これにより、特にパーティクルリスクを低減できるウエハプロセスラインにて第２金属層１４の形成が可能となる。第２金属層１４には、Taの他、Sn系はんだとの拡散性が低いバナジュウム族の金属（Ｖ，Nbなど）を採用することができる。
第３金属層１５には、第２金属層１４の表面に無洗浄フラックスや還元ガス等で表面酸化膜が還元可能であり、Snに対する拡散性が高い、例えば、Cuが採用される。第３金属層１５の平均厚みは第２金属層１４の酸化を防げるように８０ｎｍ以上程度とする。第３金属層１５には、Cuの他、Co，Ni，Pd，Au，Ptなどを採用することができる。
上述した構成を採用することにより、第２金属層１４の材料として非常に酸化が進み易く、還元が容易ではないTaやTiなど採用した場合でも、Sn系はんだと第２金属層１４を容易に接触（反応）させることができる。また、第２金属層１４にTaを採用することにより、信頼性と電気特性を向上させることができる。
＜半導体装置を製造する製造装置の製造方法＞
次に、図３に示された半導体装置の製造方法について、図４乃至図６を参照して説明する。
図４は、図３の半導体装置の製造方法を説明するフローチャートである。図５および図６は、製造過程を示す半導体装置の断面図である。
ステップＳ１では、図５Ａに示されるように、電極としてのAl PAD１１が設けられた第１半導体素子１０上にSiO2層１２が形成される。次に、SiO2層１２の上に、後述する開口部２１の位置や径に応じた、開口部２１以外の部分を保護するためのレジストパターニング（不図示）が施される。さらに、図５Ｂに示されるように、ドライエッチングによってAl PAD１１が露出するまでSiO2層１２が削られて開口部２１が設けられる。
ステップＳ２では、図５Ｃに示されるように、スパッタ法により、第１金属層（TaN）１３、第２金属層(Ta)１４、および第３金属層(Cu)１５が形成される。次に、ステップＳ３では、図５Ｄに示されるように、第３金属層１５と同じ材料（いまの場合、Cu）のメッキプロセスによって第３金属層１５の厚みが増加されて開口部２１の凹みが第３金属層１５によって埋められる。
ステップＳ４では、図５Ｅに示されるように、CMP(Chemical Mechanical Polishing)により、開口部２１以外の第３金属層１５、および第２金属層１４が除去される。ステップＳ５では、表面全体にパシベーション層としてのSiN層１６が形成され、SiN層１６の上にレジストパターニング（不図示）が施されて、さらに、図６Ａに示されるように、ドライエッチングによって開口部２１の第３金属層１５が露出するまでSiN層１６が削られる。これにより、開口部２１が凹構造となるため、第２半導体素子２３に形成されているSn系はんだからなるマイクロバンプ２４との位置合わせが容易となる。以下、マイクロバンプ２４と対向する開口部２１をバンプパッド２１とも称する。
ステップＳ６では、図６Ｂに示されるように、バンプパッド２１の第３金属層１５に、第２半導体素子２３に形成されているマイクロバンプ２４が接触され、ギ酸などの還元雰囲気化による加熱処理を行うことにより、第３金属層１５とマイクロバンプ２４を成すSn系はんだ表面の酸化膜が還元される。この後、ステップＳ７では、図６Ｃに示されるように、Sn系はんだに第３金属層１５が拡散されることによりSn系はんだと第２金属層１４が接触（反応）されて、第１半導体素子１０の電極であるAl PAD１１と第２半導体素子２３の電極との接続が確立される。以上で、製造方法の説明を終了する。
＜第２金属層１４とSn系はんだ１６との相図＞
図７は、第２金属層１４に採用したTaと、マイクロバンプ２４を成すSn系はんだに含まれるSnとの相図を示している。バンプ接続が２５０℃で行われた場合、同図に示されるように、TaとSnとの境界にはTa3SnまたはTa2Sn3の合金が生成されていると推察される。
＜高温放置時間におけるKelvin抵抗測定結果＞
図８は、第１金属層１３にTaN、第２金属層１４にTa、第３金属層１５にCuを採用した場合における第２金属層１４とSn系はんだから成るマイクロバンプ２４を接続した際の、125℃高温放置時間におけるKelvin抵抗測定結果を示したものである。同図に示されているように、168時間経過後も抵抗値は変化しなかった。したがって、第１半導体素子１０と第２半導体素子２３の電極どうしの電気的な接続は時間が経過しても維持されることが分かる。
＜第１金属層１３、第２金属層１４、および第３金属層１５の材料と厚さについて＞
次に、図９は、第２金属層１４の厚さと、第３金属層１５の材料と厚さを変化された場合の第１乃至第５の例と比較例（特許文献１に記載されている構成）の評価を示している。
第１の例は、第１金属層１３に１５ｎｍのTaN、第２金属層１４に１００ｎｍのTa、第３金属層１５に８０ｎｍのCuを採用した例である。第２の例は、第１金属層１３に１５ｎｍのTaN、第２金属層１４に１００ｎｍのTa、第３金属層１５に１００ｎｍのCoを採用した例である。第３の例は、第１金属層１３に１５ｎｍのTaN、第２金属層１４に１００ｎｍのTa、第３金属層１５に３６０ｎｍのCuを採用した例である。第４の例は、第１金属層１３に１５ｎｍのTaN、第２金属層１４に５０ｎｍのTa、第３金属層１５に８０ｎｍのCuを採用した例である。第５の例は、第１金属層１３に１５ｎｍのTaN、第２金属層１４に３０ｎｍのTa、第３金属層１５に８０ｎｍのCuを採用した例である。第１乃至第５の例のいずれの場合でも接続性と高温放置試験の結果には問題がなく、第１半導体素子１０と第２半導体素子２３の電極どうしの物理的および電気的な接続が確立された。なお、比較例では、電極どうしの物理的な接続は確立されるものの、時間の経過とともに抵抗値が増して電気的な接続は維持されなかった。
＜半導体装置の第１の変形例＞
図１０は、本開示の実施の形態である半導体装置の第１の変形例を示す断面図である。該第１の変形例は、図３に示された構成例から第１金属層１３は省略したものである。これにより、プロセスタクトの短縮とコスト削減が可能となる。
＜半導体装置の第２の変形例＞
次に、図１１は、本開示の実施の形態である半導体装置の第２の変形例を示す断面図である。
該第２の変形例は、第１半導体素子１０に設けられるバンプパッド２１の径を、接続する電極（線）の用途に応じて変更したものである。第１半導体素子１０に設けられた２ヶ所のバンプパッド２１は、バンプパッド２１−２がバンプパッド２１−１に比較してその径が大きく形成されている。
なお、同一基板（いまの場合における第１半導体素子１０）に設ける複数のバンプパッド２１の径の変更は、上述した製造処理のステップＳ１の工程でSiO2層１２の上に施されるレジストパターニング、およびステップＳ５の工程でSiN層１６の上に施されるレジストパターニングを変えることによって容易に行うことができる。
一方、第２半導体素子のSn系はんだから成るマイクロバンプ２４についても、その径を対応するバンプパッド２１の径に合わせて変更するようにする。
＜バンプパッド２１およびマイクロバンプ２４の径の違いに対するバンプ容量の変化＞
図１２は、バンプパッド２１の径（開口部径）と、マイクロバンプの径の違いに対するバンプ容量の変化を示している。
同図に示されるように、バンプパッド２１の径およびマイクロバンプ２４の径が小さい場合と大きい場合とを比較すると、小さい場合の方が、バンプ容量が小さい。したがって、径が小さいバンプパッド２１とマイクロバンプ２４により信号線を接続すれば、通信する電気信号の信号特性の改善が期待できる。さらに、この場合、接続する配線の引き回しを容易に行うことができる。
＜バンプパッド２１およびマイクロバンプ２４の径の違いに対する抵抗値の変化＞
図１３は、バンプパッド２１の径（開口部径）と、マイクロバンプ２４の径の違いに対する抵抗値の変化を示している。
同図に示されるように、バンプパッド２１の径およびマイクロバンプ２４の径がより大きいほど、抵抗値が小さい。したがって、より大きな径のバンプパッド２１とマイクロバンプ２４により電源線を接続すれば、IRドロップなどの電力供給に関する不具合の発生を抑止できる。
＜半導体装置の第２の変形例の応用例＞
次に、図１４は、図１１に示された第２の構成例の応用例を示している。
該応用例では、第１半導体素子１０の電源部３５と第２半導体素子２３の電源部３３をつなぐ電力線３５を、径が大きなバンプパッド２１−２とマイクロバンプ２４により接続している。また、第１半導体素子１０の信号処理部３２と第２半導体素子２３の信号処理部３４をつなぐ信号線３６，３７を、径が小さなバンプパッド２１−１とマイクロバンプ２４により接続している。
図１４に示された応用例によれば、第１半導体素子１０と第２半導体素子２３の間で通信する電気信号の信号特性を改善することができ、また、IRドロップなどの電力供給に関する不具合の発生を抑止できる。
＜半導体装置の適用例＞
次に、本開示の半導体装置を積層型CMOSイメージセンサ（以下、積層型CISと称する）に適用した場合の構成例について説明する。
図１５は本開示の半導体装置を適用した積層型CISの積層前の状態、図１６は積層後の状態を示している。
すなわち、該積層型CISは、光電変換を行う画素部が形成されている画素基板５１に、画素基板５１から出力される画素信号を処理するロジックチップ５２がCoW(Chip on Wafer)接続により積層されて構成される。
画素基板５１は、第１半導体素子１０に相当し、光の入射側の面にはロジックチップ５２のマイクロバンプ２４と接続するためのバンプバッド２１が形成される。一方、ロジックチップ５２は、第２半導体素子２３に相当し、画素基板５１との接続面にはマイクロバンプ２４が形成される。
画素基板５１とロジックチップ５２は、バンプパッド２１とマイクロバンプ２４が接触するように積層された状態で加熱処理され、これにより両者が電気的に接続される。なお、ロジックチップ５２の画素基板５１が接続された面の反対面には、図１７に示されるようにＷＢパッド７１が形成され、ＷＢパッド７１にI/O７２が接続される。
図示したように、積層型CMOSイメージセンサに本開示の半導体装置を適用することにより、画素基板５１側にもマイクロバンプを形成して接続した場合に発生し得る画素部のダスト欠陥などのダメージを抑止できる。また、画素基板５１とロジックチップ５２を積層した際の低背化を実現でき、ＣＦの掃きムラを抑止できる。
＜バンプパッドの形成に関する変形例＞
次に、バンプパッドの形成に関する変形例について説明する。
図１７は、画素基板５１内に貫通電極８１が形成される場合に、該貫通電極８１の位置に開口部２１を設け、該貫通電極８１をロジックチップ５２のマイクロバンプ２４に対応するバンプパッドとした変形例である。貫通電極８１自体をバンプパッドとした場合、第１金属層１３乃至第３金属層１５の形成を省略することができる。
図１９および図２０は、画素基板５１（第１半導体素子１０）からAl PAD１１を省略し、画素基板５１内部の金属配線（Cu配線）９１に達するまで、開口部２１を形成し、基板内部の該金属配線９１を、ロジックチップ５２のマイクロバンプ２４に対応するバンプパッドとした変形例である。
Al PAD１１を省略して画素基板５１内部の金属配線９１をバンプパッドとした場合、カスタム工程における掃きムラを改善することができ、また、チップシュリンク(chip shrink)が可能となる。さらに、ロジックチップ５２の低背化が実現できる。
なお、本開示の半導体装置は、上述した積層型CISの他、積層された半導体素子の電極どうしが接続されるあらゆる種類の電子装置に適用することが可能である。
本開示の実施の形態は、上述した実施の形態に限定されるものではなく、本開示の要旨を逸脱しない範囲において種々の変更が可能である。
なお、本開示は以下のような構成も取ることができる。
（１）
半導体素子が積層されて構成され、対向する前記半導体素子の電極どうしが電気的に接続されている半導体装置において、
前記対向する半導体素子の一方である第２半導体素子の電極には、Sn系はんだからなるマイクロバンプが形成され、
前記マイクロバンプを介して前記第２半導体素子の電極と接続されている、前記対向する半導体素子の他方である第１半導体素子の電極には、前記マイクロバンプに対向する凹形状のバンプパッドが形成されている
半導体装置。
（２）
前記バンプパッドには、前記マイクロバンプ側から順に、前記マイクロバンプに拡散された第３金属層、およびバナジウム族に属する金属からなる第２金属層が形成されている
前記（１）に記載の半導体装置。
（３）
前記第１半導体素子上には、径が異なる複数の前記バンプパッドが設けられている
前記（１）または（２）に記載の半導体装置。
（４）
前記バンプパッドの径は、接続する前記電極の用途に応じて異なる
前記（１）から（３）のいずれかに記載の半導体装置。
（５）
前記第２半導体素子の前記マイクロバンプの径は、対応する前記第１半導体素子の前記バンプパッドの径に対応している
前記（１）から（４）のいずれかに記載の半導体装置。
（６）
前記バンプパッドには、前記マイクロバンプ側から順に、前記第３金属層、前記第２金属層、および前記第２金属層に採用されたバナジウム族に属する前記金属の窒化膜からなる第１金属層が形成されている
前記（１）から（５）のいずれかに記載の半導体装置。
（７）
前記第２金属層の平均厚みは３０ｎｍ以上である
前記（１）から（６）のいずれかに記載の半導体装置。
（８）
前記第１金属層の平均厚みは１０ｎｍ以上である
前記（１）から（６）のいずれかに記載の半導体装置。
（９）
前記第２金属層はTaであり、前記第１金属層はTaNである
前記（１）から（６）のいずれかに記載の半導体装置。
（１０）
前記第３金属層はCu，Co，Ni，Pd，AuまたはPtである
前記（１）から（６）のいずれかに記載の半導体装置。
（１１）
前記バンプパッドは、前記第１半導体素子の表面から前記第１半導体素子内の貫通電極まで設けられた開口部により形成されている
前記（１）に記載の半導体装置。
（１２）
前記バンプパッドは、前記第１半導体素子の表面から前記第１半導体素子内の金属配線まで設けられた開口部により形成されている
前記（１）に記載の半導体装置。
（１３）
前記半導体装置は、前記第１半導体素子に相当する画素基板に、前記第２半導体素子に相当するロジックチップがCoW接続されている積層型CMOSイメージセンサである
前記（１）に記載の半導体装置。
（１４）
半導体素子が積層されて構成され、対向する前記半導体素子の電極どうしが電気的に接続されている半導体装置を製造する製造装置の製造方法において、
前記製造装置による、
前記対向する半導体素子の一方である第２半導体素子の電極にSn系はんだからなるマイクロバンプを形成するマイクロバンプ形成ステップと、
前記マイクロバンプを介して前記第２半導体素子の電極と接続される、前記対向する半導体素子の他方である第１半導体素子の電極に前記マイクロバンプに対向する凹形状のバンプパッドを形成するバンプパッド形成ステップと
を含む製造方法。
（１５）
前記バンプパッド形成ステップは、
前記マイクロバンプを介して前記第２半導体素子の電極と接続される、前記対向する半導体素子の他方である第１半導体素子の電極上に、バナジウム族に属する金属からなる第２金属層を形成し、
前記第２金属層上に、前記マイクロバンプに拡散される第３金属層を形成し、
第３金属層に前記マイクロバンプを接触させ、還元雰囲気化による加熱処理により、前記第３金属層と前記マイクロバンプの表面の酸化膜を還元し、前記第３金属層を前記マイクロバンプに拡散させることにより前記マイクロバンプと前記第２金属層を接触させて、前記第１半導体素子と前記第２半導体素子の電極どうしを電気的に接続する
前記（１４）に記載の製造方法。
（１６）
前記バンプパッド形成ステップは、さらに、
前記第１半導体素子の前記第３金属層の上にパシベーション層を形成し、前記パシベーション層をエッチングすることにより、前記第３金属層が露出する開口部を設ける
前記（１５）に記載の製造方法。
（１７）
前記バンプパッド形成ステップは、さらに、
前記第２金属層を形成する前に、前記マイクロバンプを介して前記第２半導体素子の電極と接続される、前記対向する半導体素子の他方である第１半導体素子の電極上に、前記第２金属層に採用されるバナジウム族に属する前記金属の窒化膜からなる第１金属層を形成する
前記（１５）に記載の製造方法。
（１８）
前記バンプパッド形成ステップは、前記第１半導体素子の表面から前記第１半導体素子内の貫通電極まで開口部を設けることにより前記バンプパッドを形成する
前記（１４）に記載の製造方法。
（１９）
前記バンプパッド形成ステップは、前記第１半導体素子の表面から前記第１半導体素子内の金属配線まで開口部を設けることにより前記バンプパッドを形成する
前記（１４）に記載の製造方法。
１０ 第１半導体素子， １１ Al PAD， １２ SiO2層， １３ 第１金属層， １４ 第２金属層， １５ 第３金属層， １６ SiN層， ２１ 開口部（バンプパッド）， ２３ 第２半導体素子， ２４ マイクロバンプ， ３１ 電源部， ３２ 信号処理部， ３３ 電源部， ３４ 信号処理部， ３５ 電源線， ３６，３７ 信号線， ５１ 画素基板， ５２ ロジックチップ， ８１ 貫通電極， ９１ Cu配線

Claims (19)

  1. 半導体素子が積層されて構成され、対向する前記半導体素子の電極どうしが電気的に接続されている半導体装置において、
    前記対向する半導体素子の一方である第２半導体素子の電極には、Sn系はんだからなるマイクロバンプが形成され、
    前記マイクロバンプを介して前記第２半導体素子の電極と接続されている、前記対向する半導体素子の他方である第１半導体素子の電極には、前記マイクロバンプに対向する凹形状のバンプパッドが形成されている
    半導体装置。
  2. 前記バンプパッドには、前記マイクロバンプ側から順に、前記マイクロバンプに拡散された第３金属層、およびバナジウム族に属する金属からなる第２金属層が形成されている
    請求項１に記載の半導体装置。
  3. 前記第１半導体素子上には、径が異なる複数の前記バンプパッドが設けられている
    請求項２に記載の半導体装置。
  4. 前記バンプパッドの径は、接続する前記電極の用途に応じて異なる
    請求項３に記載の半導体装置。
  5. 前記第２半導体素子の前記マイクロバンプの径は、対応する前記第１半導体素子の前記バンプパッドの径に対応している
    請求項２に記載の半導体装置。
  6. 前記バンプパッドには、前記マイクロバンプ側から順に、前記第３金属層、前記第２金属層、および前記第２金属層に採用されたバナジウム族に属する前記金属の窒化膜からなる第１金属層が形成されている
    請求項２に記載の半導体装置。
  7. 前記第２金属層の平均厚みは３０ｎｍ以上である
    請求項６に記載の半導体装置。
  8. 前記第１金属層の平均厚みは１０ｎｍ以上である
    請求項６に記載の半導体装置。
  9. 前記第２金属層はTaであり、前記第１金属層はTaNである
    請求項６に記載の半導体装置。
  10. 前記第３金属層はCu，Co，Ni，Pd，AuまたはPtである
    請求項６に記載の半導体装置。
  11. 前記バンプパッドは、前記第１半導体素子の表面から前記第１半導体素子内の貫通電極まで設けられた開口部により形成されている
    請求項１に記載の半導体装置。
  12. 前記バンプパッドは、前記第１半導体素子の表面から前記第１半導体素子内の金属配線まで設けられた開口部により形成されている
    請求項１に記載の半導体装置。
  13. 前記半導体装置は、前記第１半導体素子に相当する画素基板に、前記第２半導体素子に相当するロジックチップがCoW接続されている積層型CMOSイメージセンサである
    請求項１に記載の半導体装置。
  14. 半導体素子が積層されて構成され、対向する前記半導体素子の電極どうしが電気的に接続されている半導体装置を製造する製造装置の製造方法において、
    前記製造装置による、
    前記対向する半導体素子の一方である第２半導体素子の電極にSn系はんだからなるマイクロバンプを形成するマイクロバンプ形成ステップと、
    前記マイクロバンプを介して前記第２半導体素子の電極と接続される、前記対向する半導体素子の他方である第１半導体素子の電極に前記マイクロバンプに対向する凹形状のバンプパッドを形成するバンプパッド形成ステップと
    を含む製造方法。
  15. 前記バンプパッド形成ステップは、
    前記マイクロバンプを介して前記第２半導体素子の電極と接続される、前記対向する半導体素子の他方である第１半導体素子の電極上に、バナジウム族に属する金属からなる第２金属層を形成し、
    前記第２金属層上に、前記マイクロバンプに拡散される第３金属層を形成し、
    第３金属層に前記マイクロバンプを接触させ、還元雰囲気化による加熱処理により、前記第３金属層と前記マイクロバンプの表面の酸化膜を還元し、前記第３金属層を前記マイクロバンプに拡散させることにより前記マイクロバンプと前記第２金属層を接触させて、前記第１半導体素子と前記第２半導体素子の電極どうしを電気的に接続する
    請求項１４に記載の製造方法。
  16. 前記バンプパッド形成ステップは、さらに、
    前記第１半導体素子の前記第３金属層の上にパシベーション層を形成し、前記パシベーション層をエッチングすることにより、前記第３金属層が露出する開口部を設ける
    請求項１５に記載の製造方法。
  17. 前記バンプパッド形成ステップは、さらに、
    前記第２金属層を形成する前に、前記マイクロバンプを介して前記第２半導体素子の電極と接続される、前記対向する半導体素子の他方である第１半導体素子の電極上に、前記第２金属層に採用されるバナジウム族に属する前記金属の窒化膜からなる第１金属層を形成する
    請求項１５に記載の製造方法。
  18. 前記バンプパッド形成ステップは、前記第１半導体素子の表面から前記第１半導体素子内の貫通電極まで開口部を設けることにより前記バンプパッドを形成する
    請求項１４に記載の製造方法。
  19. 前記バンプパッド形成ステップは、前記第１半導体素子の表面から前記第１半導体素子内の金属配線まで開口部を設けることにより前記バンプパッドを形成する
    請求項１４に記載の製造方法。
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