CN105981160B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN105981160B
CN105981160B CN201580006909.0A CN201580006909A CN105981160B CN 105981160 B CN105981160 B CN 105981160B CN 201580006909 A CN201580006909 A CN 201580006909A CN 105981160 B CN105981160 B CN 105981160B
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metal layer
electrode
semiconductor element
semiconductor device
solder
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Expired - Fee Related
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CN201580006909.0A
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Chinese (zh)
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CN105981160A (zh
Inventor
胁山悟
城直树
清水完
林利彦
中村卓矢
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Sony Corp
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Sony Corp
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    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/018Manufacture or treatment of image sensors covered by group H10F39/12 of hybrid image sensors
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    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/18Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
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    • H10F39/80Constructional details of image sensors
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    • H10F39/80Constructional details of image sensors
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    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
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    • H10W72/01933Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01935Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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    • H10W72/01938Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
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    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07255Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in materials
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    • H10W72/241Dispositions, e.g. layouts
    • H10W72/244Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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    • H10W90/722Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
CN201580006909.0A 2014-04-23 2015-04-15 半导体装置及其制造方法 Expired - Fee Related CN105981160B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811352193.1A CN109637992B (zh) 2014-04-23 2015-04-15 半导体装置及其制造方法

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2014-088804 2014-04-23
JP2014088804 2014-04-23
JP2014256186A JP6424610B2 (ja) 2014-04-23 2014-12-18 半導体装置、および製造方法
JP2014-256186 2014-12-18
PCT/JP2015/002071 WO2015162872A1 (en) 2014-04-23 2015-04-15 Semiconductor device and method of manufacturing thereof

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CN105981160A CN105981160A (zh) 2016-09-28
CN105981160B true CN105981160B (zh) 2020-07-21

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US (3) US10600838B2 (https=)
JP (1) JP6424610B2 (https=)
KR (3) KR20220030314A (https=)
CN (2) CN105981160B (https=)
TW (1) TWI697074B (https=)
WO (1) WO2015162872A1 (https=)

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JP6424610B2 (ja) 2014-04-23 2018-11-21 ソニー株式会社 半導体装置、および製造方法
US9564418B2 (en) * 2014-10-08 2017-02-07 Micron Technology, Inc. Interconnect structures with intermetallic palladium joints and associated systems and methods
KR102720747B1 (ko) * 2015-03-12 2024-10-23 소니그룹주식회사 촬상 장치, 제조 방법 및 전자 기기
US9812555B2 (en) * 2015-05-28 2017-11-07 Semiconductor Components Industries, Llc Bottom-gate thin-body transistors for stacked wafer integrated circuits
US10522582B2 (en) * 2015-10-05 2019-12-31 Sony Semiconductor Solutions Corporation Imaging apparatus
JP6639188B2 (ja) * 2015-10-21 2020-02-05 ソニーセミコンダクタソリューションズ株式会社 半導体装置、および製造方法
CN106057692B (zh) * 2016-05-26 2018-08-21 河南工业大学 一种三维集成电路堆栈集成方法及三维集成电路
MX387378B (es) * 2016-11-22 2025-03-18 Senju Metal Industry Co Metodo de soldadura.
JP6685470B2 (ja) * 2017-03-30 2020-04-22 三菱電機株式会社 半導体装置およびその製造方法、ならびに電力変換装置
KR102380823B1 (ko) 2017-08-16 2022-04-01 삼성전자주식회사 발열체를 포함하는 칩 구조체
US11257745B2 (en) * 2017-09-29 2022-02-22 Intel Corporation Electroless metal-defined thin pad first level interconnects for lithographically defined vias
CN110660809B (zh) * 2018-06-28 2023-06-16 西部数据技术公司 包含分支存储器裸芯模块的垂直互连的半导体装置
US10622321B2 (en) 2018-05-30 2020-04-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structures and methods of forming the same
KR102830541B1 (ko) 2020-09-23 2025-07-07 삼성전자주식회사 반도체 칩의 접속 구조물 및 접속 구조물을 포함하는 반도체 패키지
US11824037B2 (en) * 2020-12-31 2023-11-21 International Business Machines Corporation Assembly of a chip to a substrate
US20230135057A1 (en) * 2021-10-28 2023-05-04 Skyworks Solutions, Inc. Dual sided molded package with varying interconnect pad sizes and uniform exposed solderable area
US20250015117A1 (en) * 2023-07-06 2025-01-09 Semiconductor Components Industries, Llc Pads for image sensors and related methods
US20250192099A1 (en) * 2023-12-06 2025-06-12 Qualcomm Incorporated Integrated circuit(ic) package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce die-substrate clearance

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US4617730A (en) * 1984-08-13 1986-10-21 International Business Machines Corporation Method of fabricating a chip interposer
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US20060292824A1 (en) * 2005-06-08 2006-12-28 Eric Beyne Methods for bonding and micro-electronic devices produced according to such methods
US7427557B2 (en) * 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
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