CN108878390B - 梳状凸块结构及其制造方法 - Google Patents

梳状凸块结构及其制造方法 Download PDF

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CN108878390B
CN108878390B CN201711009578.3A CN201711009578A CN108878390B CN 108878390 B CN108878390 B CN 108878390B CN 201711009578 A CN201711009578 A CN 201711009578A CN 108878390 B CN108878390 B CN 108878390B
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metal
bump
comb
soldering tin
conductive layer
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CN108878390A (zh
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林柏均
朱金龙
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明公开了一种梳状凸块结构及其制造方法，梳状凸块结构包含：半导体基板；焊垫设置于半导体基板之上；导电层设置于焊垫于之上；焊锡凸块设置于导电层之上；以及至少两个金属侧壁，分别沿焊锡凸块的相对两侧设置，从而提升结合强度。

Description

梳状凸块结构及其制造方法
技术领域
本发明是有关于梳状凸块结构及其制造方法。
背景技术
半导体器件用于大量电子设备，例如计算机，蜂窝电话等。半导体器件包括通过在半导体晶片上沉积许多类型的材料薄膜而形成在半导体晶片上的集成电路(IC)，以及图案化材料薄膜以形成集成电路。
再分配层(RDL)过程是采用原始设计的IC的I/O焊垫，并使用晶片级金属布线处理和触碰处理来改变IC的接触点位置。形成凸块(Bumping)是先进的晶片级工艺技术，其中在将晶片切割成单个芯片之前，以整个晶片形式在晶片上形成由焊料制成的“凸块”或“球”。
如今，低成本RDL/Bumping解决方案普遍加工，但不能处理细间距产品。钝化后的聚亚酰胺(PI)下面的PI可以是良好的缓冲层，但是PI的弱点对于其他钝化本身或金属的粘合强度低。因此，当处理不正确地控制时，PI有时会很容易地从晶片剥离。
发明内容
本发明提出一种创新的梳状凸块结构及其制造方法，以解决先前技术的困境，从而提升结合强度。
在本发明的一实施例中，一种梳状凸块结构包含：半导体基板；焊垫设置于半导体基板之上；导电层设置于焊垫之上；焊锡凸块设置于导电层之上；以及至少两个金属侧壁，分别沿焊锡凸块的相对两侧设置。
在本发明的一实施例中，梳状凸块结构更包含：钝化层，设置于半导体基板之上，钝化层具有开口以部分暴露焊垫，且导电层连接于焊垫以及钝化层。
在本发明的一实施例中，金属侧壁垂直设置在导电层上。
在本发明的一实施例中，任一个金属侧壁的顶部高于焊锡凸块的顶部。
在本发明的一实施例中，梳状凸块结构还包含：多个金属针脚，设置在焊锡凸块中，并从导电层突出。
在本发明的一实施例中，任一个金属针脚的顶部高于焊锡凸块的顶部。
在本发明的一实施例中，任一个金属针脚的顶部低于任一个金属侧壁的顶部。
在本发明的一实施例中，金属侧壁的熔点温度高于金属针脚的熔点温度。
在本发明的一实施例中，导电层包含凸块下金属层。
在本发明的另一实施例中，一种梳状凸块结构包含：第一半导体基板；第一焊垫，设置于第一半导体基板之上；第一导电层设置于第一焊垫之上；第一焊锡凸块设置于第一导电层之上；至少两个第一金属侧壁分别沿第一焊锡凸块的相对两侧设置；第二半导体基板；第二焊垫设置于第二半导体基板之上；第二导电层设置于第二焊垫之上；第二焊锡凸块设置于第二导电层之上；以及至少两个第二金属侧壁，分别沿第二焊锡凸块的相对两侧设置，当第一、第二焊锡凸块相结合且执行回焊工艺时，第二焊锡凸块与第一焊锡凸块用于形成焊点。
在本发明的另一实施例中，至少两个第一金属侧壁中的一个位于焊点中，并位于至少两个第二金属侧壁之间。
在本发明的另一实施例中，至少两个第二金属侧壁中的一个位于焊点中，并位于至少两个第一金属侧壁之间。
在本发明的另一实施例中，至少两个第一金属侧壁位于焊点中的那个与至少两个第二金属侧壁中位于焊点中的那个的熔点温度低于至少两个第一金属侧壁中的另一个与至少两个第二金属侧壁中的另一个的熔点温度。
在本发明的另一实施例中，梳状凸块结构还包含：多个第一金属针脚，设置于第一焊锡凸块中，并从第一导电层突出；以及
在本发明的另一实施例中，多个第二金属针脚，设置于第二个焊锡凸块中，并从第二导电层突出，且第一，第二金属针脚交替排列在焊点中。
在本发明的另一实施例中，第一、第二金属针脚的熔点温度低于至少两个第一金属侧壁中的另一个与至少两个第二金属侧壁中的另一个的熔点温度。
在本发明的又一实施例中，一种梳状凸块结构的制造方法包含：提供半导体基板；在半导体基板之上形成焊垫；在焊垫之上形成导电层；在导电层之上形成焊锡凸块；以及形成至少两个金属侧壁分别沿焊锡凸块的相对两侧设置。
在本发明的又一实施例中，任一个金属侧壁的顶部高于焊锡凸块的顶部。
在本发明的又一实施例中，制造方法，还包含：形成多个金属针脚，从导电层突出，并设置在焊锡凸块中。
在本发明的又一实施例中，金属侧壁的熔点温度高于金属针脚的熔点温度。
在本发明的又一实施例中，任一个金属侧壁的顶部高于焊锡凸块的顶部。
综上所述，本发明的技术方案与现有技术相比具有明显的可提升结合强度的有益效果。以下将以实施方式对上述的说明作详细的描述，并对本发明的技术方案提供更进一步的解释。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂，现结合附图说明如下：
图1是依照本发明实施例的一种梳状凸块结构的剖面图；
图2是依照本发明实施例的一种梳状凸块结构的剖面图；
图3A、图3B是依照本发明实施例的一种梳状凸块结构在接合之前和之后的剖面图；
图4A、图4B是依照本发明实施例的一种梳状凸块结构在接合之前和之后的剖面图；以及
图5A～图5F是依照本发明实施例绘示的一种梳状凸块结构的制造程序。
具体实施方式
为了使本发明的叙述更加详尽与完备，可参照所附的附图及以下所述各种实施例，附图中相同的号码代表相同或相似的元件。另一方面，众所周知的元件与步骤并未描述于实施例中，以避免对本发明造成不必要的限制。
在实施方式与申请专利范围中，涉及“电性连接”的描述，其可泛指一个元件通过其他元件而间接电气耦合至另一个元件，或是一个元件无须通过其他元件而直接电气连结至另一个元件。
在实施方式与申请专利范围中，除非内文中对于冠词有所特别限定，否则“一”与“该”可泛指单一个或多个。
图1是依照本发明实施例的一种梳状凸块结构100图。如图1所示，焊垫120设置在半导体基板110上，导电层140设置在焊垫120上。另外，一个或多个钝化层130设置在半导体基板110上，钝化层130具有部分露出焊垫120的开口，并且导电层140在焊垫120和钝化层130处连接。
在图1中，焊接凸块150设置在导电层140上，并且至少两个金属侧壁160分别沿着焊料凸块150的相对两侧设置并垂直设置在导电层140上，从而提高后续工艺中的接合强度。
在结构中，任何一个金属侧壁160的顶部高于焊料凸块160的顶部。换句话说，焊接凸块150的顶部与钝化层130的顶部之间的垂直距离小于金属侧壁160的顶部与钝化层130的顶部之间的垂直距离。
在一些实施例中，导电层140是或包括凸块下金属层。例如，凸块下金属层可以是金属的复合层，例如铬，随后是铜，随后是金，以促进改善的附着力(与铬)并形成扩散阻挡层或防止氧化(金在铜上)。
图2是依照本发明实施例的一种梳状凸块结构的剖面图。如图2所示，焊垫220设置在半导体基板210上，导电层240设置在焊垫220上。另外，一个或多个钝化层230设置在半导体基板210上，钝化层230具有部分露出焊垫220的开口，并且导电层240连接于焊垫220和钝化层230。
在图2中，焊接凸块250设置在导电层240上，并且至少两个金属侧壁260分别设置在焊接凸块250的相对两侧，并垂直设置在导电层240上，从而提高后续工艺中的接合强度。
另外，金属针脚270设置在焊接凸块250中并且从导电层240突出，以进一步提高后续过程中的接合强度。在一些实施例中，金属侧壁260的熔点温度高于金属针脚270的熔点温度。
在结构中，任何金属针脚270的顶部高于焊接凸块250的顶部。换句话说，焊接凸块250的顶部与钝化层230的顶部之间的垂直距离小于金属针脚270的顶部和钝化层130的顶部之间的垂直距离。此外，任一个金属针脚270的顶部可以低于任一个金属侧壁260的顶部。
图3A、图3B是依照本发明实施例的一种梳状凸块结构300在接合之前和之后的剖面图。如图3A所示，第一焊垫320设置在第一半导体基板310上，第一导电层340设置在第一焊垫320上。一个或多个第一钝化层330设置在第一半导体基板310上。第一焊锡凸块350设置在第一导电层340上，并且至少两个第二金属侧壁360、361分别沿着第一焊锡凸块350的相对两侧设置。
另外，在图3A中，第二焊垫322设置在第二半导体基板312上，第二导电层342设置在第二焊垫322上。一个或多个第二钝化层332设置在第二导体体基板312上。第二焊锡凸块352设置在第二导电层342上，并且至少两个第二金属侧壁362、363分别沿着第二个焊锡凸块352的相对两侧设置。
当第一，第二焊锡凸块350、352相结合且回焊工艺执行时，第二焊锡凸块352与第一焊锡凸块350形成焊点356(如图3B所示)。第一焊垫320和第二焊垫322之间的垂直距离大于金属侧壁360-363中任一个(如第二金属侧壁363)的垂直长度。
如图3B所示，第一金属侧壁360设置在焊点356中，并且位于至少两个第二金属侧壁362、363之间。第二金属侧壁363设置在焊点356中，并位于至少两个第一金属侧壁360和361之间。在一些实施例中，第一、第二金属侧壁360、363的熔点温度低于第一，第二金属侧壁361、362的熔点温度。
图4A、图4B是依照本发明实施例的一种梳状凸块结构在接合之前和之后的剖面图。如图4A所示，第一焊垫420设置在第一半导体基板410上，第一导电层440设置在第一焊垫420上。一个或多个第一钝化层430设置在第一半导体基板410上。第一焊锡凸块450设置在第一导电层440上，至少两个第一金属侧壁460、461沿第一焊锡凸块450的相对两侧设置。第一金属针脚470设置在第一焊锡凸块450中，并且从第一导电层440突出。
另外，在图4A中，第二焊垫422设置在第二半导体基板412上，第二导电层442设置在第二焊垫422上。一个或多个第二钝化层432设置在第二半导体基板412上。第二焊锡凸块452设置在第二导电层442上，至少两个第二金属侧壁462、463沿第二焊锡凸块452的相对两侧设置。第二金属针脚472设置在第二焊锡凸块452中，并且从第二导电层442突出。
当第一，第二焊锡凸块450、452相结合且回焊工艺执行时，第二焊锡凸块452与第一焊锡凸块450形成焊点456(如图4B所示)。
如图4B所示，第一、第二金属针脚470、472交替地布置在焊点456中。第一金属侧壁461设置在焊点456中，并且位于两个第二金属侧壁462、463之间。第二金属侧壁462设置在焊点456中，并且位于两个第一金属侧壁460、461之间。在一些实施例中，第一、第二金属侧壁461、462的熔点温度和第一、第二金属针脚470、472系低于第一、第二金属侧壁460、463的熔点温度。
图5A～图5F是依照本发明实施例绘示的一种梳状凸块结构的制造程序。应了解到，在本实施例中所提及的步骤，除特别叙明其顺序者外，均可依实际需要调整其前后顺序，甚至可同时或部分同时执行。
如图5A所示，提供半导体基板510。在半导体基板510上形成焊垫520，在半导体基板510上形成一个或多个钝化层530，钝化层530部分地露出焊垫520，形成凸块下金属层540连接于焊垫520和钝化层530。光阻层580形成在凸块下金属层542上。光阻层580可以被曝光和显影以形成第一开口582。第一开口582可以将焊垫520上的凸块下金属层542的一部分暴露出来。
如图5B所示，导电层540形成在凸块下金属层542的上述部分之上。光阻层583形成在导电层540上。光阻层583可以被曝光和显影以形成第二开口584，第二开口584可以暴露在凸块下金属层542上的导电层540上的一部分。
如图5C所示，焊接凸块550形成在导电层540上，并且对应于上述第二开口584的位置。
如图5D所示，在凸块下金属层542上形成光阻层585。
如图5E所示，金属侧壁560分别沿着焊锡凸块550的外侧边缘形成。金属针脚570形成在导电层540上，并且设置在焊接凸块550中。
如图5F所示，去除了焊锡凸块550，金属侧壁560和金属针脚570的冗余部分。例如，通过使用化学机械平面化(CMP)工艺来抛光焊锡凸块550、金属侧壁560和金属针脚570的尖端，以便去除冗余部分。
虽然本发明已以实施方式公开如上，然其并非用以限定本发明，任何本领域的一般技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求所界定的为准。

Claims (13)

1.一种梳状凸块结构，其特征在于，包含：
半导体基板；
焊垫，设置于所述半导体基板之上；
导电层，设置于所述焊垫之上；
焊锡凸块，设置于所述导电层之上；
至少两个金属侧壁，分别沿所述焊锡凸块的相对两侧设置，任一个所述金属侧壁的顶部高于所述焊锡凸块的顶部；以及
多个金属针脚，设置在所述焊锡凸块中，并从所述导电层突出，任一个所述金属针脚的顶部高于所述焊锡凸块的顶部。
2.如权利要求1所述的梳状凸块结构，其特征在于，还包含：
钝化层，设置于所述半导体基板之上，所述钝化层具有开口以部分暴露所述焊垫，且所述导电层连接于所述焊垫以及所述钝化层。
3.如权利要求1所述的梳状凸块结构，其特征在于，所述金属侧壁垂直设置在所述导电层上。
4.如权利要求1所述的梳状凸块结构，其特征在于，任一个所述金属针脚的顶部低于任一个所述金属侧壁的顶部。
5.如权利要求1所述的梳状凸块结构，其特征在于，所述金属侧壁的熔点温度高于所述金属针脚的熔点温度。
6.如权利要求5所述的梳状凸块结构，其特征在于，所述导电层包含凸块下金属层。
7.一种梳状凸块结构，其特征在于，包含：
第一半导体基板；
第一焊垫，设置于所述第一半导体基板之上；
第一导电层，设置于所述第一焊垫之上；
第一焊锡凸块，设置于所述第一导电层之上；
至少两个第一金属侧壁，分别沿所述第一焊锡凸块的相对两侧设置，任一个所述第一金属侧壁的顶部高于所述第一焊锡凸块的顶部；
多个第一金属针脚，设置于所述第一焊锡凸块中，并从所述第一导电层突出，任一个所述第一金属针脚的顶部高于所述第一焊锡凸块的顶部；
第二半导体基板；
第二焊垫，设置于所述第二半导体基板之上；
第二导电层，设置于所述第二焊垫之上；
第二焊锡凸块，设置于所述第二导电层之上；
至少两个第二金属侧壁，分别沿所述第二焊锡凸块的相对两侧设置，任一个所述第二金属侧壁的顶部高于所述第二焊锡凸块的顶部，当所述第一、第二焊锡凸块相结合且执行回焊工艺时，第二焊锡凸块与所述第一焊锡凸块用于形成焊点；以及
多个第二金属针脚，设置于所述第二焊锡凸块中，并从所述第二导电层突出，且所述第一，第二金属针脚交替排列在所述焊点中，任一个所述第二金属针脚的顶部高于所述第二焊锡凸块的顶部。
8.如权利要求7所述的梳状凸块结构，其特征在于，所述至少两个第一金属侧壁中的一个位于所述焊点中，并位于所述至少两个第二金属侧壁之间。
9.如权利要求8所述的梳状凸块结构，其特征在于，所述至少两个第二金属侧壁中的一个位于所述焊点中，并位于所述至少两个第一金属侧壁之间。
10.如权利要求9所述的梳状凸块结构，其特征在于，所述至少两个第一金属侧壁中的所述一个与所述至少两个第二金属侧壁中的所述一个的熔点温度低于所述至少两个第一金属侧壁中的另一个与所述至少两个第二金属侧壁中的另一个的熔点温度。
11.如权利要求10所述的梳状凸块结构，其特征在于，所述第一、第二金属针脚的熔点温度低于所述至少两个第一金属侧壁中的所述另一个与所述至少两个第二金属侧壁中的所述另一个的熔点温度。
12.一种梳状凸块结构的制造方法，其特征在于，所述制造方法包含：
提供半导体基板；
在所述半导体基板之上形成焊垫；
在所述焊垫于之上形成导电层；
在所述导电层之上形成焊锡凸块；以及
形成至少两个金属侧壁分别沿所述焊锡凸块的相对两侧设置，任一个所述金属侧壁的顶部高于的所述焊锡凸块的顶部；以及
形成多个金属针脚，从所述导电层突出，并设置在所述焊锡凸块中，任一个所述金属针脚的顶部高于所述焊锡凸块的顶部。
13.如权利要求12所述的制造方法，其特征在于，所述金属侧壁的熔点温度高于所述金属针脚的熔点温度。
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Publication number Priority date Publication date Assignee Title
US10838732B2 (en) 2018-12-21 2020-11-17 Micron Technology, Inc. Apparatuses and methods for ordering bits in a memory device
JP7525878B2 (ja) 2020-06-17 2024-07-31 東北マイクロテック株式会社 積層型半導体装置及びこれに用いる搭載部品、基体及びバンプ接続体
US20230107847A1 (en) * 2021-10-06 2023-04-06 Taiwan Semiconductor Manufacturing Company Limited High-density microbump arrays with enhanced adhesion and methods of forming the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100392834C (zh) * 2003-09-23 2008-06-04 三星电子株式会社 加强的焊料凸块结构以及形成加强的焊料凸块的方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05226419A (ja) * 1991-07-09 1993-09-03 Oki Electric Ind Co Ltd 半導体素子と基板の接続構造
KR100541396B1 (ko) * 2003-10-22 2006-01-11 삼성전자주식회사 3차원 ｕｂｍ을 포함하는 솔더 범프 구조의 형성 방법
US7713858B2 (en) * 2006-03-31 2010-05-11 Intel Corporation Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same
JP2008135654A (ja) * 2006-11-29 2008-06-12 Sanyo Electric Co Ltd 太陽電池モジュール
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
EP2075834A1 (en) 2007-12-28 2009-07-01 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) Solder bumps for flip chip bonding with higher density
JP4591529B2 (ja) * 2008-03-26 2010-12-01 株式会社デンソー バンプの接合方法およびバンプの接合構造体
US8310367B1 (en) * 2009-05-18 2012-11-13 Empire Technology Development Llc Methods of implanting electronics in objects and objects with implanted electronics
JP2011176011A (ja) 2010-02-23 2011-09-08 Panasonic Corp 半導体集積回路装置
US8507940B2 (en) 2010-04-05 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Heat dissipation by through silicon plugs
US9048135B2 (en) * 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
FR2978002B1 (fr) * 2011-07-15 2015-12-11 Dictao Procede de signature authentique d'un document de travail
JP5720485B2 (ja) 2011-08-12 2015-05-20 オムロン株式会社 電子部品
US9230932B2 (en) * 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
KR101936232B1 (ko) * 2012-05-24 2019-01-08 삼성전자주식회사 전기적 연결 구조 및 그 제조방법
US8653626B2 (en) * 2012-07-18 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US9040334B2 (en) * 2013-03-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS integrated pressure sensor devices and methods of forming same
US20150262920A1 (en) * 2014-03-17 2015-09-17 Texas Instruments Incorporated Integrated circuit package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100392834C (zh) * 2003-09-23 2008-06-04 三星电子株式会社 加强的焊料凸块结构以及形成加强的焊料凸块的方法

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