TWI678812B - 半導體記憶裝置 - Google Patents

半導體記憶裝置 Download PDF

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TWI678812B
TWI678812B TW105111230A TW105111230A TWI678812B TW I678812 B TWI678812 B TW I678812B TW 105111230 A TW105111230 A TW 105111230A TW 105111230 A TW105111230 A TW 105111230A TW I678812 B TWI678812 B TW I678812B
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floating gate
insulating film
state
tunnel
gate
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TW201705497A (zh
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理崎智光
Tomomitsu Risaki
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日商艾普凌科有限公司
Ablic Inc.
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Abstract

為一種半導體記憶裝置，其中半導體組成的浮動閘極係由導電型之極性不同的第1浮動閘極和第2浮動閘極構成。藉由上述第2浮動閘極之價電子帶之電洞減少記憶電子經由隧道絕緣膜而被注入至上述第1浮動閘極之情形，藉由上述第2浮動閘極之價電子帶之電洞增加記憶電子經上述隧道絕緣膜而從上述第1浮動閘極被排出之情形。

Description

半導體記憶裝置
本發眀係關於半導體記憶裝置。
以EEPROM為例，說明以往之半導體記憶裝置。圖5為表示以往之EEPROM之概念圖，為揭示於專利文獻1之一般的構造。
構成EEPROM之單位單元係由記憶本體部002和選擇記憶本體部002之選擇閘極電晶體部001所構成。在記憶本體部002存在儲存電荷之電極，且該電極被稱為浮動閘極013。當在該浮動閘極013儲存電子時，記憶本體部002成為臨界值高之狀態的增強，為“1”狀態。成為當儲存電洞時臨界值低之狀態的空乏，為“0”狀態。
朝向“1”狀態之寫入係對選擇閘極003和控制閘極015施加正電壓，使n型選擇電晶體汲極區域005和n型記憶單元源極011和p型半導體基板006之電位成為GND，隔著隧道絕緣膜010將電子從n型隧道汲極區域009注入至浮動閘極013。以下，使用能帶圖針對朝向“1”狀態之寫 入進行說明。
圖6係沿著圖5之線段A-A’的能帶圖，表示朝向“1”狀態寫入時之狀態的變化。省略p型半導體基板006。圖中之E F、E C、E V分別表示費米能階、傳導帶之下端、價電子帶之上端。在此，浮動閘極013和控制閘極015假設為n型之多晶矽。
在圖6(a)所示之熱平衡狀態之記憶單元電晶體中，當將上述表示的“1”狀態寫入時之電壓狀態，即是n型隧道汲極區域009之電位設為GND，將控制閘極015之電位設為正時，成為圖6(b)所示之能帶圖，如圖6(b)之箭號所示般，電子018經由隧道絕緣膜010從n型隧道汲極區域009以FN(Fowler-Nordheim)電流機構被注入至浮動閘極013。被注入電子018之浮動閘極013之電位如圖6(c)之空白箭號所示般下降(在圖中上升)，當被施加至隧道絕緣膜101之電位變弱，FN電流停止時，“1”狀態之寫入動作完成。
因EEPROM係即使切斷電源亦可以保持資訊的非揮發性記憶體，故如圖6(d)所示般，在將n型隧道汲極區域009和控制閘極015之電位設為GND之狀態下，必須具有一般可以將“1”狀態保持數十年間的能力。但是，由於如圖6(c)之空白箭號所示般，藉由被注入至浮動閘極013之電子018，浮動閘極013之電位下降，故在資料保持狀態的圖6(d)中成為被注入至浮動閘極013之電子018經隧道絕緣膜010而漏至n型隧道汲極區域009 之方向的電場被施加至隧道絕緣膜010的狀態。在該狀態下，於隧道絕緣膜010薄時或劣化之時，如圖6(d)所示般，有產生非意圖之電子洩漏020且引起資料保持不良之情形。
接著，針對“0”狀態進行研討。朝向“0”狀態之寫入係對選擇閘極003和n型選擇電晶體汲極區域005施加正電壓，將控制閘極015和p型半導體基板006連接於GND，且使n型記憶單元電晶體源極區域011成為浮動狀態，使電子018從浮動閘極013經隧道絕緣膜010排出至n型隧道汲極區域009。以下以能帶圖說明此。
在圖7表示沿著“0”狀態寫入時之圖5之線段A-A’的能帶圖。圖6同樣地省略p型半導體基板0006，E F、E C、E V分別表示費米能階、傳導帶之下端、價電子帶之上端。再者，浮動閘極013和控制閘極015假設為n型之多晶矽。
在圖7(a)所示之熱平衡狀態之記憶單元電晶體中，當將上述表示的“0”狀態寫入時之電壓狀態，即是將控制閘極015之電位設為GND，將n型隧道汲極區域009之電位設為正時，成為圖7(b)般之能帶圖，如圖7(b)之箭號所示般，電子018經由隧道絕緣膜010從浮動閘極013以FN(Fowler-Nordheim)電流機構被注入至n型隧道汲極區域009。電子018減少的浮動閘極013之電位如圖7(c)之空白箭號所示般上升，當被施加至隧道絕緣膜010之電位變弱，FN電流停止時，“0”狀態之寫 入動作完成。
因EEPROM係即使切斷電源亦可以保持資訊的非揮發性記憶體，故如圖7(d)所示般，在將n型隧道汲極區域009和控制閘極015之電位設為GND之狀態下，必須具有一般可以將“0”狀態保持數十年間的能力。但是，由於如圖7(c)之空白箭號所示般，藉由被注入至浮動閘極013之電子018，浮動閘極013之電位上升，故在資料保持狀態的圖7(d)中成為n型隧道汲極區域009之電子018經隧道絕緣膜010被注入至浮動閘極013之方向的電場被施加至隧道絕緣膜010的狀態。在該狀態下，於隧道絕緣膜010薄時或劣化之時，如圖7(d)所示般，有產生非意圖之電子洩漏020且引起資料保持不良之情形。
如此一來，在非揮發性記憶體中產生資料保持不良(保留不良)問題。專利文獻2係抑制上述保留不良的手法。該發明係藉由降低隧道絕緣膜附近之浮動閘極內雜質濃度，抑制隧道絕緣膜中之阱部位，抑制阱部位由於原因產生的保留不良。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2004-071077號公報
[專利文獻2]日本特開平11-067940號公報
但是，就算使用專利文獻1之手法，阻礙存在於浮動閘極013內之電荷之保持的方向之電場被施加於隧道絕緣膜010之情形也不會改變，不會成為在使用圖6及圖7中所說明的保留不良之根本改善。再者，作為抑制保留不良之另外的手法，雖然舉出單純地增加隧道絕緣膜010厚度之手法，但是該也不會成為藉由圖6及圖7所書說明之保留不良的根本改善。由於增加隧道絕緣膜010之膜厚的部分，需要高的寫入電壓，故其結果，產生晶片尺寸變大的問題。
即是，可以換句說該些改善手段就算使不流出成為資料保持之障礙的非意圖電子洩漏020，亦無法使隧道絕緣膜010薄膜化，該可以說成為寫入電壓低電壓化和晶片尺寸縮小之障礙而成為非揮發性記憶體之貫穿的妨礙。
為了解決上述課題，使用以下之手段。
半導體組成的浮動閘極係由第1浮動閘極和第2浮動閘極構成，成為上述第1浮動閘極和上述第2浮動閘極之導電型之極性不同的半導體記憶裝置。
再者，具有：記憶單元電晶體源極區域，其係被形成在第1導電型之半導體基板的表層；記憶單元電晶體汲極區域，其係被形成與上述記憶單 元電晶體源極區域間隔開；隧道汲極區域，其係被設置成在上述記憶單元電晶體源極區域和上述記憶單元電晶體汲極區域之間與上述記憶單元電晶體汲極區域接觸；隧道絕緣膜，其係被設置在上述隧道汲極區域之一部分的上述半導體基板上；閘極絕緣膜，其係被設置在上述隧道汲極區域之一部分和上述記憶單元電晶體源極區域之一部分和上述隧道汲極區域和上述記憶單元電晶體源極區域之間的上述半導體基板上；第1浮動閘極，其係隔著包含上述隧道絕緣膜之上述閘極絕緣膜而被形成在上述半導體基板上；第2浮動閘極，其係被設置成與上述第1浮動閘極接觸；及控制閘極，其係經絕緣膜被形成在上述第2浮動閘極上。
因抑制資料保持狀態下的洩漏電流，可取得提升保留特性之效果。而且，由於亦能夠使隧道絕緣膜厚薄膜化，故能夠使資料寫入成為低電壓化，且關係到晶片尺寸之縮小。
001‧‧‧選擇電晶體
002‧‧‧記憶單元電晶體
003‧‧‧選擇閘極
004‧‧‧選擇閘極絕緣膜
005‧‧‧n型選擇電晶體汲極區域
006‧‧‧p型半導體基板
007‧‧‧n型區域
008‧‧‧n型選擇電晶體源極區域(n型記憶單元電晶體汲極區域)
009‧‧‧n型隧道汲極區域
010‧‧‧隧道絕緣膜
011‧‧‧n型記憶單元電晶體源極區域
012‧‧‧記憶單元閘極絕緣膜
013‧‧‧浮動閘極
014‧‧‧浮動控制閘極間絕緣膜
015‧‧‧控制閘極
016‧‧‧第1浮動閘極
017‧‧‧第2浮動閘極
018‧‧‧電子
019‧‧‧電洞
020‧‧‧非意圖的電子洩漏
圖1為表示本發明之EEPROM的剖面圖。
圖2為表示本發明之EEPROM之圖1之線段的A-A’的能帶圖，說明“1”狀態寫入的圖示。為熱平衡狀態，(b)為“1”狀態寫入初期，(c)為“1”狀態寫入結束，(d)為“1”狀態保持之能帶圖。
圖3為表示本發明之EEPROM之圖1之線段的A-A’的能帶圖，說明“0”狀態寫入的圖示。(a)為熱平衡狀態，(b)為“0”狀態寫入初期，(c)為“0”狀態寫入結束，(d)為“0”狀態保持之能帶圖。
圖4為表示本發明之EEPROM的剖面圖。
圖5為表示以往之EEPROM的剖面圖。
圖6為表示以往之EEPROM之圖5之線段的A-A’的能帶圖，說明“1”狀態寫入的圖示。(a)為熱平衡狀態，(b)為“1”狀態寫入初期，(c)為“1”狀態寫入結束，(d)為“1”狀態保持之能帶圖。
圖7為表示以往之EEPROM之圖5之線段的A-A’的能帶圖，說明“0”狀態寫入的圖示。(a)為熱平衡狀態，(b)為“0”狀態寫入初期，(c)為“0”狀態寫入結束，(d)為“0”狀態保持之能帶圖。
以下，針對本發明之實施型態，參考圖面而予以說明。
圖1為表示本發明之EEPROM的剖面圖。本發明之 EEPROM與圖5所示之以往之EEPROM相同係由記憶本體部002和選擇記憶本體部002之選擇閘極電晶體部001構成。動作原理也與上述以往之EEPROM相同，不同之點係由本發明之浮動閘極係由第1浮動閘極016和第2浮動閘極017構成。該些浮動閘極假設係由多晶矽般之半導體構成，第1浮動閘極016和第2浮動閘極017之不同在於半導體之極性不同。其結果，在浮動閘極內，第1浮動閘極016和第2浮動閘極017形成PN接合。
圖2係例如將第1浮動閘極016設為n型半導體，將第2浮動閘極017設為p型半導體之時的沿著“1”狀態寫入時之圖1之線段A-A’的能帶圖。在圖2中，省略p型半導體基板006。圖中之E F、E C、E V分別表示費米能階、傳導帶之下端、價電子帶之上端。浮動閘極013係由第1浮動閘極016和第2浮動閘極017構成。控制閘極015係假設n型之半導體。
在圖2(a)所示之熱平衡狀態之記憶單元電晶體中，當將上述表示的“1”狀態寫入時之電壓狀態，即是n型隧道汲極區域009之電位設為GND，將控制閘極015之電位設為正時，成為圖2(b)所示之能帶圖，如圖2(b)之箭號所示般，電子018經由隧道絕緣膜010從n型隧道汲極區域009以FN電流機構被注入至第1浮動閘極016。
被注入電子018的第1浮動閘極016之電位如圖2(c)之空白箭號般下降(在圖中上升)，被施加於隧道 絕緣膜010之電位變弱，FN電流停止之同時，第1浮動閘極016和第2浮動閘極017間之內建電位減少，如圖2(d)所示般，第1浮動閘極016之傳導帶之電子朝向第2浮動閘極017之傳導帶流動。
流入第2浮動閘極017之傳導帶的電子018掉落至第2浮動閘極017之價電子帶(與電洞再結合)。其電子018係使第2浮動閘極017如圖2(d)之空白箭號表示般下降(在圖中上升)，減少的第1浮動閘極016和第2浮動閘極017間之內建電位回到原點，電子018從第1浮動閘極016之傳導帶朝向第2浮動閘極017之傳導帶的流入停止，成為安定狀態，“1”狀態寫入動作完成。即是，被儲存於浮動閘極017之“1”狀態的資訊藉由第2浮動閘極017之價電子帶的電洞減少現象(電子增加現象)而被記憶。
可以在資料保持狀態，即是如圖2(e)所示般使n型隧道汲極區域009和控制閘極015之電位成為GND之狀態下考慮此。由於與以往技術相同，電位被施加至電子018從第1浮動閘極016經由隧道絕緣膜010而朝向n型隧道汲極區域009洩漏的方向，故有第1浮動閘極016之傳導帶之電子018作為非意圖之電子洩漏002而逃逸至n型隧道汲極區域009的可能性，但是由於幾乎的“1”狀態之資訊被保持在第2浮動閘極017之價電子帶，故即使隧道絕緣膜010薄之時，亦能夠保持“1”狀態，不會成為保留不良。
接著，針對“0”狀態進行研討。在圖3(a)所示之熱平衡狀態之記憶單元電晶體中，當將上述表示的“0”狀態寫入電壓狀態，即是將控制閘極015之電位設為GND，將n型隧道汲極區域009之電位設為正時，成為圖3(b)般之能帶圖，如圖3(b)之箭號所示般，電子018經由隧道絕緣膜010從第1浮動閘極016以FN電流機構被注入至n型隧道汲極區域009。
排出電子018的第1浮動閘極016之電位如圖3(c)之空白箭號般上升(在圖中上下降)，被施加於隧道絕緣膜010之電位變弱，FN電流停止之同時，第1浮動閘極016和第2浮動閘極017間之內建電位增大，如圖3(c)所示般，第2浮動閘極017之價電子帶之電子018藉由齊納(Zener)機構或突崩機構朝向第1浮動閘極016之傳導帶流動(圖3(c)之箭號意象齊納機構)。
藉由其電子018之移動，如圖3(d)之空白箭號所示般，第1浮動閘極016之電位下降，第2浮動閘極017之電位上升，第1浮動閘極016和第2浮動閘極017間之內建電位回到原點，電子018藉由齊納機構或突崩機構從第2浮動閘極017之價電子帶流入第1浮動閘極016之傳導帶停止，成為安定狀態，“0”狀態寫入動作完成。即是，被儲存於浮動閘極017之“0”狀態的資訊藉由第2浮動閘極017之價電子帶的電洞增加現象而被記憶。
可以在資料保持狀態，即是如圖3(e)所示般使n型隧道汲極區域009和控制閘極015之電位成為GND之 狀態下考慮此。由於與以往技術相同，電位被施加至電子018從n型隧道汲極區域009經由隧道絕緣膜010而朝向第1浮動閘極016洩漏的方向，故有n型隧道汲極區域009之傳導帶之電子018作為非意圖之電子洩漏020而流入第1浮動閘極016的可能性，但是由於幾乎的“0”狀態之資訊被保持在第2浮動閘極017之價電子帶，故即使隧道絕緣膜010薄之時，亦能夠保持“0”狀態，不會成為保留不良。
如上述所示般，藉由本發明由於記憶體之資訊被記憶於不與隧道絕緣膜010直接接觸之第2浮動閘極017，故即使由於隧道絕緣膜010之薄膜化而使得非意圖之電子洩漏020增大，也難以產生保留不良。因此，能夠藉由隧道絕緣膜010之薄膜化使寫入電壓低電壓化，縮小晶片尺寸。
針對其他實施型態進行說明。為了取得上述效果，由於與隧道絕緣膜010接觸之浮動閘極僅有第1浮動閘極016，並且第1浮動閘極016若與第2浮動閘極017接觸即可，故即使如圖4所示般，第2浮動閘極017描繪成L字，成為第1浮動閘極016之上面與側面之一部分接觸而覆蓋的構造亦可。
再者，在上述例中，雖然將第1浮動閘極016設為n型半導體，將第2浮動閘極017設為p型半導體，但是即使將第1浮動閘極016設為p型半導體，將第2浮動閘極017設為n型半導體亦可以取得相同之效果。
而且，在上述中，雖然將浮動限定成極性不同的兩層半導體，即是在浮動閘極內具有一個接面的構造，但是即使設成3層以上之複數層(將接面設為兩個以上)亦可以取得相同之效果。

Claims (4)

  1. 一種半導體記憶裝置，具有：記憶單元電晶體源極區域，其係被形成在第1導電型之半導體基板的表層；記憶單元電晶體汲極區域，其係被形成與上述記憶單元電晶體源極區域間隔開；隧道汲極區域，其係被設置成在上述記憶單元電晶體源極區域和上述記憶單元電晶體汲極區域之間與上述記憶單元電晶體汲極區域接觸；隧道絕緣膜，其係被設置在上述隧道汲極區域之一部分的上述半導體基板上；閘極絕緣膜，其係被設置在上述隧道汲極區域之一部分和上述記憶單元電晶體源極區域之一部分和上述隧道汲極區域和上述記憶單元電晶體源極區域之間的上述半導體基板上；第1浮動閘極，其係隔著包含上述隧道絕緣膜之上述閘極絕緣膜而被形成在上述半導體基板上；第2浮動閘極，其係被設置成與上述第1浮動閘極接觸；及控制閘極，其係經絕緣膜被形成在上述第2浮動閘極上，藉由上述第2浮動閘極之價電子帶之電洞減少記憶電子經由上述隧道絕緣膜而被注入上述第1浮動閘極之情形，藉由上述第2浮動閘極之價電子帶之電洞增加記憶電子經由上述隧道絕緣膜而從上述第1浮動閘極被排出之情形。
  2. 如請求項1所記載之半導體記憶裝置，其中上述第1浮動閘極為N型之半導體，上述第2浮動閘極為P型之半導體，上述第1浮動閘極和上述第2浮動閘極形成PN接合。
  3. 如請求項1或2所記載之半導體記憶裝置，其中上述第1浮動閘極上面全部與上述第2浮動閘極接觸。
  4. 如請求項1或2所記載之半導體記憶裝置，其中上述第1浮動閘極上面和側面之一部分與上述第2浮動閘極接觸。
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