CN106129124B - 半导体存储装置 - Google Patents

半导体存储装置 Download PDF

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CN106129124B
CN106129124B CN201610298551.XA CN201610298551A CN106129124B CN 106129124 B CN106129124 B CN 106129124B CN 201610298551 A CN201610298551 A CN 201610298551A CN 106129124 B CN106129124 B CN 106129124B
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floating gate
insulating film
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tunnel insulating
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理崎智光
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Abstract

半导体存储装置。由半导体形成的浮栅由导电型的极性不同的第1浮栅和第2浮栅构成。通过所述第2浮栅的价电子带的空穴的减少来存储电子经由隧道绝缘膜而注入到所述第1浮栅的状态，通过所述第2浮栅的价电子带的空穴的增加来存储电子经由所述隧道绝缘膜而从所述第1浮栅排出的状态。

Description

半导体存储装置
技术领域
本发明涉及半导体存储装置。
背景技术
以EEPROM为例对现有的半导体存储装置进行说明。图5是示出现有的EEPROM的概念的截面图，是在专利文献1中公开的一般性结构。
构成EEPROM的单位单元由存储器主体部002和对存储器主体部002进行选择的选择栅晶体管部001构成。存储器主体部002中存在被称为浮栅013的蓄积电荷的电极。当在该浮栅013中蓄积了电子时，存储器主体部002成为阈值高的状态即增强，为“1”状态。当蓄积了空穴时成为阈值低的状态即耗尽，为“0”状态。
关于成为“1”状态的写入，对选择栅003和控制栅015施加正电压，使n型选择晶体管漏区域005、n型存储单元源极011和p型半导体衬底006的电位为GND，使电子经由隧道绝缘膜010而从n型隧道漏区域009注入到浮栅013。下面利用能带图关于成为“1”状态的写入进行说明。
图6是沿着图5的线段A－A’的能带图，示出成为“1”状态的写入时的状态变化。省略了p型半导体衬底006。图中的EF、EC、EV分别表示费米能级、导带的下端和价电子带的上端。在此，浮栅013和控制栅015假定为n型多晶硅。
在图6的(a)所示的热平衡状态的存储单元晶体管中，当将上述所示的“1”状态写入时的电压状态、即n型隧道漏区域009的电位设为GND、将控制栅015的电位设为正时，成为图6的(b)所示的能带图，如图6的(b)的箭头所示那样，电子018利用FN(Fowler-Nordheim)电流机制经由隧道绝缘膜010而从n型隧道漏区域009注入到浮栅013。被注入了电子018的浮栅013的电位如图6的(c)的空白箭头所示那样下降(在图中为上升)，当对隧道绝缘膜010施加的电位减弱而使得FN电流停止时，“1”状态的写入动作完成。
EEPROM是切断电源也能够保持信息的非易失性存储器，因此，如图6的(d)所示那样，一般而言必须具有在将n型隧道漏区域009和控制栅015的电位设为GND的状态下保持“1”状态几十年的能力。但是，如图6的(c)的空白箭头所示那样，由于注入到浮栅013的电子018，浮栅013的电位下降，因此成为数据保持状态，即在图6的(d)中隧道绝缘膜010被施加了注入到浮栅013的电子018经由隧道绝缘膜010而逃逸到n型隧道漏区域009的方向的电场的状态。在该状态下，在隧道绝缘膜010较薄的情况下或者老化的情况下，有时如图6的(d)所示那样产生不期望的电子泄漏020而引起数据保持不良。
接着，考虑“0”状态。关于成为“0”状态的写入，对选择栅003和n型选择晶体管漏区域005施加正电压，使控制栅015和p型半导体衬底006与GND连接，使n型存储单元晶体管源区域011为浮动状态，而将电子018从浮栅013经由隧道绝缘膜010而排出到n型隧道漏区域009。下面利用能带图对其进行说明。
图7示出“0”状态写入时的沿着图5的线段A－A’的能带图。与图6同样，省略了p型半导体衬底006，EF、EC、EV分别表示费米能级、导带的下端、价电子带的上端。并且，浮栅013和控制栅015假定为n型多晶硅。
在图7的(a)所示的热平衡状态的存储单元晶体管中，在上述所示的“0”状态写入电压状态时，即设控制栅015的电位为GND、n型隧道漏区域009的电位为正时，成为图7的(b)那样的能带图，如图7的(b)的箭头所示那样，电子018利用FN(Fowler-Nordheim)电流机制经由隧道绝缘膜010而从浮栅013排出到n型隧道漏区域009。电子018减少后的浮栅013的电位如图7的(c)的空白箭头所示那样上升，当施加给隧道绝缘膜010的电位减弱而使得FN电流停止时，“0”状态的写入动作完成。
EEPROM是切断电源也能够保持信息的非易失性存储器，因此，如图7的(d)所示那样，一般而言必须具有在将n型隧道漏区域009和控制栅015的电位设为GND的状态下保持“0”状态几十年的能力。但是，如图7的(c)的空白箭头所示那样，由于浮栅013的电子018的减少，浮栅013的电位上升，因此成为数据保持状态，即在图7的(d)中隧道绝缘膜010被施加了处于n型隧道漏区域009中的电子018经由隧道绝缘膜010而注入到浮栅013的方向的电场的状态。在该状态下，在隧道绝缘膜010较薄的情况下或者老化的情况下，有时如图7的(d)所示那样产生不期望的电子泄漏020而引起数据保持不良。
这样，非易失性存储器带有数据保持不良(保存不良)的问题。专利文献2是抑制上述保存不良的手法的发明。本发明通过降低隧道绝缘膜附近的浮栅内的杂质浓度来抑制隧道绝缘膜中的陷阱点(trap site)，抑制以陷阱点为成因的保存不良。
专利文献1：日本特开2004－071077号公报
专利文献2：日本特开平11－067940号公报
发明内容
但是，即使使用了专利文献1的手法，也并没有改变阻碍浮栅013内存在的电荷保持的方向的电场被施加于隧道绝缘膜010的情况，并没有根本改善利用图6和图7说明的保存不良。并且，作为抑制保存不良的另一手法，可以举出单纯增厚隧道绝缘膜010的手法，但这也没有根本改善利用图6和图7说明的保存不良。当增厚隧道绝缘膜010的膜厚时，相应地需要较高的写入电压，因此，作为结果产生芯片尺寸变大的问题。
即，换言之，这些改善手法不能在使成为数据保持障碍的不期望的电子泄漏020不流动的同时使隧道绝缘膜010薄膜化，可以说这成为写入电压低电压化和减小芯片尺寸的妨碍、成为非易失性存储器取得突破的妨碍。
为了解决上述课题，本发明利用了以下的手段。
一种半导体存储装置，其中，由半导体形成的浮栅由第1浮栅和第2浮栅构成，所述第1浮栅和所述第2浮栅的导电型的极性不同。
此外，一种半导体存储装置，其具有：存储单元晶体管源区域，其形成于第1导电型半导体衬底的表层；存储单元晶体管漏区域，其与所述存储单元晶体管源区域隔开而形成；隧道漏区域，其设置为在所述存储单元晶体管源区域与所述存储单元晶体管漏区域之间与所述存储单元晶体管漏区域接触；隧道绝缘膜，其设置在所述隧道漏区域的一部分的所述半导体衬底上；栅绝缘膜，其设置在所述隧道漏区域的一部分、所述存储单元晶体管源区域的一部分、以及所述隧道漏区域与所述存储单元晶体管源区域之间的所述半导体衬底上；第1浮栅，其隔着包含所述隧道绝缘膜的所述栅绝缘膜而形成在所述半导体衬底上；第2浮栅，其设置为与所述第1浮栅接触；以及控制栅，其隔着绝缘膜而形成在所述第2浮栅上。
因为抑制了数据保持状态下的泄漏电流，因此能够得到提高保存特性的效果。并且，因为还能够实现隧道绝缘膜厚的薄膜化，因此数据写入的低电压化成为可能，对芯片尺寸的缩小作出贡献。
附图说明
图1是示出本发明的EEPROM的截面图。
图2是示出本发明的EEPROM的图1的线段A-A’处的能带图，是用于说明“1”状态写入的图。(a)是热平衡状态的能带图，(b)是“1”状态写入初期的能带图，(c)是“1”状态写入结束的能带图，(d)和(e)是“1”状态保持的能带图。
图3是示出本发明的EEPROM的图1的线段A-A’处的能带图，是用于说明“0”状态写入的图。(a)是热平衡状态的能带图，(b)是“0”状态写入初期的能带图，(c)是“0”状态写入结束的能带图，(d)和(e)是“0”状态保持的能带图。
图4是示出本发明的EEPROM的截面图。
图5是示出现有的EEPROM的截面图。
图6是示出现有的EEPROM的图5的线段A-A’处的能带图，是用于说明“1”状态写入的图。(a)是热平衡状态的能带图，(b)是“1”状态写入初期的能带图，(c)是“1”状态写入结束的能带图，(d)是“1”状态保持的能带图。
图7是示出现有的EEPROM的图5的线段A-A’处的能带图，是用于说明“0”状态写入的图。(a)是热平衡状态的能带图，(b)是“0”状态写入初期的能带图，(c)是“0”状态写入结束的能带图，(d)是“0”状态保持的能带图。
标号说明
001：选择晶体管；002：存储单元晶体管；003：选择栅；004：选择栅绝缘膜；005：n型选择晶体管漏区域；006：p型半导体衬底；007：n型区域；008：n型选择晶体管源区域(n型存储单元晶体管漏区域)；009：n型隧道漏区域；010：隧道绝缘膜；011：n型存储单元晶体管源区域；012：存储单元栅绝缘膜；013：浮栅；014：浮动/控制栅间绝缘膜；015：控制栅；016：第1浮栅；017：第2浮栅；018：电子；019：空穴；020：不期望的电子泄漏。
具体实施方式
下面，参照附图对本发明的实施方式进行说明。
图1是示出本发明的EEPROM的截面图。本发明的EEPROM与图5所示的现有的EEPROM同样地，由存储器主体部002和对存储器主体部002进行选择的选择栅晶体管部001构成。工作原理也与上述现有的EEPROM相同，不同之处在于，本发明的浮栅由第1浮栅016和第2浮栅017构成。假定这些浮栅由多晶硅那样的半导体构成，第1浮栅016与第2浮栅017的不同之处在于半导体的极性不同。其结果是，在浮栅内，第1浮栅016和第2浮栅017形成PN结。
图2是例如设第1浮栅016为n型半导体、第2浮栅017为p型半导体时的、“1”状态写入时的沿图1的线段A-A’处的能带图。图2中省略了p型半导体衬底006。图中的EF、EC、EV分别表示费米能级、导带的下端、价电子带的上端。浮栅013由第1浮栅016和第2浮栅017构成。控制栅015假定为n型半导体。
在图2的(a)所示的热平衡状态的存储单元晶体管中，在上述所示的“1”状态写入电压状态时，即设n型隧道漏区域009的电位为GND、控制栅015的电位为正时，成为图2的(b)所示那样的能带图，如图2的(b)的箭头所示那样，利用FN电流机制，电子018经由隧道绝缘膜010而从n型隧道漏区域009注入到第1浮栅016。
被注入电子018的第1浮栅016的电位如图2的(c)的空白箭头所示那样下降(在图中为上升)，施加给隧道绝缘膜010的电位减弱而使得FN电流停止，与此同时，第1浮栅016与第2浮栅017之间的内建电势(built-in potential)减小，如图2的(d)所示，第1浮栅016的导带的电子018流向第2浮栅017的导带。
流入第2浮栅017的导带的电子018落入第2浮栅017的价电子带(与空穴复合)。该电子018使第2浮栅017的电位如图2的(d)的空白箭头所示那样下降(在图中为上升)，第1浮栅016与第2浮栅017之间的减小后的内建电势恢复原样，电子018的从第1浮栅016的导带向第2浮栅017的导带的流入停止，成为稳定状态，完成“1”状态写入动作。即，蓄积在浮栅017中的“1”状态的信息通过第2浮栅017的价电子带的空穴减少现象(电子增加现象)而被存储。
在数据保持状态、即如图2的(e)所示那样将n型隧道漏区域009和控制栅015的电位设为GND的状态下对其进行考虑。与现有技术同样地，被施加了电子018经由隧道绝缘膜010而从第1浮栅016向n型隧道漏区域009进行泄漏的方向的电位，因此存在第1浮栅016的导带的电子018作为不期望的电子泄漏020而向n型隧道漏区域009逃逸的可能性，但绝大多数的“1”状态的信息被保持在第2浮栅017的价电子带，因此即使在隧道绝缘膜010较薄的情况下也能保持“1”状态，不会成为保存不良。
接着，对“0”状态写入时进行考虑。在图3的(a)所示的热平衡状态的存储单元晶体管中，在“0”状态写入电压状态时，即设控制栅015的电位为GND、n型隧道漏区域009的电位为正时，成为图3的(b)所示的能带图，如图3的(b)的箭头所示那样，利用FN电流机制，电子018经由隧道绝缘膜010而从第1浮栅016排出到n型隧道漏区域009。
排出了电子018的第1浮栅016的电位如图3(c)的空白箭头所示那样上升(在图中为下降)，施加给隧道绝缘膜010的电位减弱而使得FN电流停止，与此同时，第1浮栅016与第2浮栅017之间的内建电势增大，如图3的(c)所示，第2浮栅017的价电子带的电子018通过齐纳机制或雪崩机制流向第1浮栅016的导带(图3的(c)的箭头示意性示出齐纳机制)。
通过该电子018的移动，如图3的(d)的空白箭头所示那样，第1浮栅016的电位下降，第2浮栅017的电位上升，第1浮栅016与第2浮栅017之间的内建电势恢复原样，由齐纳机制或雪崩机制导致的、电子018从第2浮栅017的价电子带向第1浮栅016的导带的流入停止，成为稳定状态，完成“0”状态写入动作。即，蓄积在浮栅017中的“0”状态的信息通过第2浮栅017的价电子带的空穴增加现象而被存储。
在数据保持状态、即如图3的(e)所示那样将n型隧道漏区域009和控制栅015的电位设为GND的状态下对其进行考虑。与现有技术同样地，被施加了电子018经由隧道绝缘膜010从n型隧道漏区域009向第1浮栅016进行泄漏的方向的电位，因此存在n型隧道漏区域009的导带的电子018作为不期望的电子泄漏020而流入第1浮栅016的可能性，但绝大多数的“0”状态的信息被保持在第2浮栅017的价电子带，因此即使在隧道绝缘膜010较薄的情况下也能够保持“0”状态，不会成为保存不良。
如上所示，根据本发明，存储器的信息被存储在不与隧道绝缘膜010直接接触的第2浮栅017中，因此即使由于隧道绝缘膜010的薄膜化而使得不期望的电子泄漏020增大，也不易产生保存不良。因此，能够实现隧道绝缘膜010的薄膜化带来的写入电压的低电压化，且能够减小芯片尺寸。
对其它实施方式进行说明。为了得到上述效果，使与隧道绝缘膜010接触的浮栅仅为第1浮栅016且使第1浮栅016与第2浮栅017接触即可，因此，也可以如图4所示，使第2浮栅017形成L状，构成为接触并覆盖第1浮栅016的上表面和侧面的一部分的结构。
另外，在上述示例中，设为第1浮栅016为n型半导体、第2浮栅017为p型半导体，但将第1浮栅016设为p型半导体、第2浮栅017设为n型半导体，也能够得到同样的效果。
另外，在上文中，将浮栅限定为是极性不同的两层的半导体，即限定为浮栅内具有一个结(junction)的结构，但设为三层以上的多层(结为2个以上)也能够得到同样的效果。

Claims (6)

1.一种半导体存储装置，其具有：
隧道绝缘膜；以及
浮栅，其具有与所述隧道绝缘膜相接的第1浮栅和与所述第1浮栅相接的第2浮栅，
在该半导体存储装置中，
通过所述第2浮栅的价电子带的空穴的减少来存储电子经由所述隧道绝缘膜而注入到所述第1浮栅的状态，
通过所述第2浮栅的价电子带的空穴的增加来存储电子经由所述隧道绝缘膜而从所述第1浮栅排出的状态，
所述第1浮栅的上表面和侧面的一部分与所述第2浮栅接触，并且在所述第1浮栅和所述第2浮栅中，仅所述第1浮栅与所述隧道绝缘膜接触。
2.根据权利要求1所述的半导体存储装置，其中，
所述第1浮栅是N型半导体，所述第2浮栅是P型半导体，所述第1浮栅和所述第2浮栅形成PN结。
3.根据权利要求1或2所述的半导体存储装置，其中，
所述第1浮栅的上表面全部与所述第2浮栅接触。
4.一种半导体存储装置，其具有：
存储单元晶体管源区域，其形成于第1导电型半导体衬底的表层；
存储单元晶体管漏区域，其与所述存储单元晶体管源区域隔开而形成；
隧道漏区域，其设置为在所述存储单元晶体管源区域与所述存储单元晶体管漏区域之间与所述存储单元晶体管漏区域接触；
隧道绝缘膜，其设置在所述隧道漏区域的一部分的所述半导体衬底上；
栅绝缘膜，其设置在所述隧道漏区域的一部分、所述存储单元晶体管源区域的一部分、以及所述隧道漏区域与所述存储单元晶体管源区域之间的所述半导体衬底上；
第1浮栅，其隔着包含所述隧道绝缘膜的所述栅绝缘膜而形成在所述半导体衬底上；
第2浮栅，其设置为与所述第1浮栅接触；以及
控制栅，其隔着绝缘膜而形成在所述第2浮栅上，
通过所述第2浮栅的价电子带的空穴的减少来存储电子经由所述隧道绝缘膜而注入到所述第1浮栅的状态，
通过所述第2浮栅的价电子带的空穴的增加来存储电子经由所述隧道绝缘膜而从所述第1浮栅排出的状态，
所述第1浮栅的上表面和侧面的一部分与所述第2浮栅接触，并且在所述第1浮栅和所述第2浮栅中，仅所述第1浮栅与所述隧道绝缘膜接触。
5.根据权利要求4所述的半导体存储装置，其中，
所述第1浮栅是N型半导体，所述第2浮栅是P型半导体，所述第1浮栅和所述第2浮栅形成PN结。
6.根据权利要求4或5所述的半导体存储装置，其中，
所述第1浮栅的上表面全部与所述第2浮栅接触。
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