TWI659417B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI659417B
TWI659417B TW106146166A TW106146166A TWI659417B TW I659417 B TWI659417 B TW I659417B TW 106146166 A TW106146166 A TW 106146166A TW 106146166 A TW106146166 A TW 106146166A TW I659417 B TWI659417 B TW I659417B
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Taiwan
Prior art keywords
memory
chip
memory chip
logic
front surface
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TW106146166A
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English (en)
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TW201916029A (zh
Inventor
築山慧至
栗田洋一郎
青木秀夫
河崎一茂
Original Assignee
日商東芝記憶體股份有限公司
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Publication of TW201916029A publication Critical patent/TW201916029A/zh
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Publication of TWI659417B publication Critical patent/TWI659417B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

本發明提供一種可抑制誤動作及可靠性之降低之半導體裝置。 實施形態之半導體裝置具備：第1記憶體晶片，其具有第1正面及第1背面，於第1正面側設置有第1記憶體電路；第2記憶體晶片，其具有第2正面及與第1正面相向之第2背面，於第2正面側設置有第2記憶體電路，與第1記憶體晶片電性連接；以及邏輯晶片，其與第2記憶體晶片之間設置有第1記憶體晶片，具有第3正面及第3背面，於第3正面側設置有邏輯電路，與第1記憶體晶片電性連接。

Description

半導體裝置
本發明之實施形態係關於一種半導體裝置。
具有一種半導體記憶體，其將多個記憶體晶片積層並收納至一個封裝體內。藉由將複數個記憶體晶片積層並收納至一個封裝體內，實現半導體記憶體之大容量化、高速化、低耗電化。為了使半導體記憶體進一步高功能化，除複數個記憶體晶片以外，考慮將邏輯晶片亦收納至一個封裝體內。 但是，邏輯晶片動作時之發熱量與記憶體晶片相比較大。因此，有因邏輯晶片之發熱而導致記憶體晶片誤動作、或記憶體晶片之可靠性降低之虞。
本發明提供一種可抑制誤動作及可靠性之降低之半導體裝置。 實施形態之半導體裝置具備：第1記憶體晶片，其具有第1正面及第1背面，於上述第1正面側設置有第1記憶體電路；第2記憶體晶片，其具有第2正面及與上述第1正面相向之第2背面，於上述第2正面側設置有第2記憶體電路，與上述第1記憶體晶片電性連接；以及邏輯晶片，其與上述第2記憶體晶片之間設置有上述第1記憶體晶片，具有第3正面及第3背面，於上述第3正面側設置有邏輯電路，與上述第1記憶體晶片電性連接。
以下，一面參照圖式一面對本發明之實施形態進行說明。再者，於以下之說明中，對相同或類似之構件標註相同之符號，對於一度說明之構件等適當省略其說明。 又，於本說明書中，有時為方便起見而使用「上」或「下」之類的用語。「上」或「下」只不過係表示圖式內之相向位置關係之用語，並非為規定相對於重力之位置關係之用語。 以下，參照圖式對實施形態之半導體裝置進行說明。 (第1實施形態) 第1實施形態之半導體裝置具備：第1記憶體晶片，其具有第1正面及第1背面，於第1正面側設置有第1記憶體電路；第2記憶體晶片，其具有第2正面及與第1正面相向之第2背面，於第2正面側設置有第2記憶體電路，與第1記憶體晶片電性連接；以及邏輯晶片，其於與第2記憶體晶片之間設置有第1記憶體晶片，具有第3正面及第3背面，於第3正面側設置有邏輯電路，與第1記憶體晶片電性連接。 圖1係第1實施形態之半導體裝置之模式剖視圖。第1實施形態之半導體裝置為半導體記憶體100。 半導體記憶體100具備第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14、邏輯晶片15、再配線層(RDL，Redistribution Layer)20(配線體)、密封樹脂22(第1樹脂)、間隔樹脂24(第2樹脂)、TSV(Through Silicon Via，矽穿孔)26、微凸塊28、連接端子30、外部端子32。 半導體記憶體100係利用使用半導體製造程序所製造之再配線層20將第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14連接於外部端子32之FO-WLP(Fan Out Wafer Level Package，扇出型晶圓級封裝體)。 第1記憶體晶片11具有正面11a(第1正面)、背面11b(第1背面)、記憶體電路11c(第1記憶體電路)。背面11b位於正面11a之相反側。第1記憶體晶片11例如使用單晶矽而製造。 記憶體電路11c設置於第1記憶體晶片11之正面11a側。記憶體電路11c包含例如電晶體、記憶胞、金屬配線。 第2記憶體晶片12設置於第1記憶體晶片11之上。第2記憶體晶片12具有正面12a(第2正面)、背面12b(第2背面)、記憶體電路12c(第2記憶體電路)。第2記憶體晶片12之背面12b位於第2記憶體晶片12之正面12a之相反側。第2記憶體晶片12之背面12b與第1記憶體晶片11之正面11a相向。第2記憶體晶片12例如使用單晶矽而製造。 記憶體電路12c(第2記憶體電路)設置於第2記憶體晶片12之正面12a側。記憶體電路12c包含例如電晶體、記憶胞、金屬配線。第2記憶體晶片12具有與第1記憶體晶片11相同之構成。 第3記憶體晶片13設置於第2記憶體晶片12之上。第4記憶體晶片14設置於第3記憶體晶片13之上。第3記憶體晶片13及第4記憶體晶片14具有與第1記憶體晶片11相同之構成。 第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14具有記憶資料之功能。第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14例如為NAND(Not AND，反及)型快閃記憶體。 第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14於內部具有TSV26。又，於第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14之各者之間設置有微凸塊28。 第1記憶體晶片11與第2記憶體晶片12、第2記憶體晶片12與第3記憶體晶片13、第3記憶體晶片13與第4記憶體晶片14係使用TSV26及微凸塊28電性連接。 邏輯晶片15設置於第1記憶體晶片11之下。於邏輯晶片15與第2記憶體晶片12之間設置有第1記憶體晶片11。邏輯晶片15與第1記憶體晶片11之背面11b相向。 邏輯晶片15具有正面15a(第3正面)、背面15b(第3背面)、邏輯電路15c。邏輯晶片15之背面15b位於正面15a之相反側。邏輯晶片15例如使用單晶矽而製造。 邏輯電路15c設置於邏輯晶片15之正面15a側。邏輯電路15c包含例如電晶體、金屬配線。 邏輯晶片15具備運算功能。邏輯晶片15例如為介面晶片。 再配線層20設置於邏輯晶片15與第1記憶體晶片11之間。再配線層20具有正面20a(第4正面)、背面20b(第4背面)、第1金屬配線20c、第2金屬配線20d(配線)、樹脂層20e。再配線層20之背面20b與邏輯晶片15相向。 第1金屬配線20c與第2金屬配線20d設置於樹脂層20e中。樹脂層20e例如為聚醯亞胺。 再配線層20為具有第1金屬配線20c及第2金屬配線20d之2層配線層之多層配線構造。再配線層20可為配線層為1層之單層配線構造，亦可為配線層為3層以上之多層配線構造。 再配線層20之寬度(圖1中之w1)大於第1記憶體晶片11之寬度(圖1中之w2)。再配線層20之面積大於第1記憶體晶片之面積。 再配線層20將邏輯晶片15與第1記憶體晶片11電性連接。又，再配線層20將第1記憶體晶片11與外部端子32電性連接。 連接端子30將邏輯晶片15與再配線層20電性連接。連接端子30電性連接於第2金屬配線20d。連接端子30例如為微凸塊。 外部端子32設置於再配線層20之背面20b側。外部端子32電性連接於第2金屬配線20d。外部端子32例如為焊料球。 外部端子32與連接端子30由第2金屬配線20d電性連接。外部端子32與連接端子30例如不經由位於較第2金屬配線20d更靠再配線層20之正面20a側之導體而電性連接。例如外部端子32與連接端子30不經由第1金屬配線20c而連接。外部端子32與連接端子30例如於再配線層20中僅利用最靠近再配線層20之背面20b之金屬配線連接。外部端子32與連接端子30例如於再配線層20中僅利用最靠近邏輯晶片15之金屬配線連接。 密封樹脂22覆蓋第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14。密封樹脂22亦設置於再配線層20與第1記憶體晶片11之間。又，密封樹脂22亦設置於第1記憶體晶片11與第2記憶體晶片12之間、第2記憶體晶片12與第3記憶體晶片13之間、第3記憶體晶片13與第4記憶體晶片14之間。 密封樹脂22具有保護第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14之功能。密封樹脂22例如以環氧樹脂作為主成分。密封樹脂22中例如含有填料。填料例如為二氧化矽粒子。 間隔樹脂24於再配線層20與第1記憶體晶片11之間設置複數個。間隔樹脂24亦於第1記憶體晶片11與第2記憶體晶片12之間、第2記憶體晶片12與第3記憶體晶片13之間、第3記憶體晶片13與第4記憶體晶片14之間設置複數個。間隔樹脂24與密封樹脂22不同。間隔樹脂24例如較佳為由聚醯亞胺樹脂、酚樹脂、環氧樹脂、BCB(苯并環丁烯)樹脂等形成。間隔樹脂24中例如不含填料。 於製造半導體記憶體100之過程中，於將第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14依序積層於再配線層20之上時，間隔樹脂24係作為用以確保晶片間距離之間隔件發揮功能。再者，作為接著第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14各者之接著劑發揮功能。 於隔著間隔樹脂24而積層第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14後，使用密封樹脂22將第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14密封。藉由使用間隔樹脂24，簡化半導體記憶體100之製造程序。 接下來，對第1實施形態之半導體裝置之作用及效果進行說明。 圖2係比較例之半導體裝置之模式剖視圖。比較例之半導體裝置為半導體記憶體900。 半導體記憶體900具備第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14、邏輯晶片15、矽中介層21、密封樹脂22、底部填充樹脂25、TSV26、微凸塊28、凸塊29、連接端子30、外部端子32。 半導體記憶體900係使用矽中介層21將第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14連接於外部端子32之封裝體。例如使用凸塊29、矽中介層21內之TSV21a，將第1記憶體晶片11電性連接於外部端子32。 第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14、邏輯晶片15各自之構成與第1實施形態相同。 於半導體記憶體900中，與第1實施形態之半導體記憶體100不同，邏輯晶片15與第1記憶體晶片11之正面11a相向。邏輯晶片15之邏輯電路15c與第1記憶體晶片11之記憶體電路11c相向。 又，與第1實施形態不同，以第2記憶體晶片12之正面12a與第1記憶體晶片11之背面11b相向之方式積層第1記憶體晶片11與第2記憶體晶片12。因此，第2記憶體晶片12之記憶體電路12c存在於第2記憶體晶片12之靠近邏輯晶片15之側。 又，與第1實施形態不同，邏輯晶片15設置於作為配線體之矽中介層21與第1記憶體晶片11之間。於邏輯晶片15與矽中介層21之間設置底部填充樹脂25。 又，與第1實施形態不同，設置於邏輯晶片15與第1記憶體晶片11之間、第1記憶體晶片11與第2記憶體晶片12之間、第2記憶體晶片12與第3記憶體晶片13之間、第3記憶體晶片13與第4記憶體晶片14之間之樹脂僅為密封樹脂22。不使用間隔樹脂24。 於半導體記憶體900中，藉由將複數個記憶體晶片、即第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14收納至一個封裝體內，實現半導體記憶體900之大容量化、高速化、低耗電化。而且，藉由將邏輯晶片15收納至相同之封裝體內，實現半導體記憶體900之高功能化。 但是，邏輯晶片15動作時之發熱量與記憶體晶片相比較大。因此，有因邏輯晶片15之發熱而導致記憶體晶片發生誤動作、或記憶體晶片之可靠性降低之虞。於半導體記憶體900中，尤其對接近邏輯晶片15之第1記憶體晶片11或第2記憶體晶片12之影響成為問題。 於第1實施形態之半導體記憶體100中，與半導體記憶體900不同，邏輯晶片15與第1記憶體晶片11之背面11b相向。換言之，邏輯晶片15與第1記憶體晶片11之記憶體電路11c不相向。因此，可使邏輯晶片15與第1記憶體晶片11之記憶體電路11c之距離較半導體記憶體900變長。 又，於第1實施形態之半導體記憶體100中，與半導體記憶體900不同，以第2記憶體晶片12之背面12b與第1記憶體晶片11之正面11a相向之方式積層第1記憶體晶片11與第2記憶體晶片12。因此，第2記憶體晶片12之記憶體電路12c存在於第2記憶體晶片12之遠離邏輯晶片15之側。 因此，於第1實施形態之半導體記憶體100中，可使邏輯晶片15與第1記憶體晶片11之記憶體電路11c之距離、及邏輯晶片15與第2記憶體晶片12之記憶體電路12c之距離變長。因此，可抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 於第1實施形態之半導體記憶體100中，於邏輯晶片15與第1記憶體晶片11之間設置有再配線層20。因此，可使邏輯晶片15與第1記憶體晶片11之記憶體電路11c之距離、及邏輯晶片15與第2記憶體晶片12之記憶體電路12c之距離進一步變長。藉此，可進一步抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 尤其，藉由使用含有導熱率低於矽等半導體之樹脂層20e之再配線層20作為配線體，邏輯晶片15與第1記憶體晶片11及第2記憶體晶片12之間之隔熱性提高。因此，可減少自邏輯晶片15傳遞至第1記憶體晶片11及第2記憶體晶片12之熱量。 又，於第1實施形態之半導體記憶體100中，較佳為連接外部端子32與邏輯晶片15之連接端子30不經由位於較第2金屬配線20d更靠再配線層20之正面20a側之導體而電性連接。較佳為外部端子32與連接端子30於再配線層20中僅藉由最靠近再配線層20之背面20b之金屬配線連接。藉由該構成，使用導熱率高之金屬配線將邏輯晶片15之熱以較短路徑傳遞至外部端子32。因此，減少自邏輯晶片15傳遞至第1記憶體晶片11及第2記憶體晶片12之熱量。藉此，可進一步降低伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 又，於第1實施形態之半導體記憶體100中，較佳為密封樹脂22中所含之填料之體積比率大於間隔樹脂24中所含之填料之體積比率。又，更佳為密封樹脂22含有填料，間隔樹脂24不含填料。藉由使密封樹脂22含有填料，密封樹脂22之強度提高，另一方面，藉由導熱率高之填料，密封樹脂22整體之導熱率提高。 藉由於邏輯晶片15與第1記憶體晶片11之間、及第1記憶體晶片11與第2記憶體晶片12之間局部地設置不含填料之間隔樹脂24，邏輯晶片15與第1記憶體晶片11之間、及第1記憶體晶片11與第2記憶體晶片12之間之隔熱性提高。因此，減少自邏輯晶片15傳遞至第1記憶體晶片11及第2記憶體晶片12之熱量。藉此，可進一步抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 以上，根據第1實施形態之半導體記憶體100，可抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 (第2實施形態) 第2實施形態之半導體裝置於第1記憶體晶片之第1背面與邏輯晶片之第3背面相向之方面，與第1實施形態不同。以下，關於與第1實施形態重複之內容省略一部分記述。 圖3係第2實施形態之半導體裝置之模式剖視圖。第2實施形態之半導體裝置為半導體記憶體200。 半導體記憶體200具備第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14、邏輯晶片15、TSV16(貫通電極)、再配線層20(配線體)、密封樹脂22(第1樹脂)、間隔樹脂24(第2樹脂)、TSV26、微凸塊28、連接端子30、外部端子32。 半導體記憶體200係利用使用半導體製造程序所製造之再配線層20將第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14連接於外部端子32之FO-WLP。 第1記憶體晶片11具有正面11a(第1正面)、背面11b(第1背面)、記憶體電路11c。邏輯晶片15具有正面15a(第3正面)、背面15b(第3背面)、邏輯電路15c。 第1記憶體晶片11之背面11b與邏輯晶片15之背面15b相向。換言之，再配線層20之背面20b與邏輯晶片15之背面15b相向。 於邏輯晶片15內設置有TSV16。使用TSV16、連接端子30、再配線層20、微凸塊28將邏輯晶片15之邏輯電路15c與第1記憶體晶片11電性連接。 於第2實施形態之半導體記憶體200中，可使邏輯晶片15之邏輯電路15c與第1記憶體晶片11之記憶體電路11c之距離較第1實施形態之半導體記憶體100變長。藉此，可進一步抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 以上，根據第2實施形態之半導體記憶體200，與第1實施形態之半導體記憶體100相比，可進一步抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 (第3實施形態) 第3實施形態之半導體裝置於第1記憶體晶片之第1正面與第2記憶體晶片之第2正面相向之方面，與第1實施形態相同。以下，關於與第1實施形態重複之內容省略一部分記述。 圖4係第3實施形態之半導體裝置之模式剖視圖。第3實施形態之半導體裝置為半導體記憶體300。 半導體記憶體300具備第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14、邏輯晶片15、再配線層20(配線體)、密封樹脂22(第1樹脂)、間隔樹脂24(第2樹脂)、TSV26、微凸塊28、連接端子30、外部端子32。 半導體記憶體300係以使用半導體製造程序而製造之再配線層20將第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14連接於外部端子32之FO-WLP。 第1記憶體晶片11具有正面11a(第1正面)、背面11b(第1背面)、記憶體電路11c(第1記憶體電路)。第2記憶體晶片12具有正面12a(第2正面)、背面12b(第2背面)、記憶體電路12c(第2記憶體電路)。 第1記憶體晶片11之正面11a與第2記憶體晶片12之正面12a相向接合。換言之，第1記憶體晶片11之記憶體電路11c與第2記憶體晶片12之記憶體電路12c相向接合。 就半導體記憶體之高速化及低耗電化之觀點而言，較佳為減薄記憶體晶片之厚度而降低TSV之寄生電容。但是，以晶圓級形成TSV時，若晶圓變得過薄則難以操作。 於半導體記憶體300中，於製造TSV時，將包含第1記憶體晶片11之晶圓與包含第2記憶體晶片12之晶圓貼合而製造。因此，可確保TSV形成時之晶圓強度，並且減薄第1記憶體晶片11與第2記憶體晶片12之厚度。因此，可降低TSV之寄生電容，實現半導體記憶體300之高速化及低耗電化。 以上，根據第3實施形態之半導體記憶體300，可抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。進而，可實現高速化及低耗電化。 (第4實施形態) 第4實施形態之半導體裝置於第1記憶體晶片之第1正面與第2記憶體晶片之第2背面相向之方面，與比較例不同。以下，對於與比較例及第1實施形態重複之內容省略一部分記述。 圖5係第4實施形態之半導體裝置之模式剖視圖。第4實施形態之半導體裝置為半導體記憶體400。 半導體記憶體400具備第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14、邏輯晶片15、矽中介層21、密封樹脂22(第1樹脂)、間隔樹脂24(第2樹脂)、TSV26、微凸塊28、凸塊29、連接端子30、外部端子32。 半導體記憶體400係使用矽中介層21將第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14連接於外部端子32之封裝體。例如使用凸塊29、矽中介層21內之TSV21a，將第1記憶體晶片11電性連接於外部端子32。 於半導體記憶體400中，與比較例之半導體記憶體900不同，邏輯晶片15與第1記憶體晶片11之背面11b相向。換言之，邏輯晶片15與第1記憶體晶片11之記憶體電路11c不相向。因此，可使邏輯晶片15與第1記憶體晶片11之記憶體電路11c之距離較半導體記憶體900為長。 又，於第4實施形態之半導體記憶體400中，與半導體記憶體900不同，以第2記憶體晶片12之背面12b與第1記憶體晶片11之正面11a相向之方式積層第1記憶體晶片11與第2記憶體晶片12。因此，第2記憶體晶片12之記憶體電路12c存在於第2記憶體晶片12之遠離邏輯晶片15之一側。 因此，於第4實施形態之半導體記憶體400中，可使邏輯晶片15與第1記憶體晶片11之記憶體電路11c之距離、及邏輯晶片15與第2記憶體晶片12之記憶體電路12c之距離變長。藉此，可抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 以上，根據第4實施形態之半導體記憶體400，與比較例之半導體記憶體900相比，可抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 (第5實施形態) 第5實施形態之半導體裝置於邏輯晶片之第3背面與第1記憶體晶片相向之方面與第4實施形態不同。以下，關於與第4實施形態重複之內容省略一部分記述。 圖6係第5實施形態之半導體裝置之模式剖視圖。第5實施形態之半導體裝置為半導體記憶體500。 半導體記憶體500具備第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14、邏輯晶片15、TSV16、矽中介層21、密封樹脂22(第1樹脂)、間隔樹脂24(第2樹脂)、TSV26、微凸塊28、凸塊29、連接端子30、外部端子32。 半導體記憶體500係使用矽中介層21將第1記憶體晶片11、第2記憶體晶片12、第3記憶體晶片13、第4記憶體晶片14連接於外部端子32之封裝體。例如使用凸塊29、矽中介層21內之TSV21a，第1記憶體晶片11被電性連接於外部端子32。 於邏輯晶片15內設置有TSV16。使用TSV16、連接端子30將邏輯晶片15之邏輯電路15c與第1記憶體晶片11電性連接。 於半導體記憶體500中，與第4實施形態之半導體記憶體400不同，邏輯晶片15之背面15b與第1記憶體晶片11相向。邏輯晶片15之邏輯電路15c與第1記憶體晶片11之記憶體電路11c不相向。因此，可使邏輯晶片15之邏輯電路15c與第1記憶體晶片11之記憶體電路11c之距離較半導體記憶體400變長。同樣地，可使邏輯晶片15之邏輯電路15c與第2記憶體晶片12之記憶體電路12c之距離較半導體記憶體400變長。 於第5實施形態之半導體記憶體500中，可使邏輯晶片15之邏輯電路15c與第1記憶體晶片11之記憶體電路11c之距離、及邏輯晶片15之邏輯電路15c與第2記憶體晶片12之記憶體電路12c之距離變長。藉此，可抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 以上，根據第5實施形態之半導體記憶體500，可抑制伴隨著邏輯晶片15之發熱之記憶體晶片之誤動作及可靠性之降低。 於第1至第5實施形態中，作為配線體，以再配線層20及矽中介層21為例進行了說明，但配線體並不限定於該兩例。作為配線體，例如亦可應用使用玻璃環氧樹脂之封裝基板。 於第1至第5實施形態中，以積層4個記憶體晶片之情形為例進行了說明，但積層之記憶體晶片之數量亦可為2個或3個或5個以上。 以上，對本發明之若干種實施形態進行了說明，但該等實施形態係作為示例提出，並非意圖限定發明之範圍。該等新穎之實施形態可藉由其他各種形態而實施，可於不脫離發明主旨之範圍內進行各種省略、替換、變更。例如亦可將一實施形態之構成要素替換或變更為其他實施形態之構成要素。該等實施形態或其變化包含於發明之範圍或主旨內，並且包含於申請專利範圍所記載之發明及其均等之範圍內。 [相關申請案] 本申請案享有將日本專利申請案2017-179328號(申請日：2017年9月19日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
11 第1記憶體晶片 11a 正面(第1正面) 11b 背面(第1背面) 11c 記憶體電路(第1記憶體電路) 12 第2記憶體晶片 12a 正面(第2正面) 12b 背面(第2背面) 12c 記憶體電路(第2記憶體電路) 13 第3記憶體晶片 14 第4記憶體晶片 15 邏輯晶片 15a 正面(第3正面) 15b 背面(第3背面) 15c 邏輯電路 16 TSV(貫通電極) 20 再配線層(配線體) 20a 正面(第4正面) 20b 背面(第4背面) 20c 第1金屬配線 20d 第2金屬配線(配線) 20e 樹脂層 21 矽中介層(配線體) 21a TSV 22 密封樹脂(第1樹脂) 24 間隔樹脂(第2樹脂) 25 底部填充樹脂 26 TSV 28 微凸塊 29 凸塊 30 連接端子 32 外部端子 100 半導體記憶體(半導體裝置) 200 半導體記憶體(半導體裝置) 300 半導體記憶體(半導體裝置) 400 半導體記憶體(半導體裝置) 500 半導體記憶體(半導體裝置) 900 半導體記憶體 w1 寬度 w2 寬度
圖1係第1實施形態之半導體裝置之模式剖視圖。 圖2係比較例之半導體裝置之模式剖視圖。 圖3係第2實施形態之半導體裝置之模式剖視圖。 圖4係第3實施形態之半導體裝置之模式剖視圖。 圖5係第4實施形態之半導體裝置之模式剖視圖。 圖6係第5實施形態之半導體裝置之模式剖視圖。

Claims (9)

  1. 一種半導體裝置，其具備： 第1記憶體晶片，其具有第1正面及第1背面，於上述第1正面側設置有第1記憶體電路； 第2記憶體晶片，其具有第2正面及與上述第1正面相向之第2背面，於上述第2正面側設置有第2記憶體電路，與上述第1記憶體晶片電性連接；以及 邏輯晶片，其與上述第2記憶體晶片之間設置有上述第1記憶體晶片，具有第3正面及第3背面，於上述第3正面側設置有邏輯電路，與上述第1記憶體晶片電性連接。
  2. 如請求項1之半導體裝置，其中進而具備配線體，該配線體具有第4正面及第4背面，設置於上述邏輯晶片與上述第1記憶體晶片之間，上述第4背面與上述邏輯晶片相向，寬度大於上述第1記憶體晶片，且具有配線，將上述第1記憶體晶片與上述邏輯晶片電性連接。
  3. 如請求項2之半導體裝置，其中上述配線體具有樹脂層，上述配線設置於上述樹脂層之中。
  4. 一種半導體裝置，其具備： 第1記憶體晶片，其具有第1正面及第1背面，於上述第1正面側設置有第1記憶體電路； 第2記憶體晶片，其具有第2正面及第2背面，於上述第2正面側設置有第2記憶體電路，與上述第1正面相向，與上述第1記憶體晶片電性連接；以及 邏輯晶片，其與上述第2記憶體晶片之間設置有上述第1記憶體晶片，具有第3正面及第3背面，於上述第3正面側設置有邏輯電路，上述第1背面與上述第3背面相向，與上述第1記憶體晶片電性連接。
  5. 如請求項4之半導體裝置，其中進而具備配線體，該配線體具有第4正面及第4背面，設置於上述邏輯晶片與上述第1記憶體晶片之間，上述第4背面與上述邏輯晶片相向，寬度大於上述第1記憶體晶片，具有配線，將上述第1記憶體晶片與上述邏輯晶片電性連接。
  6. 如請求項5之半導體裝置，其中上述配線體具有樹脂層，且上述配線設置於上述樹脂層之中。
  7. 一種半導體裝置，其具備： 第1記憶體晶片，其具有第1正面及第1背面，於上述第1正面側設置有第1記憶體電路； 第2記憶體晶片，其具有第2正面及第2背面，於上述第2正面側設置有第2記憶體電路，與上述第1正面相向，與上述第1記憶體晶片電性連接； 邏輯晶片，其與上述第2記憶體晶片之間設置有上述第1記憶體晶片，具有第3正面及第3背面，於上述第3正面側設置有邏輯電路，與上述第1記憶體晶片電性連接；以及 配線體，其具有第4正面及第4背面，設置於上述邏輯晶片與上述第1記憶體晶片之間，上述第4背面與上述邏輯晶片相向，寬度大於上述第1記憶體晶片，具有配線，將上述第1記憶體晶片與上述邏輯晶片電性連接。
  8. 如請求項7之半導體裝置，其中上述配線體具有樹脂層，且上述配線設置於上述樹脂層之中。
  9. 如請求項7或8之半導體裝置，其中進而具備：外部端子，其設置於上述配線體之上述第4背面側，電性連接於上述配線；以及連接端子，其設置於上述邏輯晶片與上述配線體之間，將上述邏輯晶片與上述配線電性連接。
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