TWI633662B - 高電子遷移率電晶體及其製造方法 - Google Patents

高電子遷移率電晶體及其製造方法 Download PDF

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TWI633662B
TWI633662B TW105121517A TW105121517A TWI633662B TW I633662 B TWI633662 B TW I633662B TW 105121517 A TW105121517 A TW 105121517A TW 105121517 A TW105121517 A TW 105121517A TW I633662 B TWI633662 B TW I633662B
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layer
field plate
edge
passivation layer
donor supply
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TW201731103A (zh
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蔡明瑋
敬源 黃
熊志文
林明正
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台灣積體電路製造股份有限公司
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Abstract

本發明一些實施例提供一種半導體裝置。半導體裝置包括一半導體基板。一供體供應層，其係於該半導體基板之上。該供體供應層包括一頂表面。一閘極結構、一汲極及一源極，其等係於該供體供應層之上。一鈍化層，其共形地覆蓋於該閘極結構及該供體供應層之上。一閘極電極，其係於該閘極結構之上。一場板，其設置於該鈍化層上及介於該閘極電極與該汲極間。該場板包括一底邊緣。其中該閘極電極具有一第一邊緣，其係相鄰於該場板，該場板包括一第二邊緣，其與該第一邊緣面對，介於該第一邊緣與該第二邊緣間之一水平距離係於從約0.05至約0.5微米之一範圍內。

Description

高電子遷移率電晶體及其製造方法
本發明係關於一種半導體裝置，特別是關於一種高電子遷移率電晶體(HEMT)。
一高電子遷移率電晶體(HEMT)，其亦稱為異質結構場效電晶體(HFET)或調制摻雜場效電晶體(MODFET)，包括介於具有不同能帶隙之兩材料間之接面(亦即一異質接面)為通道而非如多數之金氧半場效電晶體(MOSFET)為摻雜區域。
HEMT可操作在上至複數毫米波頻率之高頻，且係使用於複數高頻產品。HEMT通常使用採用複數三五族化合物半導體之材料組合。化合物半導體例如像砷化鎵、砷化鋁鎵、氮化鎵或氮化鋁鎵能使用於作為HEMT之通道之接面。
本發明一些實施例提供一種半導體裝置。半導體裝置包括一半導體基板。一供體供應層，其係於該半導體基板之上。該供體供應層包括一頂表面。一閘極結構、一汲極及一源極，其等係於該供體供應 層之上。一鈍化層，其係於該閘極結構及該供體供應層之上。一閘極電極，其係於該閘極結構之上。一場板，其設置於該鈍化層上及介於該閘極電極與該汲極間。該場板包括一底邊緣。其中該閘極電極具有一第一邊緣，其係相鄰於該場板，該場板包括一第二邊緣，其與該第一邊緣面對，介於該第一邊緣與該第二邊緣間之一水平距離係於從約0.05至約0.5微米之一範圍內。
本發明一些實施例提供一種製造一半導體裝置之方法。該方法包括提供一半導體基板；形成於該半導體基板之上之一供體供應層；形成於該供體供應層之上之一閘極結構；形成於該閘極結構及該供體供應層之上之一鈍化層；形成於該鈍化層中之複數開口；經由沉積於該鈍化層之上及於該等開口中之一導電層以形成一汲極及一源極；經由圖案化該導電層以形成相鄰於該閘極結構之一場板及形成於該源極或該汲極之上之一接觸；及形成一覆蓋層，其覆蓋於該場板之上。
本發明一些實施例一種製造一半導體裝置之方法。該方法包括接收一半導體基板；形成於該半導體基板之上之一供體供應層；形成於該供體供應層之上之一閘極結構；形成於該閘極結構及該供體供應層之上之一鈍化層，該鈍化層之一頂表面係以一特定高度位於該供體供應層之上；形成於該鈍化層中之複數開口；經由沉積於該鈍化層之上及於該等開口中之一導電層以形成一汲極及一源極，以及移除該導電層之一部分；形成於該鈍化層之上之一場板，該場板係以一高度位於該供體供應層之上，該高度小於該特定高度；及形成一氧化層，其覆蓋於該場板之上及其部分覆蓋於該閘極結構之上。
1‧‧‧半導體基板
2‧‧‧緩衝層
3‧‧‧緩衝層
4‧‧‧通道層
5‧‧‧供體供應層
10‧‧‧閘極保護層
11‧‧‧鈍化層
14‧‧‧覆蓋層
15‧‧‧閘極結構
17‧‧‧閘極電極
18‧‧‧源極
19‧‧‧汲極
20‧‧‧場板
21‧‧‧場板
31‧‧‧蝕刻操作
40‧‧‧直條
41‧‧‧直條
42‧‧‧直條
43‧‧‧直條
50‧‧‧實線
51‧‧‧折線
52‧‧‧曲線
53‧‧‧曲線
54‧‧‧曲線
55‧‧‧曲線
100‧‧‧半導體裝置
111‧‧‧部分
121‧‧‧凹陷
171‧‧‧開口
172‧‧‧水平部分
181‧‧‧源極接觸
182‧‧‧開口
189‧‧‧導電層
191‧‧‧汲極接觸
192‧‧‧開口
200‧‧‧半導體裝置
202‧‧‧硬遮罩
300‧‧‧半導體裝置
400‧‧‧製造方法
410-480‧‧‧操作
441-481‧‧‧操作
500‧‧‧半導體裝置之場強度之圖
501‧‧‧半導體裝置之汲極至源極電壓之圖
502‧‧‧半導體裝置之性能指數之圖
B2‧‧‧底邊緣
B3‧‧‧底表面
H1‧‧‧垂直距離
H2‧‧‧垂直距離
H3‧‧‧垂直距離
H4‧‧‧高度
L1‧‧‧水平距離
L3‧‧‧長度
L20‧‧‧長度
L25‧‧‧距離
L32‧‧‧長度
S1‧‧‧第一邊緣
S2‧‧‧第二邊緣
S4‧‧‧遠邊緣
S5‧‧‧頂表面
S8‧‧‧介面
S11‧‧‧頂表面
S20‧‧‧遠邊緣
T19‧‧‧頂表面
T20‧‧‧頂表面
當結合附圖閱讀時，自以下實施方式最好地理解本發明之各方面。應提及，根據業界中之標準慣例，各種特徵未按比例繪製。事實 上，為了論述清楚起見，可任意增加或減小各種特徵之尺寸。
圖1為根據本發明之一些實施例之半導體裝置之剖面圖。
圖2為根據本發明之一些實施例之半導體裝置之剖面圖。
圖3為根據本發明之一些實施例之半導體裝置之剖面圖。
圖4為根據本發明之一些實施例所顯示半導體裝置之場強度之圖。
圖5為根據本發明之一些實施例所顯示一閘極至汲極電容相對於一施加之半導體裝置之汲極至源極電壓之圖。
圖6為根據本發明之一些實施例所顯示半導體裝置之性能指數之圖。
圖7為根據本發明之一些實施例之製造一半導體裝置之一方法之一操作流程。
圖8至17為根據本發明之一些實施例當製造一半導體裝置之一方法之複數操作之複數片段剖面圖。
圖18為根據本發明之一些實施例之製造一半導體裝置之一方法之一操作流程。
圖19A至25為根據本發明之一些實施例當製造一半導體裝置之一方法之複數操作之複數片段剖面圖。
以下揭示內容提供用於實施所提供之標的物之不同特徵的許多不同實施例或實例。下文描述元件及配置之特定實例以簡化本發明。當然，此等僅為實例而並不希望為限制性。例如，在以下描述中，第一特徵在第二特徵之上或上之形成可包括第一特徵及第二特徵直接接觸地形成之實施例，且亦可包括額外特徵可在第一特徵與第二特徵間形成而使得第一特徵與第二特徵可不直接接觸之實施例。另外，本發 明可在各種實例中重複參考標號及/或字母。此重複係出於簡單及清楚之目的，且本身並不限定所論述之各種實施例及/或組態間的關係。
進一步來說，諸如「下墊」、「之下」、「下」、「之上」、「上」及類似等空間相對術語可為了描述方便而於本文中用來描述如圖式中所顯示之一個元件或一個特徵與另一或多元件或另一或多特徵之關係。除圖中所描繪之定向之外，空間上相對之術語意圖涵蓋在使用或操作中之器件之不同定向。裝置可以其他方式定向(旋轉90度或處於其他些定向)，且本文中所使用之空間相對描述詞同樣可相應地進行解釋。
在複數矽基板上之複數氮化鎵之HEMTs係使用作為用於複數電壓轉換應用之複數功率切換電晶體。相較於複數矽功率電晶體，氮化鎵之HEMTs具有複數低導通狀態之特徵，及由於複數寬能帶隙特性之複數低切換損耗。
複數增強型氮化鋁鎵/氮化鎵之高電子遷移率電晶體(E-HEMTs)係使用於複數功率電路應用。E-HEMT包括一場板，其設計以調制於一通道中之複數電場。
於介於通道及漂移區間之一介面中之複數高電壓造成複數低崩潰電壓。於介面中之電場能經由包括一非常低之摻雜於漂移區中而減少。由於此操作會增加電阻，其他解決方式例如像減少電場之峰值被使用。此解決方式亦稱為降低表面電場(RESURF)技術。RESURF技術能使用一場板結構以降低介於閘極與汲極間之電容(Cgd)及以增加功率效率。RESURF技術能影響一功率裝置之性能指數(FOM)。場板調制介於閘極與汲極間之電場以致於減少一空乏輪廓以及增加一裝置速度。
使場板較靠近閘極與通道可減少鄰近閘極之電場與降低Cgd。於 一些實施例中，如圖1所示，場板20係設置於覆蓋層14之下，而非覆蓋層14之上，以致於場板20係設置較靠近通道。通道能位於通道層4中。覆蓋層14經由完全覆蓋於場板20之上以保護場板20。
圖1顯示用於高電壓應用之一半導體裝置100。半導體裝置100能為一高電子遷移率電晶體(HEMT)，其包括一半導體基板1、一通道層4、一供體供應層5、一閘極結構15、一閘極保護層10、一鈍化層11、一閘極電極17、一源極18、一源極接觸181、一汲極19、一汲極接觸191、一場板20及覆蓋層14。
供體供應層5包括一頂表面S5。閘極結構15係於供體供應層5之頂表面S5上。汲極19與源極18部分埋於供體供應層5。閘極保護層10係於閘極結構15及供體供應層5之上。鈍化層11亦係於閘極結構15及供體供應層5之上並沿著閘極保護層10之形狀。汲極19或源極18穿透鈍化層11及閘極保護層10以達到供體供應層5。源極接觸181係於源極18之上。汲極接觸191係於汲極19之上。源極接觸181或汲極接觸191之一底表面B3係與場板20之一底邊緣B2實質共平面。閘極電極17係於閘極結構15之上。
於一些實施例中，場板20係設置於鈍化層11上，且係位於閘極結構15與汲極19間。閘極電極17包括一第一邊緣S1，其與場板20相鄰。場板20包括一第二邊緣S2及一底邊緣B2。第二邊緣S2面對第一邊緣S1。底邊緣B2面對供體供應層5。介於第一邊緣S1與第二邊緣S2間之一水平距離L1係於從約0.05至約0.5微米之一範圍內。場板20為靠近閘極電極17之第一邊緣S1以減少靠近閘極電極17之第一邊緣S1之電場。然而，水平距離L1係設計為於從約0.05至約0.5微米之一範圍內以致於在界定源極接觸181及汲極接觸191之一蝕刻操作後保留一足夠的厚度，其顯示為介於第一邊緣S1與第二邊緣S2間之鈍化層11之一部分111。於一些實施例中，複數蝕刻操作係能用於移除鈍化層11之一 頂部分，其關於過蝕刻源極接觸181與汲極接觸191。鈍化層11之部分111避免場板20與閘極電極17間之電氣短路。
介於底邊緣B2及頂表面S5之一垂直距離H1係約100埃。場板20係為靠近供體供應層5之頂表面S5以減少於場板20之下之電場。場板20包括從第二邊緣S2至與第二邊緣S2相對之一遠邊緣S20之一長度L20。垂直距離H1係設計為約100埃，以避免過蝕刻鈍化層11造成暴露下墊之保護層10或供體供應層5。然而，於一些實施例中，由於當使用較厚之垂直距離H1時能避免前述之過蝕刻，垂直距離H1能係較約100埃為厚。保護層10包括從約5至約500埃之一範圍內之一厚度。垂直距離H1係至少較保護層10之厚度為大。於一些實施例中，由於係選擇以例如像各向異性蝕刻之蝕刻操作移除鈍化層11中較複數垂直部分為多之複數水平部分，垂直距離H1係較水平距離L1為小。垂直部分係為直接環繞閘極電極17之部分111。水平部分係為平行於頂表面S5之部分。
覆蓋層14係於場板20、源極接觸181、汲極接觸191或閘極結構15之上。閘極電極17包括於場板20之上之一水平部分172。水平部分172係部分覆蓋於覆蓋層14之上。水平部分172包括一遠邊緣S4，及延伸至場板20之上。於一些實施例中，水平部分172與場板20以在從約0.05至約0.5微米之一範圍內之一長度L3重疊，以致於水平部分172完全覆蓋於鈍化層11之部分111之上以保護一絕緣區域免於後續例如像蝕刻之製造操作。
半導體裝置100包括於半導體基板1之上之複數層。一些層為複數磊晶層。該些層包括一選擇性之氮化鋁之凝核層、一選擇性之氮化鋁鎵之緩衝層及一整體氮化鎵層，例如像通道層4。通道層4可係於一緩衝層之上或直接於半導體基板1上。
例如像供體供應層5之一主動層係於通道層4之頂上。於通道層4 及供體供應層5之間界定一介面S8。二維電子氣(2-DEG)之一載子通道41係位於與介面S8相鄰之處。於一些實施例中，供體供應層5係為一氮化鋁鎵(AlGaN)層。供體供應層5具有AlxGa(1-x)N之化學式，其中x於約10%及約100%之間變化。供體供應層5具有一厚度，其係在從約5奈米至約50奈米之一範圍內。於其他實施例中，供體供應層5可包括一AlGaAs層，或AlInP層。
一能帶隙間斷存在於供體供應層5及通道層4之間。於供體供應層5從壓電效應而來的複數電子掉入通道層4，於通道層4中創造高遷移之導通電子之一非常薄之層。此薄層係稱為一二維電子氣(2-DEG)，其形成一載子通道41。2-DEG之薄層係位於靠近供體供應層5與通道層4之介面S8。因此，因為通道層4係為無摻雜或是非特意地無摻雜，及複數電子能自由地移動而與複數雜質無碰撞或實質減少碰撞，載子通道41具有高電子遷移率。
源極18與汲極19係設置於供體供應層5上，以與載子通道41電連接。源極18與汲極19包括一對應之金屬間化合物。於一些實施例中，金屬間化合物係嵌入於供體供應層5及可更嵌入於通道層4之一頂部分。於一些實施例中，金屬間化合物包括Al、Ti或Cu。於其他一些實施例中，金屬間化合物包括AN、TiN、Al3Ti或AlTiN。
閘極結構15係置於供體供應層5上，及係位於源極18與場板20之間。閘極結構15可包括一或多層。閘極結構15包括例如像具有複數負或正摻雜物之氮化鎵之一半導體材料。
於閘極電極17中之一導電材料係用於電壓偏壓及與載子通道41電耦接。於一些實施例中，導電材料可包括一耐熔材料或其複數化合物，舉例而言為鎢(W)、氮化鈦(TiN)及鉭(Ta)。其它通常使用於導電材料中之複數金屬包括鎳(Ni)及金(Au)。
鈍化層11覆蓋介於閘極結構15與汲極19間之供體供應層5之一漂 移區。鈍化層11中位於場板20以下之一部分具有例如像垂直距離H1之相對一致之高度。
場板20包括相對於第二邊緣S2之一遠邊緣S20。鈍化層11中介於遠邊緣S20及汲極19間之一部分包括例如像垂直距離H2之相對一致之另一高度。於一些實施例中，垂直距離H1係較垂直距離H2大有約為100至200埃。鈍化層11中場板20之下及汲極接觸191之一突出部分之下之一高度能與垂直距離H1大約相同。鈍化層11之頂表面S11係較底邊緣B2或底表面B3為低。場板20與汲極接觸191之對應複數厚度係實質相同以致於場板20之一頂表面T20及汲極接觸191之一頂表面T19係實質置於一相同高度水平。
於一些實施例中，源極18、汲極19、源極接觸181或汲極接觸191包括一與場板20相同之材料。材料能為一歐姆金屬。
鈍化層11包括例如像氧化矽(SiOx)、氮化矽(SiNx)、氮氧化矽、碳摻雜之氧化矽、碳摻雜之氮化矽、碳摻雜之氮氧化矽、氧化鋅、氧化鋯、氧化鉿或氧化鈦之材料。鈍化層11之一厚度係於從約50奈米至約500奈米之一範圍內。經由減少鈍化層11之厚度，能減少垂直距離H1及水平距離L1。減少垂直距離H1及水平距離L1使得場板20較靠近閘極電極17之第一邊緣S1及較靠近供體供應層5之頂表面S5。經此以增加RESURF區域之效用，固而，降低介於閘極與汲極間之電容(Cgd)及增加HEMT之功率效率。圖2顯示用於高功率應用之一半導體裝置200。半導體裝置200與圖1中之半導體裝置100相似，差異在於一場板21包括材料，其不同於源極接觸181、汲極接觸191、源極18或汲極19之材料。場板21之一底邊緣B2係與鈍化層11之頂表面S11為實質共平面。底邊緣B2係較汲極接觸191之一底表面B3低有從約100至約200埃之一範圍。於一些實施例中，緩衝層2或緩衝層3係設置於半導體基板1與通道層4間。
圖3顯示用於另一高功率電晶體之一半導體裝置300。半導體裝置300與圖2中之半導體裝置200相似，差異在於一場板21之底邊緣B2較鈍化層11之頂表面S11為低。場板21係以一垂直距離H3位於供體供應層5之頂表面S5之上。於一些實施例中，垂直距離H1係較垂直距離H2為大。垂直距離H2係較垂直距離H3為大。與例如像第一邊緣S1之一閘極邊緣相鄰之場板20或21減少於閘極邊緣之一最大表面電場。
圖4為根據本發明之一些實施例所顯示半導體裝置之場強度之圖500。圖500之一水平軸表示通道層4之介面S8之一位置。舉例而言，閘極邊緣(或稱為圖1中閘極電極17之第一邊緣S1)係以約1.7微米位於介面S8之位置之上。一場板邊緣(或稱為圖1中場板20之遠邊緣S20)係以約2.7微米位於介面S8之位置之上。圖500之一垂直軸表示於介面S8之電場強度之大小。一實線50表示於一些實施例中使用一場板之電場強度。一折線51表示於其它例如像於一鈍化層之上設置一場板之使用一場板之傳統配置之電場強度。於閘極邊緣(亦為第一邊緣S1)之附近，折線51抵達約為2.5E6之一峰值高度，然而實線50抵達約為2.4E6之一峰值高度。本發明中之場板降低靠近閘極邊緣(亦為第一邊緣S1)之電場強度之峰值高度。
圖5為根據本發明之一些實施例所顯示一閘極至汲極電容相對於一施加之半導體裝置之汲極至源極電壓之圖501。當施加一電壓Vds於一汲極與一源極間，閘極至汲極電容根據不同之場板結構不同地變化。曲線52表示於一傳統配置中使用一場板之一半導體裝置之閘極至汲極電容。曲線53表示於本發明之一些實施例中使用一第一場板之一半導體裝置之閘極至汲極電容。曲線54表示於本發明之一些實施例中使用一第二場板之一半導體裝置之閘極至汲極電容。舉例而言，相較於第一場板之下之鈍化厚度，分開第二場板及通道僅有75%之鈍化厚度。曲線55表示於本發明之一些實施例中使用一第三場板之一半導體 裝置之閘極至汲極電容。舉例而言，相較於第一場板之下之鈍化厚度，分開第三場板及通道僅有50%之鈍化厚度。對於在約20伏特之Vds，閘極至汲極電容係曲線55為最低，表示在一比較上較低之Vds而達成之空乏。減少介於場板及通道間之距離降低在一特定Vds之閘極至汲極電容。並且於曲線55之下之積分面積係為曲線52-54之下之積分面積等中之最小一個。固而，使用本發明所教示之場板之裝置能達成較大之切換速度。
圖6為根據本發明之一些實施例所顯示半導體裝置之性能指數之圖502。性能指數為一量值，其用以特性化一半導體裝置之效能。於圖6中，性能指數包括導通電阻Ron及閘極至汲極電荷Qgd之對應複數量值之乘積。一低導通電阻表示複數低導通損耗。一低閘極至汲極電荷顯示低切換損耗。Ron與Qgd之乘積係通常地使用於量化一裝置效能。一較小之乘積顯示較佳之切換效能。圖502顯示Ron與Qgd之乘積，其係用於不同的場板結構。直條40表示一傳統配置之場板結構。直條41表示用於圖5所描述之第一場板之乘積。直條42表示用於圖5所描述之第二場板之乘積。直條43表示用於圖5所描述之第三場板之乘積。減少介於通道及場板間之隔離增加切換效能。
一製造方法400顯示於圖7中。圖7顯示一方法流程，其用以形成圖1中之半導體裝置100。操作410接收一半導體基板1。一些用於操作410之例示性實施例係顯示於圖8中。操作420形成於半導體基板1之上之一供體供應層5。一些用於操作420之例示性實施例係顯示於圖8中。操作430形成於供體供應層5之上之一閘極結構15。一些用於操作430之例示性實施例係顯示於圖9中。操作440形成於閘極結構15及供體供應層5之上之一鈍化層11。一些用於操作440之例示性實施例係顯示於圖11中。操作450形成於鈍化層11中之複數開口192及182。一些用於操作450之例示性實施例係顯示於圖12A中。操作460經由沉積於 鈍化層11之上及於開口192及182中之一導電層189以形成一源極18與一汲極19。一些用於操作460之例示性實施例係顯示於圖12B中。操作470經由圖案化導電層189以形成鄰近於閘極結構15之一場板20及形成於源極18或汲極19之上之一接觸181或191。一些用於操作470之例示性實施例係顯示於圖14中。操作480形成一覆蓋層14，其覆蓋於場板20之上。一些用於操作480之例示性實施例係顯示於圖15中。
於圖8中，接收半導體基板1。堆疊形成於半導體基板1之上之通道層4及供體供應層5。於一些實施例中，磊晶地形成緩衝層2及3、通道層4或供體供應層5。
於圖9中，形成例如像氮化鎵之一摻雜半導體層，其包括一正或負摻雜物。摻雜半導體層係以任合適當之方法例如像微影蝕刻圖案化以形成閘極結構15。
於圖10中，共形地形成於閘極結構15及供體供應層5之上之閘極保護層10。形成閘極保護層10係經由任合適當之沉積操作，其例如像化學氣相沈積(CVD)、物理氣相沈積(PVD)、原子層沈積(ALD)、高密度電漿化學氣相沈積(HDPCVD)、遙距電漿化學氣相沈積(RPCVD)、電漿輔助化學氣相沈積(PECVD)，或低壓化學氣相沈積(LPCVD)，及其用以沉積例如像氮化鋁(AlN)或氧化鋁(Al2O3)之材料。
於圖11中，形成於閘極保護層10之上之鈍化層11係以任合適當之沉積操作。形成鈍化層11，其包括一厚度以避免後續例如像過蝕刻鈍化層11之操作毀損閘極保護層10，厚度係於從約50至約500奈米之一範圍內。厚度係為足夠地小以致於圖1中於鈍化層11之頂上之場板20以高度H1與供體供應層5之頂表面S5相近。利用鈍化層11之厚度以控制高度H1。
於圖12A中，形成開口182及192係以任合適當之操作，其例如像蝕刻。於一些實施例中，蝕刻停止在供體供應層5之一頂部分上。於 一些實施例中，移除供體供應層5之頂部分。
於圖12B中，導電層189覆蓋於鈍化層11之上及填充於開口182及192中，以形成源極18及汲極19。於一些實施例中，導電層189為一歐姆金屬，其係以任合適當之沉積形成。於一些實施例中，導電層189之一頂表面係為均勻地平坦設置於汲極19之上且延伸至鈍化層11之部分111。如圖1所示，鈍化層11之部分111係介於閘極電極17之第一邊緣S1及場板20之第二邊緣S2間。
於圖13中，圖案化光阻或硬遮罩202以致其覆蓋於源極18及汲極19之上，固而保護導電層189於源極18與汲極19之上之對應複數部分免於一蝕刻操作31。於圖14中，導電層189於源極18之上之部分形成源極接觸181。導電層189於汲極19之上之部分形成汲極接觸191。於一些實施例中，蝕刻操作31係為各向異性蝕刻，其例如像乾蝕刻。於圖14中，光阻或硬遮罩202亦保護導電層189靠近於閘極結構15之另一部分以形成場板20。移除導電層189暴露於圖13中之蝕刻操作31之蝕刻劑之複數其他部分。蝕刻操作31包括乾蝕刻、反應性離子蝕刻、單純化學(電漿蝕刻)，及/或其組合等。
於圖14中，經由因為過蝕刻而減少之鈍化層11厚度以低化鈍化層11之頂表面S11之一部分有約100至約200埃。用過蝕刻以供確定介於場板20及汲極接觸191間導電層189之一部分之一完全移除以致於避免場板20及汲極接觸191間之電氣短路。於一些實施例中，採用過蝕刻以確定所有之導電跡線為適當地圖案化而無非特意之電連接。能從圖14中看出，頂表面S11係較底邊緣B2為低。高度H1係較高度H2為高有約100至約200埃。沿著場板20形成源極接觸181及汲極接觸191。以圖13中之光阻及或硬遮罩202保護場板20之頂表面T20及汲極接觸191之頂表面T19以致於其於頂表面S5之上之對應複數高度保持近乎地相同在高度H1。場板20及汲極接觸191之對應複數厚度亦實質地相同。底 邊緣B2及底表面B3由於受到保護免於蝕刻而近乎相同地位於高度H1。於圖13中，經由圖案化接近閘極結構15之光阻或硬遮罩202以控制介於場板20與閘極結構15間之一距離L25。於一些實施例中，距離L25係小於約0.5微米。
在圖15中，覆蓋層14係形成於源極接觸181、鈍化層11、場板20及汲極接觸191之上。於一些實施例中，覆蓋層14之一頂表面沿著場板20或汲極接觸191之形狀。
在圖16中，形成開口171係以任合適當之操作，其例如像乾蝕刻。乾蝕刻移除覆蓋層14、鈍化層11及閘極保護層10在閘極結構15之上之複數部分。暴露閘極結構15之一部分。乾蝕刻界定第一邊緣S1，其在與場板20之第二邊緣S2相距水平距離L1處。控制水平距離L1為少於約0.5微米，其係經由任合適當之微影蝕刻操作，其包括乾蝕刻。
於圖17中，形成閘極電極17。於一些實施例中，毯覆式沈積一導電材料於覆蓋層14之上且填充於開口171中以形成閘極電極17。圖案化導電材料以包括於場板20之一部分之上之一水平部分172。於一些實施例中，一圖案化操作界定閘極電極17之水平部分172之遠邊緣S4，其係為從閘極電極17之第一邊緣S1延伸一長度L32而至，長度L32係在從約0.1至約2微米之一範圍內。水平部分172保護鈍化層11介於閘極電極17與場板20間之部分111。
一製造方法401顯示於圖18中。圖18顯示一方法流程，其用以形成圖2中之半導體裝置200。於一些實施例中，操作441能為接續圖7之操作430。操作441形成於閘極結構15及供體供應層5之上之鈍化層11，鈍化層11例如像頂表面S11(示於圖2)之一頂係以一特定之高度H2位於供體供應層5之上。一些用於操作441之例示性實施例係顯示於圖19A中。操作451形成於鈍化層11中之複數開口192及182。一些用於 操作451之例示性實施例係顯示於圖19A中。操作461經由沉積一導電層189於鈍化層11之上及於開口192及182中以形成一源極18與一汲極19。一些用於操作461之例示性實施例係顯示於圖19B中。操作471經由移除導電層189之一部分以形成於源極18或汲極19之上一接觸181或191。一些用於操作471之例示性實施例係顯示於圖19B及20中。操作481形成於鈍化層11上之一場板21，場板21係以小於特定高度H1之一高度H2位於供體供應層5之上。一些用於操作481之例示性實施例係顯示於圖21中。
於一些實施例中，操作471能參考至圖19B及20。經由形成於導電層189之上之光阻或硬遮罩202以形成一接觸191或181。光阻或硬遮罩202之形成接續自圖12B中之操作460。圖案化光阻或硬遮罩202位於導電層189覆蓋於源極18與汲極19之上之對應複數部分而無靠近部分111之部分。在圖19B中，暴露導電層189靠近部分111之部分於蝕刻操作31之蝕刻劑中，但保護導電層189位於源極18或汲極19之上之對應部分免於蝕刻操作31。於圖20中，場板並無與汲極接觸191同時地形成。復參照圖13，場板20係與汲極接觸191同時地於一單一微影蝕刻操作中形成。於圖21中，分開地形成場板21於形成汲極接觸191之後。
於圖20中，移除導電層189之一些暴露部分而剩下保留於源極18與汲極19之上之源極接觸181及汲極接觸191。汲極接觸191之底表面B3係以一高度H1位於頂表面S5之上。鈍化層11未以源極接觸181與汲極接觸191覆蓋之一頂部分係以過蝕刻部分地移除以致於頂表面S11自高度H1低化至高度H2。
於圖21中，形成場板21，其係於移除鈍化層11之頂部分之後。場板21係形成於鈍化層11之頂上以致於底邊緣B2係以高度H2位於頂表面S5之上。場板21可經由沉積不同於汲極接觸191或源極接觸181之材 料形成，此因場板21非係經由圖案化圖19B中之導電層189形成。適合用於場板21之材料包括氮化鈦、鈦，或鋁銅。能使場板21之底邊緣B2自汲極接觸191之底表面B3以一高度H4低化，高度H4係為約100之約200埃。低化底邊緣B2減少靠近頂表面S5之電場。場板21之一厚度能與汲極接觸191或源極接觸181之對應厚度不同。
於圖22中，形成覆蓋層14，其係覆蓋於場板21之上、鈍化層11之上，及汲極接觸191之上，此係與圖15中之覆蓋層14相同。於圖23中，形成閘極電極17及其水平部分172，其係相似於圖16及17中所顯示之操作。
於一些進一步之實施例中，於圖24中進一步移除鈍化層11之一頂部分之複數額外操作能夠後續地接在圖20中形成汲極接觸191之操作之後。圖24及25顯示用於形成圖3中之半導體裝置300之額外操作。於圖24中，蝕刻鈍化層11之頂部分以形成凹陷121以致於凹陷121之一底係以一高度H3位於頂表面S5之上。凹陷121之高度H3係小於頂表面S11之高度H2。應提及圖25及26所顯示之頂表面S11係指鈍化層11介於汲極19與場板21間之一部份。頂表面S11之高度H2係較底表面B3之高度H1為小。高度H3能為一設計因素，其係依據場板經由設置場板於距離頂表面S5一適當距離之位置而減少閘極邊緣電場之效果如何。故此，鈍化層11原來之厚度非為該適當距離之一限制因素。
於圖25中，形成於凹陷121中之場板21。場板21之底邊緣B2係與凹陷121之底接觸以致於底邊緣B2係低於頂表面S11。形成覆蓋層14，其經由形成一氧化層，其覆蓋場板21及鈍化層11。覆蓋層14係形成於閘極結構15之上。蝕刻覆蓋層14之一部份以用於閘極電極17之形成。形成場板21，其具有一第二邊緣S2。形成閘極電極17，其具有一第一邊緣S1，其與場板21之第二邊緣S2相對。從第一邊緣S1至第二邊緣S2之水平距離L1係在從約0.05至約0.5微米之一範圍內。
本發明一些實施例提供一種半導體裝置。半導體裝置包括一半導體基板。一供體供應層，其係於該半導體基板之上。該供體供應層包括一頂表面。一閘極結構、一汲極及一源極，其等係於該供體供應層之上。一鈍化層，其係於該閘極結構及該供體供應層之上。一閘極電極，其係於該閘極結構之上。一場板，其設置於該鈍化層上及介於該閘極電極與該汲極間。該場板包括一底邊緣。其中該閘極電極具有一第一邊緣，其係相鄰於該場板，該場板包括一第二邊緣，其與該第一邊緣面對，介於該第一邊緣與該第二邊緣間之一水平距離係於從約0.05至約0.5微米之一範圍內。
本發明一些實施例提供一種製造一半導體裝置之方法。該方法包括提供一半導體基板；形成於該半導體基板之上之一供體供應層；形成於該供體供應層之上之一閘極結構；形成於該閘極結構及該供體供應層之上之一鈍化層；形成於該鈍化層中之複數開口；經由沉積於該鈍化層之上及於該等開口中之一導電層以形成一汲極及一源極；經由圖案化該導電層以形成相鄰於該閘極結構之一場板及形成於該源極或該汲極之上之一接觸；及形成一覆蓋層，其覆蓋於該場板之上。
本發明一些實施例一種製造一半導體裝置之方法。該方法包括接收一半導體基板；形成於該半導體基板之上之一供體供應層；形成於該供體供應層之上之一閘極結構；形成於該閘極結構及該供體供應層之上之一鈍化層，該鈍化層之一頂表面係以一特定高度位於該供體供應層之上；形成於該鈍化層中之複數開口；經由沉積於該鈍化層之上及於該等開口中之一導電層以形成一汲極及一源極，以及移除該導電層之一部分；形成於該鈍化層之上之一場板，該場板係以一高度位於該供體供應層之上，該高度小於該特定高度；及形成一氧化層，其覆蓋於該場板之上及其部分覆蓋於該閘極結構之上。
前文概述若干實施例的特徵以使得一般熟習此項技術者可更好 地理解本發明之各方面。一般熟習此項技術者應理解，其可易於使用本發明作為設計或修改用於實現本文中所引入之實施例的相同目的及/或獲得相同優點之其他過程及結構之基礎。一般熟習此項技術者亦應認識到，此類等效構造並不脫離本發明之精神及範疇，且其可在不脫離本發明之精神及範疇之情況下在本文中進行各種改變、替代及更改。

Claims (9)

  1. 一種半導體裝置，其包含：一半導體基板；一供體供應層，其係於該半導體基板之上，及該供體供應層包含一頂表面；一閘極結構、一汲極及一源極，其等係於該供體供應層之上；一鈍化層，其係於該閘極結構及該供體供應層之上；一閘極電極，其係於該閘極結構之上；一場板，其設置於該鈍化層上及介於該閘極電極與該汲極間，該場板包含一底邊緣；及一覆蓋層，覆蓋於該鈍化層與該場板之上；其中該閘極電極具有一第一邊緣，其係相鄰於該場板，該場板包含一第二邊緣，其與該第一邊緣面對，介於該第一邊緣與該第二邊緣間之一水平距離係於從約0.05至約0.5微米之一範圍內，該鈍化層與該第一邊緣及該第二邊緣接觸，且該場板具有相對於該第二邊緣之一第三邊緣，該覆蓋層與該第一邊緣及該第三邊緣接觸。
  2. 如請求項1之半導體裝置，其更包含一接觸，其係於該源極或該汲極之上，該接觸包含一底表面，其與該場板之該底邊緣為實質共平面。
  3. 如請求項1之半導體裝置，其更包含一接觸，其係於該源極或該汲極之上，該接觸之一底表面係實質較該場板之該底邊緣為高，該場板之該底邊緣係與該鈍化層之一頂表面為實質共平面。
  4. 如請求項1之半導體裝置，其中該場板之該底邊緣係實質較該鈍化層之一頂表面為低。
  5. 如請求項1之半導體裝置，其中該閘極電極包含一水平部分，其係於該覆蓋層之上且其延伸於該場板之上。
  6. 一種製造一半導體裝置之方法，其包含：提供一半導體基板；形成於該半導體基板之上之一供體供應層；形成於該供體供應層之上之一閘極結構；形成於該閘極結構及該供體供應層之上之一鈍化層；形成於該鈍化層中之複數開口；經由沉積於該鈍化層之上及於該等開口中之一導電層以形成一汲極及一源極；經由圖案化該導電層，於一單一操作中形成相鄰於該閘極結構之一場板及形成於該源極或該汲極之上之一接觸；及形成一覆蓋層，其覆蓋於該場板之上。
  7. 一種製造一半導體裝置之方法，其包含：接收一半導體基板；形成於該半導體基板之上之一供體供應層；形成於該供體供應層之上之一閘極結構；形成於該閘極結構及該供體供應層之上之一鈍化層，該鈍化層之一頂表面係以一特定高度位於該供體供應層之上；形成於該鈍化層中之複數開口；經由沉積於該鈍化層之上及於該等開口中之一導電層以形成一汲極及一源極，以及移除該導電層之一部分；形成於該鈍化層之上之一場板，該場板係以一高度位於該供體供應層之上，該高度小於該特定高度；及形成一氧化層，其覆蓋於該場板之上及其部分覆蓋於該閘極結構之上。
  8. 如請求項7之方法，其中該形成該場板更包含於移除該導電層之該部分之後，過蝕刻該鈍化層之一頂部分，及於移除該鈍化層之該頂部分之後，形成該場板。
  9. 如請求項7之方法，其中該形成該場板包含沉積一導電材料，其與該導電層之一材料相異，該導電材料包含氮化鈦、鈦或鋁銅。
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