TWI610363B - 被處理體之處理方法 - Google Patents

被處理體之處理方法 Download PDF

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Publication number
TWI610363B
TWI610363B TW104120867A TW104120867A TWI610363B TW I610363 B TWI610363 B TW I610363B TW 104120867 A TW104120867 A TW 104120867A TW 104120867 A TW104120867 A TW 104120867A TW I610363 B TWI610363 B TW I610363B
Authority
TW
Taiwan
Prior art keywords
gas
region
plasma
fluorocarbon
etching
Prior art date
Application number
TW104120867A
Other languages
English (en)
Chinese (zh)
Other versions
TW201612977A (en
Inventor
Hikaru Watanabe
渡邊光
Masanobu Honda
本田昌伸
Akihiro Tsuji
辻晃弘
Original Assignee
Tokyo Electron Limited
東京威力科創股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited, 東京威力科創股份有限公司 filed Critical Tokyo Electron Limited
Publication of TW201612977A publication Critical patent/TW201612977A/zh
Application granted granted Critical
Publication of TWI610363B publication Critical patent/TWI610363B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers

Landscapes

  • Drying Of Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW104120867A 2014-07-01 2015-06-29 被處理體之處理方法 TWI610363B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2014135629 2014-07-01
JP2014-135629 2014-07-01
JP2014-219285 2014-10-28
JP2014219285A JP6235981B2 (ja) 2014-07-01 2014-10-28 被処理体を処理する方法

Publications (2)

Publication Number Publication Date
TW201612977A TW201612977A (en) 2016-04-01
TWI610363B true TWI610363B (zh) 2018-01-01

Family

ID=53969077

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104120867A TWI610363B (zh) 2014-07-01 2015-06-29 被處理體之處理方法

Country Status (6)

Country Link
US (1) US9330973B2 (https=)
EP (1) EP2963677A1 (https=)
JP (1) JP6235981B2 (https=)
KR (1) KR101888728B1 (https=)
CN (1) CN105244372B (https=)
TW (1) TWI610363B (https=)

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JP6086862B2 (ja) * 2013-08-30 2017-03-01 東京エレクトロン株式会社 酸化シリコンから構成された領域を選択的に除去する方法及びプラズマ処理装置
CN105810579B (zh) * 2015-01-16 2019-12-06 东京毅力科创株式会社 蚀刻方法
JP2016157793A (ja) * 2015-02-24 2016-09-01 東京エレクトロン株式会社 エッチング方法
JP6438831B2 (ja) * 2015-04-20 2018-12-19 東京エレクトロン株式会社 有機膜をエッチングする方法
US9508556B1 (en) * 2016-01-29 2016-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating fin field effect transistor and semiconductor device
JP6604476B2 (ja) * 2016-03-11 2019-11-13 パナソニックＩｐマネジメント株式会社 素子チップの製造方法
CN108780748B (zh) * 2016-03-17 2023-02-17 日本瑞翁株式会社 等离子体蚀刻方法
JP6670672B2 (ja) * 2016-05-10 2020-03-25 東京エレクトロン株式会社 エッチング方法
JP6656082B2 (ja) * 2016-05-19 2020-03-04 東京エレクトロン株式会社 酸化膜除去方法および除去装置、ならびにコンタクト形成方法およびコンタクト形成システム
JP6606464B2 (ja) * 2016-05-20 2019-11-13 東京エレクトロン株式会社 エッチング方法
JP2017212361A (ja) * 2016-05-26 2017-11-30 東京エレクトロン株式会社 プラズマ処理装置及びパーティクル付着抑制方法
KR101895931B1 (ko) * 2016-05-26 2018-09-10 세메스 주식회사 기판 처리 장치 및 방법
US10373828B2 (en) * 2016-05-29 2019-08-06 Tokyo Electron Limited Method of sidewall image transfer
JP6689674B2 (ja) * 2016-05-30 2020-04-28 東京エレクトロン株式会社 エッチング方法
JP6670707B2 (ja) * 2016-08-24 2020-03-25 東京エレクトロン株式会社 基板処理方法
WO2018057493A1 (en) * 2016-09-21 2018-03-29 Tokyo Electron Limited Method of patterning intersecting structures
JP6836953B2 (ja) * 2016-12-13 2021-03-03 東京エレクトロン株式会社 窒化シリコンから形成された第１領域を酸化シリコンから形成された第２領域に対して選択的にエッチングする方法
JP6767302B2 (ja) * 2017-04-14 2020-10-14 東京エレクトロン株式会社 成膜方法
JP6823527B2 (ja) * 2017-04-14 2021-02-03 東京エレクトロン株式会社 エッチング方法
JP6877316B2 (ja) * 2017-11-08 2021-05-26 東京エレクトロン株式会社 エッチング方法
KR102099886B1 (ko) * 2018-05-23 2020-04-14 세메스 주식회사 기판 처리 방법 및 기판 처리 장치
KR20210003230A (ko) * 2018-06-08 2021-01-11 가부시키가이샤 아루박 산화막 제거 방법, 및 산화막 제거 장치
JP7398915B2 (ja) * 2019-10-01 2023-12-15 東京エレクトロン株式会社 基板処理方法、半導体デバイスの製造方法、及び、プラズマ処理装置
US11232947B1 (en) 2020-09-01 2022-01-25 Taiwan Semiconductor Manufacturing Company Limited Ammonium fluoride pre-clean protection
TWI906294B (zh) * 2021-05-07 2025-12-01 日商東京威力科創股份有限公司 蝕刻方法及蝕刻裝置

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JP2000307001A (ja) * 1999-04-22 2000-11-02 Sony Corp 半導体装置の製造方法
US20050181588A1 (en) * 2004-02-13 2005-08-18 Kim Jeong-Ho Method to form a contact hole

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JP2890493B2 (ja) * 1989-07-10 1999-05-17 ソニー株式会社 プラズマ処理装置及びプラズマ処理方法
JP3086234B2 (ja) * 1990-06-29 2000-09-11 株式会社東芝 表面処理方法
US5562801A (en) * 1994-04-28 1996-10-08 Cypress Semiconductor Corporation Method of etching an oxide layer
KR100327346B1 (ko) * 1999-07-20 2002-03-06 윤종용 선택적 폴리머 증착을 이용한 플라즈마 식각방법 및 이를이용한 콘택홀 형성방법
KR100382725B1 (ko) * 2000-11-24 2003-05-09 삼성전자주식회사 클러스터화된 플라즈마 장치에서의 반도체소자의 제조방법
JP3759895B2 (ja) * 2001-10-24 2006-03-29 松下電器産業株式会社 エッチング方法
US6677247B2 (en) 2002-01-07 2004-01-13 Applied Materials Inc. Method of increasing the etch selectivity of a contact sidewall to a preclean etchant
JP2010021296A (ja) 2008-07-10 2010-01-28 Panasonic Corp 半導体装置の製造方法
US20110065276A1 (en) * 2009-09-11 2011-03-17 Applied Materials, Inc. Apparatus and Methods for Cyclical Oxidation and Etching
US9324576B2 (en) * 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
JP6059165B2 (ja) * 2014-02-19 2017-01-11 東京エレクトロン株式会社 エッチング方法、及びプラズマ処理装置
JP6396699B2 (ja) * 2014-02-24 2018-09-26 東京エレクトロン株式会社 エッチング方法
JP6230954B2 (ja) * 2014-05-09 2017-11-15 東京エレクトロン株式会社 エッチング方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000307001A (ja) * 1999-04-22 2000-11-02 Sony Corp 半導体装置の製造方法
US20050181588A1 (en) * 2004-02-13 2005-08-18 Kim Jeong-Ho Method to form a contact hole

Also Published As

Publication number Publication date
EP2963677A1 (en) 2016-01-06
US20160005651A1 (en) 2016-01-07
JP2016027594A (ja) 2016-02-18
KR20160003565A (ko) 2016-01-11
US9330973B2 (en) 2016-05-03
CN105244372B (zh) 2018-05-15
CN105244372A (zh) 2016-01-13
JP6235981B2 (ja) 2017-11-22
TW201612977A (en) 2016-04-01
KR101888728B1 (ko) 2018-08-14

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