TWI597833B - 可變電阻式記憶體元件 - Google Patents
可變電阻式記憶體元件 Download PDFInfo
- Publication number
- TWI597833B TWI597833B TW102130596A TW102130596A TWI597833B TW I597833 B TWI597833 B TW I597833B TW 102130596 A TW102130596 A TW 102130596A TW 102130596 A TW102130596 A TW 102130596A TW I597833 B TWI597833 B TW I597833B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- gate electrode
- variable resistance
- layers
- bit line
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000000903 blocking effect Effects 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 claims 3
- 239000011810 insulating material Substances 0.000 claims 2
- 230000004888 barrier function Effects 0.000 claims 1
- 230000015654 memory Effects 0.000 description 27
- 238000000034 method Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000005415 magnetization Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
- 238000004073 vulcanization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
- H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
- H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/75—Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Description
本發明係關於一種半導體積體電路元件,尤指一種使用一接面電晶體作為一切換元件的可變電阻記憶元件及其驅動方法。
記憶體元件通常被提供作為電腦或其他電子裝置之內部半導體積體電路。該等記憶體元件分成揮發性記憶體元件及非揮發性記憶體元件。
可變電阻式記憶體元件的例子包含:相變隨機存取記憶體元件(PCRAMs)、電阻式隨機存取記憶體元件(ReRAMs)或磁性隨機存取記憶體(MRAMs)。PCRAMS具有像是如動態隨機存取記憶體(DRAMs)的高記憶密度,與高可靠性及低耗能的特性。
包含可變電阻式記憶體元件的非揮發性記憶體元件可被使用於,例如MP3播放器的可攜式音樂撥放器、電影播放器、可攜式電話、數位相機、固態硬碟(SSDs)、可攜式記憶卡或個人電腦。
該等可變電阻式記憶體元件可包含複數記憶胞,其中該等記憶胞係以矩陣形式安排設置。該等記憶胞之每一者可包含一切換元件及一電阻元件,其中該切換元件係連接至一字元線,該電阻元件係連接至一位元線。
當對應的一字元線被啟動時,該切換元件可被接取access。基於傳輸至該電阻元件的一電流,一已選定記憶胞可被編程。
為了實現該可變電阻式記憶體元件的高集成密度及多層式胞,該切換元件係以三維(3D)的結構形成,且該電阻元件係以堆疊的結構形成。
一種示例性可變電阻式記憶體元件可包含:一基底層;一柱狀閘極電極,係形成於該基底層上,且以實質地垂直該基底層之一表面延伸;一電流傳輸層,係形成來圍繞該柱狀閘極電極;一可變電阻層,係形成於該電流傳輸層之一外部;以及一阻斷層,係配置成基於施加至該柱狀閘極電極的一電壓,而阻斷流經該電流傳輸層的電流之一路徑,以及使流經該電流傳輸層之電流轉向至該可變電阻層。
一種示例性可變電阻式記憶體元件可包含:一基底層;一柱狀閘極電極,係形成於該基底層上,且以實質地垂直該基底層之一表面延伸;複數位元線,係與複數絕緣層交替地堆疊於該柱狀閘極電極之周圍;複數可變電阻層,係形成於該等位元線之外部;以及複數阻斷層,係配置成基於施加至該柱狀閘極電極的一電壓,而阻斷流經該等位元線之電流的路徑,以及使流經該等位元線之電流轉向至該等可變電阻層。
一種驅動示例性可變電阻式記憶體元件之方法,該方法包含:形成一柱狀電極閘極於一基板上;形成一位元線來圍繞該柱狀閘極電極;形成一可變電阻層於該位元線之一外部;以及基於施加至該柱狀閘極電極的一電壓,將流經該位元線之一電流的一路徑改變成流經該可變電阻層之一電流的一路徑。
這些及其他特徵、態樣及實施例係說明於下面的「實施方式」
部分。
10‧‧‧變電阻式記憶體元件
20‧‧‧接面電晶體
30‧‧‧可變電阻
110‧‧‧位元線層
110a‧‧‧位元線層
110b‧‧‧位元線層
110c‧‧‧位元線層
110d‧‧‧位元線層
115‧‧‧絕緣層
120‧‧‧閘極電極
1200‧‧‧閘極電極
1210‧‧‧矽化物層
1230‧‧‧閘極絕緣層
1240‧‧‧P型摻雜層
1250‧‧‧通道區域
125‧‧‧空乏層
130‧‧‧可變電阻層
135‧‧‧插入層
140‧‧‧字元線
BL1-BL4‧‧‧位元線
H1‧‧‧第一孔洞
H2‧‧‧第二孔洞
I‧‧‧寫入電流
P‧‧‧路徑
WL1-WL4‧‧‧字元線
上述及本發明所揭露的標的之其他態樣、特徵及其他優點將自以下詳細說明並配合附圖而被更清楚地理解。
第1圖係顯示示例性可變電阻式記憶體元件之電路圖。
第2圖係顯示示例性3D可變電阻式記憶體元件之電路圖。
第3A圖及第3B圖係顯示示例性可變電阻式記憶體元件之平面視圖。
第4A圖至第7B圖係顯示製造示例性可變電阻式記憶體元件之剖視圖。
第8圖及第9圖係顯示示例性可變電阻式記憶體元件。
第10圖及第11圖係顯示示例性可變電阻式記憶體元件。
在下文中,示例性實施例將參考配合附圖而被更加詳細地說明。
示例性實施例於文中係以剖面圖示來說明,其中該剖面圖式係示例性實施例(及中間結構)的示意圖。就其真正的意義來說,結果該等圖式形狀的變化係可被預期的,例如製造技術及/或公差。因此,示例性實施例不應被理解為限制文中所示區域的特定形狀,而是例如從製造可包含形狀誤差之結果。通過本發明揭露,元件符號在不同的圖示及示例性實施例中直接地與相似部分的元件符號一致。在該等圖式中相似元件符號代表相似元件。應該容易地了解在本發明所揭露的“在...之上(on)”及“在...上面(over)”的意思應被擴大解釋,亦即“在...之上”不僅意指“直接地在...之上”,而是具有一中間物特徵的某構件或是在該(等)層之間的某構件;又“在...上面”不僅意指直接設於頂部,而是設於具有一
中間物特徵的某構件或是在該(等)層之間的某構件之頂部。
請參閱第1圖,一可變電阻式記憶體元件10包含複數字元線WL1至WL4、一位元線BL、一接面電晶體20及一可變電阻30。該等字元線WL1至WL4及該位元線BL係彼此交叉設置。該接面電晶體20係為一切換元件,且該接面電晶體20係連接以使該等字元線WL1至WL4及該字元線BL互相連接。該可變電阻30可以並聯連接該接面電晶體20。亦即,該可變電阻30可連接至該接面電晶體20的源級與汲極之間。如眾所知,從該閘極電極施加逆向偏壓至PN接面,使得該接面電晶體20藉由擴展一空乏層來執行切換以使載子通過,其中該空乏層係為產生於形成在靠近一通道區域的PN接面。
複數位元線BL可被提供在作為一單胞區域之一分區空間中,且該等位元線可如第2圖所示的堆疊方式安排設置。
如第3A圖及第3B圖所示,在包含一接面電晶體的一示例性可變電阻式記憶體元件中,一位元線層110係形成於一閘極電極120的周圍。一可變電阻層130可形成於該位元線層110的邊緣。
該閘極電極120可具有一柱狀結構,該柱狀結構是以實質地垂直一基底層(圖未示)的方向延伸。該閘極電極120可包含一第一導電式半導體層,例如一P型摻雜半導體層。該位元線層110可形成於該閘極電極120的一側,且可包含一第二導電式半導體層,例如一N型摻雜半導體層,以與該閘極電極120形成一PN接面。在該示例性實施例中,該閘極電極120可由一P型多晶矽層所形成,且該位元線層110可由一N型多晶矽層所形成。
一空乏層125可被形成於該閘極電極120及該位元線層110之
間的一界面中。該空乏層125的(區域)大小可根據該閘極電極120的施加電壓而改變。如眾所知,當施加一逆向偏壓至該閘極電極120時,該空乏層的區域可被擴展,使該空乏層125可干擾電流。在此,字元線WL1、WL2、WL3及WL4可被連接至該閘極電極120,且實質地垂直該位元線。另外,為了更清楚表示,在第3B圖中,省略該等字元線WL1、WL2、WL3及WL4的圖式。
亦即,如第3B圖所示,施加一逆向偏壓(-V)至一已選定閘極電極120,且其他閘極電極120係浮動的。一預定電流,例如一寫入電流I,係被施加通過該位元線層110。
基於施加逆向偏壓至該已選定閘極120,圍繞該已選定閘極電極120之空乏層125的區域被擴展。因此,流經該位元線層110的寫入電流I被該空乏層120阻斷,而繞過所形成的可變電阻層130以與該位元線層110連接。亦即,該寫入電流I的路徑P已改變。
由於施加該寫入電流I至對應該已選定閘極電極120的可變電阻層130,該可變電阻層130的電阻係藉由該寫入電流I而改變。因此,「0」或「1」的資料係寫入該可變電阻層130。
一示例性可變電阻式記憶體元件的製造方法將參考第4A圖至第7B圖而被詳細說明如下。在此,第4A圖、第5A圖、第6A圖及第7A圖係為沿著平行該示例性可變電阻式記憶體元件之一字元線的方向之剖視圖,而第4B圖、第5B圖、第6B圖及第7B圖係為沿著平行該示例性可變電阻式記憶體元件之一位元線的方向之剖視圖。
首先,複數位元線層110a、110b、110c及110d係與絕緣層115
依序堆疊於一基底層100上,其中各該絕緣層115係插入至該等位元線層110a、110b、110c及110d之間。換句話說,該等位元線層110a、110b、110c及110d與該等絕緣層115係交替地堆疊於該基底層100上。在此,該基底層100可為形成於一半導體基板(圖未示)上之一絕緣層。
請參閱第5A圖及第5B圖,該等位元線層110a、110b、110c及110d與該等絕緣層115之預定部分為了一閘極電極(圖未示)而被佈局圖樣以形成一貫通孔。接著,舉例來說,一P型多晶矽層可被形成於該貫通孔中以形成一閘極電極120。該P型多晶矽層可藉由一已知沉積製程及一已知拋光製程而形成。
請參閱第6A圖至第6B圖,為了定義一單位記憶胞區域,該等位元線層110a、110b、110c及110d的預定部分(在下文中,將其稱作複數位元線)及該等絕緣層115係佈局圖樣以形成一第一孔洞H1。當以平行該字元線的方向觀之,該第一孔洞H1可被配置於該閘極電極120之二側(見於第6A圖)。接著,透過該第一孔洞H1而暴露的位元線層110a、110b、110c及110d係凹進一預定厚度以形成複數第二孔洞H2。該凹孔製程可使用一已知蝕刻製程來完成。
請參閱第7A圖及第7B圖,可變電阻層130係選擇地埋在該等第二孔洞H2中。該等可變電阻層130可被例如作為用於一ReRAM的材料之一PCMO(Pr1-xCaxMnO3)層、作為用於一PCRAM的材料之一硫化層、作為用於一MRAM的材料之一磁性層、作為用於自旋轉移力矩隨機存取記憶體(STTMRAM,spin-transfer torque magnetoresistive RAM)的材料之一磁化反轉元件層,或作為用於一聚合物隨機存取記憶體(PoRAM,polymer RAM)的材料之一
聚合物層可被使用。然後,一插入層135係形成於該第一孔洞H1中以得到分離的胞變成單胞單元。接著,一字元線140係形成以電性連接至該閘極電極120。
在該示例性實施例中,於具有柱狀結構的閘極電極120形成之後,該等位元線層110a、110b、110c及110d係形成來圍繞該閘極電極120。此時,該等空乏層125可形成於該閘極電及120與該等位元線層110a、110b、110c及110d之間。該等空乏層125藉由施加至該閘極電極120之一足夠的逆向偏壓而被夾止。因此,該寫入電流I之路徑P或該讀取電流之路徑P係繞過該可變電阻層130,而執行該記憶操作。
如第8圖及第9圖所示,一閘極電極1200可由一金屬柱體所形成,且一矽化層1210可形成於金屬的閘極電極1200與各該位元線層110a、110b、110c及110d之間的一接合界面中,以造成該矽化層1210與各該位元線層110a、110b、110c及110d之間的一空乏層。
上述結構可藉由在第5A圖及第5B圖的製程中之貫通孔中的一耐火金屬層而獲得,而非在P型多晶矽層,且藉由使形成於該耐火金屬層的閘極電極1200所形成具有一預定厚度的矽化層1210反應(例如熱處理),且一N型多晶矽層作為用於該等位元線層110a、110b、110c及110d之一材料。
另外,如第10圖及第11圖所示之一示例性實施例中,一閘極電極1200可由一導電材料所形成,例如一金屬柱體。一P型摻雜層1240可被插入至該閘極電極1200與各該位元線層110a、110b、110c及110d之間,其中該等位元線包含一N型多晶矽層。在此,該P型摻雜層1240可為由各該位元線層110a、110b、110c及110d所形成之一摻雜層。
上述結構造成一通道區域1250,其由於施加至該閘極電極1200的偏壓大於一臨界電壓,而擴展該P型摻雜層1240以與一可變電阻層130接觸。
該通道區域1250藉由阻斷該電流路徑以作用為繞過流通該位元線層110至該可變電阻層130的一電流路徑。
因此,可實現該可變電阻層130之一記憶操作。
一閘極絕緣層1230可被插入至該閘極電極1200及該P型摻雜層1240之間。舉例來說,該P型摻雜層1240可藉由一傾斜離子植入程序而被形成至該等位元線層110a、110b、110c及110d,在該閘極電極1200形成之前,該等位元線層110a、110b、110c及110d係透過該貫通孔之一側壁而暴露。
如上所述,該記憶操作亦可藉由繞過通過該通道區域之延伸的電流路徑而被實現。
上述示例性實施例係用於說明,而不限與此。各種替代及相同係有可能的。本發明並不限於此所說明之示例性實施例。本發明也不限制任何特定形式的半導體元件。鑑於本發明所揭露之顯而易見的其他增加、減少或修改,都將落入該等所附申請專利範圍中。
110‧‧‧位元線層
120‧‧‧閘極電極
125‧‧‧空乏層
130‧‧‧可變電阻層
P‧‧‧路徑
Claims (6)
- 一種可變電阻式記憶體元件,包含:一基底層;一柱狀閘極電極,係形成於該基底層上,且以實質地垂直該基底層之一表面延伸;一電流傳輸層,係形成來圍繞該柱狀閘極電極;一可變電阻層,係形成於該電流傳輸層之一外部;以及一阻斷層,係配置成:基於施加至該柱狀閘極電極的一電壓,而阻斷流經該電流傳輸層的電流之一路徑,以及使流經該電流傳輸層之電流轉向至該可變電阻層,其中該柱狀閘極電極係由一導電材料所形成,以及該電流傳輸層係由一預定導電式半導體層所形成,以及更包含:一接面層,係插入至該柱狀閘極電極及該電流傳輸層之間;以及一閘極絕緣層,係插入至該柱狀閘極電極及該接面層之間。
- 如申請專利範圍第1項所述之可變電阻式記憶體元件,其中該接面層係形成以具有與該電流傳輸層之一導電性相反的一導電性,以及基於施加至該柱狀閘極電極之電壓,該接面層形成一通道以作為該阻斷層。
- 如申請專利範圍第1項所述之可變電阻式記憶體元件,其中該基底層包含一絕緣材料。
- 一種可變電阻式記憶體元件,包含:一基底層;一柱狀閘極電極,係形成於該基底層上,且以實質地垂直該基底層之一表面延伸;複數位元線,係與複數絕緣層交替地堆疊於該柱狀閘極電極之周圍;複數可變電阻層,係形成於該等位元線之外部;以及複數阻斷層,係配置成:基於施加至該柱狀閘極電極的一電壓,而阻斷流經該等位元線之電流路徑,以及使流經該等位元線之電流轉向至該等可變電阻層,其中該柱狀閘極電極係由一導電材料所形成,以及該等位元線係由一預定導電式半導體層所形成,以及更包含:複數接面層,係插入至該柱狀閘極電極及該等位元線之間;以及一閘極絕緣層,係插入至該柱狀閘極電極及各該接面層之間。
- 如申請專利範圍第4項所述之可變電阻式記憶體元件,其中該等接面層係形成以具有與該等位元線之一導電性相反的一導電性,以及基於施加電壓至該柱狀閘極電極,該等接面層形成通道以作為該等阻斷層。
- 如申請專利範圍第4項所述之可變電阻式記憶體元件,其中該基底層包含一絕緣材料。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020130027872A KR20140113024A (ko) | 2013-03-15 | 2013-03-15 | 저항 변화 메모리 장치 및 그 구동방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201436192A TW201436192A (zh) | 2014-09-16 |
TWI597833B true TWI597833B (zh) | 2017-09-01 |
Family
ID=51504102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW102130596A TWI597833B (zh) | 2013-03-15 | 2013-08-27 | 可變電阻式記憶體元件 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9666642B2 (zh) |
KR (1) | KR20140113024A (zh) |
CN (1) | CN104051465B (zh) |
TW (1) | TWI597833B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11222923B2 (en) | 2019-01-16 | 2022-01-11 | Winbond Electronics Corp. | Resistance variable memory |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9418985B2 (en) * | 2013-07-16 | 2016-08-16 | Qualcomm Incorporated | Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology |
US9472281B1 (en) * | 2015-06-30 | 2016-10-18 | HGST Netherlands B.V. | Non-volatile memory with adjustable cell bit shape |
US9825100B2 (en) * | 2015-08-31 | 2017-11-21 | Toshiba Memory Corporation | Nonvolatile semiconductor memory device |
JP6656104B2 (ja) * | 2016-07-15 | 2020-03-04 | キオクシア株式会社 | 半導体記憶装置 |
KR20200014801A (ko) | 2017-06-02 | 2020-02-11 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치, 전자 부품, 및 전자 기기 |
JP7195068B2 (ja) | 2017-06-26 | 2022-12-23 | 株式会社半導体エネルギー研究所 | 半導体装置、電子機器 |
JP7265475B2 (ja) | 2017-06-27 | 2023-04-26 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US11374012B2 (en) | 2017-07-06 | 2022-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method of semiconductor device |
US10665604B2 (en) | 2017-07-21 | 2020-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, semiconductor wafer, memory device, and electronic device |
US10777566B2 (en) | 2017-11-10 | 2020-09-15 | Macronix International Co., Ltd. | 3D array arranged for memory and in-memory sum-of-products operations |
US10719296B2 (en) | 2018-01-17 | 2020-07-21 | Macronix International Co., Ltd. | Sum-of-products accelerator array |
US10957392B2 (en) | 2018-01-17 | 2021-03-23 | Macronix International Co., Ltd. | 2D and 3D sum-of-products array for neuromorphic computing system |
US10242737B1 (en) | 2018-02-13 | 2019-03-26 | Macronix International Co., Ltd. | Device structure for neuromorphic computing system |
US10635398B2 (en) | 2018-03-15 | 2020-04-28 | Macronix International Co., Ltd. | Voltage sensing type of matrix multiplication method for neuromorphic computing system |
JP2019165114A (ja) | 2018-03-20 | 2019-09-26 | 東芝メモリ株式会社 | 抵抗変化型記憶装置 |
KR102542998B1 (ko) * | 2018-06-26 | 2023-06-14 | 에스케이하이닉스 주식회사 | 3차원 적층형 반도체 메모리 소자 |
US11138497B2 (en) | 2018-07-17 | 2021-10-05 | Macronix International Co., Ltd | In-memory computing devices for neural networks |
US10664746B2 (en) | 2018-07-17 | 2020-05-26 | Macronix International Co., Ltd. | Neural network system |
US11636325B2 (en) | 2018-10-24 | 2023-04-25 | Macronix International Co., Ltd. | In-memory data pooling for machine learning |
US11562229B2 (en) | 2018-11-30 | 2023-01-24 | Macronix International Co., Ltd. | Convolution accelerator using in-memory computation |
US10672469B1 (en) | 2018-11-30 | 2020-06-02 | Macronix International Co., Ltd. | In-memory convolution for machine learning |
US11934480B2 (en) | 2018-12-18 | 2024-03-19 | Macronix International Co., Ltd. | NAND block architecture for in-memory multiply-and-accumulate operations |
KR102674883B1 (ko) * | 2018-12-21 | 2024-06-14 | 에스케이하이닉스 주식회사 | 적층된 셀 트랜지스터들을 포함하는 비휘발성 메모리 소자 및 상기 비휘발성 메모리 소자의 동작 방법 |
US11119674B2 (en) | 2019-02-19 | 2021-09-14 | Macronix International Co., Ltd. | Memory devices and methods for operating the same |
US10783963B1 (en) | 2019-03-08 | 2020-09-22 | Macronix International Co., Ltd. | In-memory computation device with inter-page and intra-page data circuits |
US11132176B2 (en) | 2019-03-20 | 2021-09-28 | Macronix International Co., Ltd. | Non-volatile computing method in flash memory |
US10910393B2 (en) | 2019-04-25 | 2021-02-02 | Macronix International Co., Ltd. | 3D NOR memory having vertical source and drain structures |
KR20210029870A (ko) | 2019-09-06 | 2021-03-17 | 삼성전자주식회사 | 정보 저장 구조물을 포함하는 반도체 소자 |
KR20210107304A (ko) | 2020-02-24 | 2021-09-01 | 삼성전자주식회사 | 수직형 가변 저항 메모리 장치 및 수직형 가변 저항 메모리 장치의 동작 방법 |
US11737274B2 (en) | 2021-02-08 | 2023-08-22 | Macronix International Co., Ltd. | Curved channel 3D memory device |
US11916011B2 (en) | 2021-04-14 | 2024-02-27 | Macronix International Co., Ltd. | 3D virtual ground memory and manufacturing methods for same |
US11710519B2 (en) | 2021-07-06 | 2023-07-25 | Macronix International Co., Ltd. | High density memory with reference memory using grouped cells and corresponding operations |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5604158A (en) * | 1993-03-31 | 1997-02-18 | Intel Corporation | Integrated tungsten/tungsten silicide plug process |
JP2008160004A (ja) * | 2006-12-26 | 2008-07-10 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP5091491B2 (ja) * | 2007-01-23 | 2012-12-05 | 株式会社東芝 | 不揮発性半導体記憶装置 |
KR100908819B1 (ko) * | 2007-11-02 | 2009-07-21 | 주식회사 하이닉스반도체 | 수직채널트랜지스터를 구비한 반도체소자 및 그 제조 방법 |
KR20090055874A (ko) * | 2007-11-29 | 2009-06-03 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
JP2009135328A (ja) * | 2007-11-30 | 2009-06-18 | Toshiba Corp | 不揮発性半導体記憶装置 |
KR101539697B1 (ko) * | 2008-06-11 | 2015-07-27 | 삼성전자주식회사 | 수직형 필라를 활성영역으로 사용하는 3차원 메모리 장치,그 제조 방법 및 그 동작 방법 |
KR20100001260A (ko) * | 2008-06-26 | 2010-01-06 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
JP5462490B2 (ja) * | 2009-01-19 | 2014-04-02 | 株式会社日立製作所 | 半導体記憶装置 |
US8829646B2 (en) * | 2009-04-27 | 2014-09-09 | Macronix International Co., Ltd. | Integrated circuit 3D memory array and manufacturing method |
KR101028993B1 (ko) | 2009-06-30 | 2011-04-12 | 주식회사 하이닉스반도체 | 3차원 구조의 비휘발성 메모리 소자 및 그 제조 방법 |
JP5388814B2 (ja) * | 2009-11-24 | 2014-01-15 | 株式会社東芝 | 半導体記憶装置 |
KR20110090056A (ko) * | 2010-02-02 | 2011-08-10 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
JP5079927B2 (ja) * | 2010-02-23 | 2012-11-21 | パナソニック株式会社 | 不揮発性メモリ装置の製造方法、不揮発性メモリ素子、および不揮発性メモリ装置 |
KR101623546B1 (ko) * | 2010-05-28 | 2016-05-23 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
US8289763B2 (en) * | 2010-06-07 | 2012-10-16 | Micron Technology, Inc. | Memory arrays |
KR20120030193A (ko) * | 2010-09-17 | 2012-03-28 | 삼성전자주식회사 | 3차원 반도체 장치의 제조 방법 |
KR20130046700A (ko) * | 2011-10-28 | 2013-05-08 | 삼성전자주식회사 | 3차원적으로 배열된 메모리 요소들을 구비하는 반도체 장치 |
KR101996020B1 (ko) * | 2012-02-08 | 2019-07-04 | 삼성전자주식회사 | 가변 저항 메모리 장치 및 그것의 쓰기 방법 |
KR101942274B1 (ko) * | 2012-02-13 | 2019-01-28 | 삼성전자주식회사 | 저항성 메모리 장치 |
KR20130112219A (ko) | 2012-04-03 | 2013-10-14 | 에스케이하이닉스 주식회사 | 적층형 메모리 장치 |
KR20140127577A (ko) * | 2013-04-25 | 2014-11-04 | 에스케이하이닉스 주식회사 | 3차원 저항 가변 메모리 장치 및 그 제조방법 |
KR102061694B1 (ko) * | 2013-10-14 | 2020-01-02 | 삼성전자주식회사 | 3차원 크로스 포인트 어레이를 갖는 반도체 메모리 소자 |
US9331088B2 (en) * | 2014-03-25 | 2016-05-03 | Sandisk 3D Llc | Transistor device with gate bottom isolation and method of making thereof |
-
2013
- 2013-03-15 KR KR1020130027872A patent/KR20140113024A/ko not_active Application Discontinuation
- 2013-07-25 US US13/950,681 patent/US9666642B2/en active Active
- 2013-08-27 TW TW102130596A patent/TWI597833B/zh active
- 2013-10-11 CN CN201310473523.3A patent/CN104051465B/zh active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11222923B2 (en) | 2019-01-16 | 2022-01-11 | Winbond Electronics Corp. | Resistance variable memory |
Also Published As
Publication number | Publication date |
---|---|
CN104051465B (zh) | 2018-11-02 |
KR20140113024A (ko) | 2014-09-24 |
CN104051465A (zh) | 2014-09-17 |
US9666642B2 (en) | 2017-05-30 |
US20140268996A1 (en) | 2014-09-18 |
TW201436192A (zh) | 2014-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI597833B (zh) | 可變電阻式記憶體元件 | |
US8283186B2 (en) | Magnetic memory device and method for manufacturing the same | |
TWI565111B (zh) | 磁性穿隧接面(mtj)自旋霍爾磁性隨機存取記憶體(mram)位元胞及陣列 | |
US9337239B2 (en) | Electronic device having flash memory array formed in at different level than variable resistance memory cells | |
TWI508250B (zh) | 記憶體單元結構 | |
JP7168241B2 (ja) | 集積回路装置 | |
US9620565B2 (en) | Semiconductor memory device | |
TWI565045B (zh) | 多位元鐵電性記憶體裝置及其製造方法 | |
US20100019297A1 (en) | Multi-Stacked Spin Transfer Torque Magnetic Random Access Memory and Method of Manufacturing the Same | |
US20190229264A1 (en) | Conductive bridge random access memory (cbram) devices with low thermal conductivity electrolyte sublayer | |
US20200144293A1 (en) | Ferroelectric field effect transistors (fefets) having ambipolar channels | |
KR20200066848A (ko) | 스핀-궤도 토크 라인을 갖는 반도체 소자 | |
US10325651B2 (en) | 3D semiconductor device with stacked memory | |
KR20150091944A (ko) | 자기 메모리 소자 | |
JP6606177B2 (ja) | 金属カルコゲナイドを含むデバイス | |
CN104103754A (zh) | 三维可变电阻存储器件及其制造方法 | |
KR20140102993A (ko) | 증가된 온/오프 비를 갖는 자기 메모리 소자와 그 제조 및 동작방법 | |
JP2012256693A (ja) | 半導体記憶装置 | |
JP5386528B2 (ja) | 半導体記憶装置およびその製造方法 | |
TW201709367A (zh) | 用於低功率非揮發絲切換器的熱管理結構 | |
JP2013069753A (ja) | 半導体記憶装置およびその製造方法 | |
KR100979350B1 (ko) | 마그네틱 램 및 그 제조 방법 | |
JP2006332671A (ja) | 相変化記憶素子及びその製造方法 | |
JP2007157823A (ja) | 磁気記憶装置 | |
US9520447B2 (en) | Memory cells having a common gate terminal |