US11222923B2 - Resistance variable memory - Google Patents

Resistance variable memory Download PDF

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US11222923B2
US11222923B2 US16/666,421 US201916666421A US11222923B2 US 11222923 B2 US11222923 B2 US 11222923B2 US 201916666421 A US201916666421 A US 201916666421A US 11222923 B2 US11222923 B2 US 11222923B2
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variable resistance
variable
voltage
transistor
resistance
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US20200227476A1 (en
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Yasuhiro Tomita
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Winbond Electronics Corp
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • H01L27/249—
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    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
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    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
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    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
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    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
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    • G11C13/0021—Auxiliary circuits
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    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
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    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • H01L45/1206—
    • H01L45/1253—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/253—Multistable switching devices, e.g. memristors having three or more terminals, e.g. transistor-like devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0045—Read using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0078—Write using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
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    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/78—Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
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    • G11C2213/70—Resistive array aspects
    • G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

Definitions

  • the disclosure relates to a resistance variable memory using a variable resistance element, and more particularly to a three-dimensional structure of a memory array.
  • a resistance variable random access memory may randomly select a memory cell according to a column address and a row address, and read data from the selected memory cell or write data to the selected memory cell.
  • a memory cell MC includes a variable resistance element and a transistor connected in series therewith. The gate of the transistor is electrically connected to the word line; the drain region is electrically connected to one electrode of the variable resistance element; the source region is electrically connected to the source line; and another electrode of the variable resistance element is electrically connected to the bit line.
  • SET set
  • RESET reset
  • a resistance variable memory includes a unipolar type and a bipolar type.
  • the unipolar type the polarities of the write voltages applied to the variable resistance element at the time of set and reset are the same, and the set or reset is performed by changing the magnitude of the write voltage.
  • the bipolar type the polarities of the write voltages applied to the variable resistance element at the time of set and reset are reversed.
  • a transition metal oxide such as hafnium oxide
  • the forming operation is to apply a voltage slightly larger than that when write is performed to the variable resistance element to a thin film so that the transition metal oxide film is converted from an insulating state to a variable resistance state (such as Japanese Patent No. 5748877).
  • a bipolar resistance variable memory it is necessary to dispose a bit line in a one-to-one relationship with a dedicated source line extending in the same direction as the bit line, with the ability to swap the symmetry of the bit line and the source line.
  • a layout may be a hindrance to high integration of a memory array.
  • FIG. 1A illustrates a part of a memory array including shared bit lines
  • FIG. 1B is a schematic cross-sectional diagram taken along a line X 1 -X 1
  • shared bit lines S_BL 1 and S_BL 2 and word lines WL 1 and WL 2 extend in the same direction
  • source lines SL 1 and SL 2 extend in a direction orthogonal thereto.
  • the shared bit line S_BL 1 is commonly connected to memory cells MC 1 and MC 3
  • the shared bit line S_BL 2 is commonly connected to memory cells MC 2 and MC 4 .
  • End portions of the shared bit line S_BL 1 and the shared bit line S_BL 2 are respectively connected to the bit line BL 1 and the bit line BL 2 (not shown), and the bit line BL 1 , the bit line BL 2 and the source line SL extend in the same direction.
  • two transistors of the memory cells MC 3 and MC 4 are formed in a p-type well W on a silicon substrate.
  • the gates of the two transistors are respectively connected to the word lines WL 1 and WL 2 ; the source regions share an n-type diffusion region; and the source regions are electrically connected to the source line SL 2 via contacts CT 11 , vias V 1 , vias V 2 , and an intermediate metal IM 1 and an intermediate metal IM 2 of the substrate.
  • the drain regions of the two transistors are respectively connected to corresponding variable resistance elements RE 3 and RE 4 via the contacts CT 12 and the intermediate metal IM 1 of the substrate, and the variable resistance element RE 3 is connected to the shared bit line S_BL 1 via the via hole contact V 1 .
  • the drain region of the variable resistance element RE 4 is also connected to the shared bit line S_BL 2 in the same manner.
  • a memory array employing shared source lines can provide improved high integration, but it is still limited by the pitch of the transistors. Therefore, in order to realize further high integration, it is necessary to further reduce the transistor size, but the size reduction of the transistor is approaching a limit.
  • the disclosure has been made to solve the above problems, and an object of the disclosure is to provide a resistance variable random access memory that can realize higher integration than conventional ones.
  • a resistance variable memory of the disclosure stores data in a reversible and non-volatile variable resistance element and includes: a plurality of transistors formed on a surface of a substrate; and a plurality of variable resistance elements stacked on the surface of the substrate in a vertical direction, one electrode of each of the plurality of variable resistance elements being commonly electrically connected to one electrode of one transistor, wherein another electrode of each of the plurality of variable resistance elements is electrically connected to a bit line, another electrode of each of the plurality of transistors is electrically connected to a source line, and each gate of transistors in a row direction is commonly connected to a word line.
  • a plurality of variable resistance elements are stacked on a surface of a substrate in a vertical direction, whereby high integration and high density of a memory array can be realized. Further, since a plurality of variable resistance elements share one transistor, compared with a memory cell formed by 1T ⁇ 1R, high integration and high density of the memory array can be realized. In addition, by simultaneously integrating a diode and a variable resistance element, interference at the time of read or write and the sneak current issue can be more effectively suppressed.
  • FIG. 1A is a circuit diagram of a part of a memory array including shared bit lines of a conventional resistance variable memory
  • FIG. 1B is a schematic cross-sectional diagram taken along the line X 1 -X 1 in FIG. 1A .
  • FIG. 2 is a block diagram showing a schematic configuration of a resistance variable random access memory according to an embodiment of the disclosure.
  • FIG. 3A is a circuit diagram of a part of a vertically stacked memory array according to the first embodiment of the disclosure
  • FIG. 3B is a schematic cross-sectional diagram taken along the line X 2 -X 2 in FIG. 3A .
  • FIG. 4 is a circuit diagram of a part of a vertically stacked memory array according to the second embodiment of the disclosure.
  • FIG. 5 is a diagram showing a bias voltage at the time of a read operation from the bit line side of the resistance variable memory according to the first embodiment of the disclosure.
  • FIG. 6 is a diagram showing a bias voltage at the time of a read operation from the source line side of the resistance variable memory according to the first embodiment of the disclosure.
  • FIG. 7 is a diagram showing a bias voltage at the time of a SET write operation of the resistance variable memory according to the first embodiment of the disclosure.
  • FIG. 8 is a diagram showing a bias voltage at the time of a RESET write operation of the resistance variable memory according to the first embodiment of the disclosure.
  • FIG. 9A shows an example of a diode integrated to a variable resistance element of a resistance variable memory according to a preferred embodiment of the disclosure
  • FIG. 9B is a graph showing a current-voltage (I-V) characteristic of the diode.
  • FIG. 10 is a diagram showing a bias voltage at the time of a read operation from the bit line side of the resistance variable memory according to the second embodiment of the disclosure.
  • FIG. 11 is a diagram showing a bias voltage at the time of a read operation from the source line side of the resistance variable memory according to the second embodiment of the disclosure.
  • FIG. 12 is a diagram showing a bias voltage at the time of a SET write operation of the resistance variable memory according to the second embodiment of the disclosure.
  • FIG. 13 is a diagram showing a bias voltage at the time of a RESET write operation of the resistance variable memory according to the second embodiment of the disclosure.
  • FIGS. 14A to 14J are diagrams for illustrating manufacturing steps of the resistance variable memory according to the first embodiment of the disclosure.
  • FIGS. 15A to 15G are diagrams for illustrating manufacturing steps of the resistance variable memory according to the second embodiment of the disclosure.
  • a resistance variable memory has a memory array with a three-dimensional structure in which variable resistance elements are stacked in a vertical direction.
  • FIG. 2 is a block diagram showing a schematic configuration of a resistance variable random access memory according to an embodiment of the disclosure.
  • a resistance variable memory 100 of the embodiment includes: a memory array 110 in which a plurality of memory cells including variable resistance elements and transistors are arranged in a matrix; a column decoder and driver circuit 120 which selects and drives word lines WL based on a column address X-Add; a row decoder and driver circuit 130 which generates a selection signal SSL/SBL for selecting global bit lines GBL and global source lines GSL based on a row address Y-Add; a row selection circuit 140 which respectively selects a connection between the global bit lines GBL and the bit lines BL and a connection between the global source lines GSL and the source lines SL based on the selection signal SSL/SBL; a control circuit 150 which controls each part based on a command CMD and data DQ received from the outside; sense amplifiers 160 which read read data of the memory cells via the GBL/BL; and write driver and read bias circuits
  • the memory array 110 includes an m number of sub-arrays 110 - 1 to 110 - m which are respectively and correspondingly connected to an m number of row selectors YMUX of the row selection circuit 140 .
  • the m number of row selectors YMUX are connected to the sense amplifiers 160 and the write driver and read bias circuits 170 , respectively.
  • Each of the sense amplifiers 160 is connected to the control circuit 150 via an internal data bus DO, and results read by the sense amplifiers 160 are output to the control circuit 150 via the internal data bus DO.
  • each of the write driver and read bias circuits 170 is connected to the control circuit 150 via an internal data bus DI, and each of the write driver and read bias circuits 170 receives the write data via the internal data bus DI.
  • FIG. 3A is a circuit diagram of a part of a memory array with a three-dimensional structure of the embodiment
  • FIG. 3B is a schematic cross-sectional diagram taken along the line X 2 -X 2 in FIG. 3A .
  • word lines WL 1 to WL 2 and bit lines BL 1 to BL 8 extend in parallel with one another, and source lines SL 1 to SL 2 extend in a direction orthogonal thereto.
  • the word line WL 1 is connected to gates of transistors Q 1 and Q 3
  • the word line WL 2 is connected to gates of transistors Q 2 and Q 4 .
  • four variable resistance elements are commonly connected to one transistor.
  • One electrode of each of the variable resistance elements RE 1 to RE 4 connected to the transistor Q 1 is commonly connected to one electrode of the transistor Q 1
  • another electrode of each of the variable resistance elements RE 1 to RE 4 is connected to the bit lines BL 1 to BL 4 , respectively.
  • the four variable resistance elements connected to the transistor Q 3 are also configured in the same manner.
  • one electrode of each of the four variable resistance elements connected to the transistor Q 2 is commonly connected to one electrode of the transistor Q 2 , and another electrode of each of the four variable resistance elements connected to the transistor Q 2 is connected to the bit lines BL 5 to BL 8 , respectively.
  • the four variable resistance elements connected to the transistor Q 4 are also configured in the same manner.
  • another electrode of the transistor Q 1 and another electrode of the transistor Q 2 are commonly connected, and the connection node thereof is connected to the source line SL 1 ; another electrode of the transistor Q 3 and another electrode of the transistor Q 4 are commonly connected, and the connection node thereof is connected to the source line SL 2 .
  • the memory array structure of the disclosure is configured, for example, by using a multilayer wiring structure on a silicon substrate.
  • n-type diffusion regions for serving as source/drain electrodes of the transistors are formed in a P-type well W on the silicon substrate.
  • the word lines WL 1 to WL 2 connected to the gates of the transistors are formed, for example, by a polysilicon layer.
  • the four variable resistance elements commonly connected to one transistor are stacked on the silicon substrate in the vertical direction by using five layers of metal wiring.
  • An interlayer insulating film is formed on the polysilicon layer forming the word lines WL 1 to WL 2 , and a first-layer metal wiring is formed thereon.
  • the first-layer metal wiring forms the source line SL 2 and an intermediate metal IM 1 , and a shared n-type diffusion region of the transistors Q 3 and Q 4 is electrically connected to the source line SL 2 via a contact CT 11 for the substrate formed on the interlayer insulating film. Further, another n-type diffusion region of each of the transistors Q 3 and Q 4 is electrically connected to the corresponding intermediate metal IM 1 via a contact CT 12 for the substrate formed on the interlayer insulating film.
  • An interlayer insulating film is formed on the first-layer metal wiring, and a second-layer metal wiring is formed on the interlayer insulating film.
  • the second-layer metal wiring forms the bit line BL 1 and an intermediate metal IM 2 .
  • the intermediate metal IM 2 has the same shape as the intermediate metal IM 1 and is formed at a position above the intermediate metal IM 1 and partially shifting away therefrom, and the bit line BL 1 is formed on the intermediate metal IM 1 .
  • a contact V 11 is formed in the interlayer insulating film between the intermediate metal IM 1 and the intermediate metal IM 2 .
  • the variable resistance element RE 1 and a contact V 12 are formed in the interlayer insulating film between the intermediate metal IM 1 and the bit line BL 1 .
  • the variable resistance element includes, for example, a transition metal oxide (TMO), such as hafnium oxide.
  • An interlayer insulating film is formed on the second-layer metal wiring, and a third-layer metal wiring is formed on the interlayer insulating film.
  • the third-layer metal wiring forms the bit line BL 2 and an intermediate metal IM 3 , and the intermediate metal IM 3 has the same shape as the intermediate metal IM 1 and is formed at a corresponding position above the intermediate metal IM 1 , and the bit line BL 2 is formed on the intermediate metal IM 2 .
  • a contact V 21 is formed in the interlayer insulating film between the intermediate metal IM 1 and the intermediate metal IM 2 .
  • the variable resistance element RE 2 and a contact V 22 are formed in the interlayer insulating film between the intermediate metal IM 2 and the bit line BL 2 .
  • a fourth-layer metal wiring forms the bit line BL 3 and an intermediate metal IM 4
  • a fifth-layer metal wiring forms the bit line BL 4 .
  • the four variable resistance elements RE 1 to RE 4 stacked in the vertical direction from the surface of the semiconductor substrate are formed.
  • the transistor Q 3 is turned on via the word line WL 1 , and a read voltage is applied to the bit line BL 3 , and GND is applied to the source line SL 2 .
  • variable resistance element RE 3 When the variable resistance element RE 3 is in a high resistance state, a small current flows from the bit line BL 3 to the source line SL 2 , and if the variable resistance element RE 3 is in a low resistance state, a large current flows from the bit line BL 3 to the source line SL 2 .
  • the detailed operations of read or write will be described later.
  • a plurality of variable resistance elements can be stacked on the surface of the semiconductor substrate in the vertical direction, and the plurality of stacked variable resistance elements share one transistor, so high integration and high density of the memory array can be realized.
  • variable resistance elements are commonly connected to one transistor
  • the disclosure is not limited thereto; for example, two or three variable resistance elements may be commonly connected to one transistor, or five or more variable resistance elements may be commonly connected.
  • the number of stacked metal wirings also changes depending on the number of stacked variable resistance elements.
  • FIG. 4 shows the configuration of the memory array of the second embodiment, and here, eight transistors and 32 variable resistance elements connected thereto are shown.
  • This embodiment is different from the first embodiment in that the bit lines are parallel to the source lines, and the word lines extend in a direction orthogonal thereto. In such a configuration, since the bit lines are parallel to the source lines, the layout is easier than in the first embodiment.
  • four variable resistance elements are also connected to one transistor, and the four variable resistance elements are stacked in the vertical direction from the surface of the semiconductor substrate by five layers of metal wirings.
  • FIG. 5 shows a bias voltage when read is performed from the bit line side in the memory array of the first embodiment.
  • a read voltage VWLREAD is applied to the selected word line WL 1 so that the transistor connected to the selected word line WL 1 is turned on.
  • 0 V is applied to the unselected word line WL 2 so that the transistor connected to the unselected word line WL 2 is turned off.
  • a read voltage VBLREAD is applied to the bit line BL 1 of the selected variable resistance element connected to the selected transistor, and an inhibit voltage INHIBIT is applied to the bit lines BL 2 to BL 4 of other unselected variable resistance elements commonly connected to the selected transistor.
  • the inhibit voltage INHIBIT is applied via the diode to suppress a sneak current.
  • 0 V is applied to the selected source line SL 3 .
  • the bit lines BL 5 to BL 8 of the unselected variable resistance elements connected to the unselected transistor are applied with 0 V or are set to a floating state F, and the unselected source lines SL 1 to SL 2 and SL 4 are set to the floating state F or are applied with the read voltage VBLREAD.
  • the inhibit voltage INHIBIT applied to the bit lines BL 2 to BL 4 of the remaining three unselected variable resistance elements connected to the selected transistor is an intermediate voltage lower than the read voltage VBLREAD and higher than 0 V applied to the source lines.
  • the bias voltage required for reading is not applied to the unselected three variable resistance elements from the unselected bit lines BL 2 to BL 4 .
  • a large bias voltage is applied from the selected variable resistance element to the unselected variable resistance elements, or when the unselected variable resistance elements are in a low resistance state, it is ensured that the current does not flow into them.
  • the read voltage VBLREAD is applied to the selected variable resistance element from the bit line side, and the sense amplifier 160 reads out a voltage or current corresponding to the high resistance state or the low resistance state of the selected variable resistance element.
  • FIG. 6 shows a bias voltage when read is performed from the source line side in the memory array of the first embodiment.
  • the read voltage VWLREAD is applied to the selected word line WL 1
  • 0 V is applied to the unselected word line WL 2 .
  • 0 V is applied to the bit line BL 1 of the selected variable resistance element connected to the selected transistor
  • an inhibit voltage INHIBIT is applied to the bit lines BL 2 to BL 4 of other unselected variable resistance elements commonly connected to the selected transistor.
  • the inhibit voltage INHIBIT is applied via the diode to suppress a sneak current.
  • a read voltage VSLREAD is applied to the selected source line SL 3 .
  • the bit lines BL 5 to BL 8 of the unselected variable resistance elements connected to the unselected transistor are applied with 0 V or are set to the floating state F, and the unselected source lines SL 1 to SL 2 and SL 4 are applied with 0 V.
  • the sense amplifier 160 reads out a voltage or current corresponding to the high resistance state or the low resistance state of the selected variable resistance element.
  • a write voltage VWLSET is applied to the selected word line WL 1 so that the transistor connected to the selected word line WL 1 is turned on.
  • 0 V is applied to the unselected word line WL 2 so that the transistor connected to the unselected word line WL 2 is turned off.
  • a write voltage VBLSET is applied to the bit line BL 1 of the selected variable resistance element connected to the selected transistor, and the bit lines BL 2 to BL 4 of other unselected variable resistance elements commonly connected to the selected transistor are set to the floating state F or are applied with the inhibit voltage INHIBIT.
  • 0 V is applied to the selected source line SL 3 .
  • bit lines BL 5 to BL 8 of the unselected variable resistance elements connected to the unselected transistor are set to the floating state F or are applied with 0 V, and the unselected source lines SL 1 to SL 2 and SL 4 are applied with the write voltage VBLSET or are set to the floating state F.
  • the bit lines BL 2 to BL 4 of the unselected variable resistance elements commonly connected to the selected transistor are set to the floating state F or are applied with the inhibit voltage INHIBIT, whereby the unselected variable resistance elements are not applied with a SET write bias voltage, and only the selected variable resistance element is applied with the SET write bias voltage, and the selected variable resistance element becomes the low resistance state.
  • the inhibit voltage INHIBIT is an intermediate voltage lower than the write voltage VBLSET and higher than 0 V, it is possible to suppress the unselected variable resistance elements from being affected by the application of the SET write bias voltage.
  • a write voltage VWLRESET is applied to the selected word line WL 1 so that the transistor connected to the selected word line WL 1 is turned on.
  • 0 V is applied to the unselected word line WL 2 so that the transistor connected to the unselected word line WL 2 is turned off.
  • 0 V is applied to the bit line BL 1 of the selected variable resistance element connected to the selected transistor, and the bit lines BL 2 to BL 4 of other unselected variable resistance elements commonly connected to the selected transistor are set to the floating state F or are applied with the inhibit voltage INHIBIT.
  • a write voltage VSLRESET is applied to the selected source line SL 3 .
  • the bit lines BL 5 to BL 8 of the unselected variable resistance elements connected to the unselected transistor are set to the floating state F or are applied with 0 V, and the unselected source lines SL 1 to SL 2 and SL 4 are applied with 0 V.
  • the bit lines BL 2 to BL 4 of the unselected variable resistance elements commonly connected to the selected transistor are set to the floating state F or are applied with the inhibit voltage INHIBIT, whereby the unselected variable resistance elements are not applied with a RESET write bias voltage, and only the selected variable resistance element is applied with the RESET write bias voltage, and the selected variable resistance element becomes the high resistance state.
  • the inhibit voltage INHIBIT is an intermediate voltage lower than the write voltage VSLRESET and higher than 0 V, it is possible to suppress the unselected variable resistance elements from being affected by the application of the RESET write bias voltage.
  • the inhibit voltage INHIBIT is applied to the unselected bit lines, but with the high integration development of the memory array, the bias voltage control may not be sufficient to prevent interference. Therefore, in another embodiment, a diode SEL can be integrated with all of the variable resistance elements to prevent an undesired current from flowing to the unselected variable resistance elements.
  • the diode SEL is, for example, simultaneously formed when a variable resistance element RE is formed in a via hole formed in a lower electrode of the interlayer insulating film.
  • a first electrode of the variable resistance element RE, a transition metal oxide of the variable resistance element RE, a second electrode of the variable resistance element RE, the diode SEL, and a metal plug may be sequentially formed in the via hole, wherein the diode SEL includes, for example, a stack of a p-type semiconductor layer and an n-type semiconductor layer.
  • the bit line and the intermediate metal are electrically connected via the variable resistance element RE, the diode SEL, and the metal plug in the via hole.
  • the diode SEL may also be formed on both sides of the second electrode of the variable resistance element or formed on both sides of the first electrode and the second electrode.
  • FIG. 9B is a graph showing an I-V characteristic of the diode SEL.
  • the diode SEL has a characteristic of flowing a forward current when a forward bias voltage is greater than a threshold, and flowing a reverse current when a reverse bias voltage is greater than a threshold. Therefore, by applying an inhibit voltage, which is lower than the threshold voltage that causes the diode SEL to flow the forward/reverse current, to the bit lines of the unselected variable resistance elements, interference or the sneak current at the time of read or write can be more effectively suppressed.
  • FIG. 10 shows the bias voltage at the time of the read operation from the bit line side
  • FIG. 11 shows the bias voltage at the time of the read operation from the source line side
  • FIG. 12 shows the bias voltage at the time of the SET write operation
  • FIG. 13 shows the bias voltage at the time of the RESET write operation.
  • the diode and the variable resistance element may be simultaneously integrated to more effectively suppress interference with the unselected variable resistance elements at the time of read and write.
  • FIG. 14A is a plan view showing the case where eight transistors are formed on the substrate.
  • n-type diffusion regions AA are formed, and the word lines WL including conductive polysilicon are formed in the row direction via a gate oxide film so as to be aligned therewith.
  • An interlayer insulating film is formed on the entire substrate, and the contact holes CS for exposing the n-type diffusion regions AA are formed in the interlayer insulating film.
  • the first-layer metal wiring M 1 (indicated by a solid line in the figure) is formed on the interlayer insulating film.
  • the first-layer metal wiring M 1 includes: the source line SL that extends in the column direction and is electrically connected to the n-type diffusion regions (sources) between the two word lines via the contact holes CS, and the rectangular intermediate metal IM 1 that is spaced apart from the source line SL in the row direction, extends in the row direction for a certain length and is electrically connected to the n-type diffusion regions (drains) on the outer side of the two word lines via the contact holes CS.
  • the source line SL and the intermediate metal IM 1 may be directly electrically connected to the n-type diffusion regions, or may be electrically connected to the n-type diffusion regions via a barrier metal or the like in the contact holes.
  • an interlayer insulating film is formed on the entire substrate, and two via holes for exposing the intermediate metal IM 1 are formed in the interlayer insulating film.
  • a metal plug for electrically connecting to a second-layer metal wiring M 2 is buried in one of the via holes to form a via hole V 11 .
  • the variable resistance element RE 1 and a via hole V 12 are buried in the other via hole.
  • variable resistance element RE 1 the variable resistance element RE 1 , the diode, and the via hole V 12 are sequentially buried in the other via hole, wherein the diode may be formed, for example, by stacking a p-type polysilicon layer and an n-type polysilicon layer on the variable resistance element RE 1 .
  • the second-layer metal wiring M 2 (indicated by a solid line in the figure) is formed.
  • the second-layer metal wiring M 2 includes the bit line BL 1 extending in the column direction on the intermediate metal IM 1 , and the intermediate metal IM 2 spaced apart from the bit line BL 1 in the row direction and extending in the row direction for a certain length.
  • the bit line BL 1 is electrically connected to the variable resistance element RE 1 via the via hole V 12 .
  • the intermediate metal IM 2 is electrically connected to the intermediate metal IM 1 via the via hole V 11 , and has the same shape as the intermediate metal IM 1 , but is slightly shifted from the intermediate metal IM 1 in the row direction.
  • variable resistance element RE 2 and a via hole V 22 are buried in the other via hole.
  • the variable resistance element RE 2 , the diode, and the via hole V 22 are sequentially buried in the other via hole.
  • the variable resistance element RE 2 is, for example, disposed at a position (a position which is line-symmetric in the column direction) where the variable resistance element RE 1 is reversed by 180 degrees in the row direction with the via hole V 21 as the center.
  • the third-layer metal wiring M 3 (indicated by a solid line in the figure) having the same wiring pattern as that of the first-layer metal wiring M 1 is formed, and the metal wiring M 3 forms the intermediate metal IM 3 and the bit line BL 2 .
  • the bit line BL 2 is electrically connected to the variable resistance element RE 2 via the via hole V 22
  • the intermediate metal IM 3 is electrically connected to the intermediate metal IM 2 via the via hole V 21 .
  • the variable resistance element RE 3 and a via hole V 32 are formed on the intermediate metal IM 3 , and a via hole V 31 is formed.
  • a fourth-layer metal wiring M 4 (indicated by a solid line in the figure) having the same wiring pattern as that of the second-layer metal wiring M 2 is formed, and the metal wiring M 4 forms the intermediate metal IM 4 and the bit line BL 3 .
  • the bit line BL 3 is electrically connected to the variable resistance element RE 3 via the via hole V 32
  • the intermediate metal IM 4 is electrically connected to the intermediate metal IM 3 via the via hole V 31 .
  • the variable resistance element RE 4 and a via hole V 42 are formed on the intermediate metal IM 4 .
  • a fifth-layer metal wiring M 5 (indicated by a solid line in the figure) is formed.
  • the metal wiring M 5 forms the bit line BL 4 .
  • the bit line BL 4 is electrically connected to the variable resistance element RE 4 via the via hole V 42 .
  • the resistance variable memory of the first embodiment including eight transistors and 32 variable resistance elements is formed by five layers of multilayer metal wirings.
  • variable resistance elements are formed in the via holes on the intermediate metals, but the disclosure is not limited thereto.
  • the variable resistance elements may be formed on the intermediate metals by patterning first, and then the via holes electrically connected thereto may be formed on the variable resistance elements later.
  • the size of the variable resistance element is not limited by the size of the via hole.
  • the diode may also be formed by patterning first, and then a via hole electrically connected thereto may be formed on the diode later.
  • FIGS. 15A to 15G show manufacturing steps of the resistance variable memory according to the second embodiment of the disclosure.
  • FIG. 15A is a plan view showing the case where two transistors are formed.
  • the n-type diffusion regions AA are formed, and the word lines WL including conductive polysilicon are formed in the column direction via a gate oxide film so as to be aligned therewith.
  • an interlayer insulating film is formed on the entire substrate, and the contact holes CS for exposing the n-type diffusion regions AA are formed in the interlayer insulating film.
  • FIG. 15B is a plan view of the first-layer metal wiring M 1 .
  • the first-layer metal wiring M 1 includes the source line SL extending in the row direction and having a protruding portion protruding in the column direction, and the rectangular intermediate metal IM 1 spaced apart from the source line SL in the column direction and extending in the row direction for a certain length.
  • the protruding portion of the source line SL is electrically connected to the two n-type diffusion regions (sources) between two adjacent word lines via the contact holes CS, and the intermediate metal IM 1 is electrically connected to the n-type diffusion regions (drains) on the outer side of two adjacent word lines via the contact hole CS.
  • the variable resistance element RE 1 , the via hole V 12 , and the via hole V 11 are formed on the intermediate metal IM 1 .
  • FIG. 15C is a plan view of the second-layer metal wiring M 2 .
  • the second-layer metal wiring M 2 includes the bit line BL 1 extending in the column direction, and the intermediate metal IM 2 spaced apart from the bit line BL 1 in the row direction and extending in the row direction for a certain length.
  • the bit line BL 1 is electrically connected to the variable resistance element RE 1 via the via hole V 12 .
  • the intermediate metal IM 2 is electrically connected to the intermediate metal IM 1 via the via hole V 11 , and has the same shape as the intermediate metal IM 1 , but is slightly shifted from the intermediate metal IM 1 in the row direction.
  • the variable resistance element RE 2 , the via hole V 22 , and the via hole V 21 are formed on the intermediate metal IM 2 .
  • FIG. 15D is a plan view of the third-layer metal wiring M 3 .
  • the third-layer metal wiring M 3 includes the bit line BL 2 extending in the column direction, and the intermediate metal IM 3 spaced apart from the bit line BL 2 in the row direction and extending in the row direction for a certain length.
  • the bit line BL 2 is electrically connected to the variable resistance element RE 2 via the via hole V 22 .
  • the intermediate metal IM 3 is electrically connected to the intermediate metal IM 2 via the via hole V 21 .
  • the variable resistance element RE 3 , the via hole V 32 , and the via hole V 31 are formed on the intermediate metal IM 3 .
  • the intermediate metal IM 3 , the variable resistance element RE 3 , the via hole V 32 , and the via hole V 31 are disposed at positions substantially coinciding with the positions at which the intermediate metal IM 1 , the variable resistance element RE 1 , the via hole V 12 , and the via hole V 11 are disposed.
  • FIG. 15E is a plan view of the fourth-layer metal wiring M 4 .
  • the fourth-layer metal wiring M 4 has the same pattern as that of the second-layer metal wiring M 2 , and includes the bit line BL 3 and the intermediate metal IM 4 .
  • the bit line BL 3 is electrically connected to the variable resistance element RE 3 via the via hole V 32 . Further, the variable resistance element RE 4 and the via hole V 42 are formed on the intermediate metal IM 4 .
  • FIG. 15F is a plan view of the fifth-layer metal wiring M 5 .
  • the fifth-layer metal wiring M 5 forms the bit line BL 4 , and is electrically connected to the variable resistance element RE 4 via the via hole V 42 .
  • the resistance variable memory of the second embodiment including two transistors and eight variable resistance elements is formed by five layers of multilayer metal wirings.
  • the gate width of the transistor it is desirable to minimize the gate width of the transistor on the basis of having achieved high integration of the memory array, but on the other hand, for performing write to the variable resistance element, it is necessary to apply a certain current to the variable resistance element. Therefore, it is also possible to increase the gate width of the transistor as in the example of FIG. 15G , compared with the minimum gate width that can be manufactured using design rules. In other words, since the size of the memory cell is limited by the wiring, a more suitable value is set to the gate width for accessing the transistor.

Abstract

The disclosure provides a resistance variable memory that can realize high integration. The resistance variable memory of the disclosure includes a plurality of transistors formed on a surface of a substrate, and a plurality of variable resistance elements stacked on the surface of the substrate in a vertical direction. One electrode of each of the variable resistance elements is commonly electrically connected to one electrode of one transistor, and another electrode of each of the variable resistance elements is respectively electrically connected to a bit line, and another electrode of each of the transistors is electrically connected to a source line, and each gate of transistors in a row direction is commonly connected to a word line.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Japan application serial no. 2019-005316, filed on Jan. 16, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND Technical Field
The disclosure relates to a resistance variable memory using a variable resistance element, and more particularly to a three-dimensional structure of a memory array.
Description of Related Art
A resistance variable random access memory may randomly select a memory cell according to a column address and a row address, and read data from the selected memory cell or write data to the selected memory cell. A memory cell MC includes a variable resistance element and a transistor connected in series therewith. The gate of the transistor is electrically connected to the word line; the drain region is electrically connected to one electrode of the variable resistance element; the source region is electrically connected to the source line; and another electrode of the variable resistance element is electrically connected to the bit line. In general, writing a variable resistance element to a low resistance state is called set (SET), and writing it to a high resistance state is called reset (RESET).
A resistance variable memory includes a unipolar type and a bipolar type. In the unipolar type, the polarities of the write voltages applied to the variable resistance element at the time of set and reset are the same, and the set or reset is performed by changing the magnitude of the write voltage. On the other hand, in the bipolar type, the polarities of the write voltages applied to the variable resistance element at the time of set and reset are reversed. Further, in the case where a transition metal oxide such as hafnium oxide is used in the material of the variable resistance element, it is necessary to perform a forming operation on the transition metal oxide as an initial setting. The forming operation is to apply a voltage slightly larger than that when write is performed to the variable resistance element to a thin film so that the transition metal oxide film is converted from an insulating state to a variable resistance state (such as Japanese Patent No. 5748877).
In a bipolar resistance variable memory, it is necessary to dispose a bit line in a one-to-one relationship with a dedicated source line extending in the same direction as the bit line, with the ability to swap the symmetry of the bit line and the source line. However, such a layout may be a hindrance to high integration of a memory array.
Therefore, research has been conducted to realize high integration of a memory array in which source lines are shared by a plurality of memory cells. FIG. 1A illustrates a part of a memory array including shared bit lines, and FIG. 1B is a schematic cross-sectional diagram taken along a line X1-X1. As shown in FIG. 1A, shared bit lines S_BL1 and S_BL2 and word lines WL1 and WL2 extend in the same direction, and source lines SL1 and SL2 extend in a direction orthogonal thereto. The shared bit line S_BL1 is commonly connected to memory cells MC1 and MC3, and the shared bit line S_BL2 is commonly connected to memory cells MC2 and MC4. End portions of the shared bit line S_BL1 and the shared bit line S_BL2 are respectively connected to the bit line BL1 and the bit line BL2 (not shown), and the bit line BL1, the bit line BL2 and the source line SL extend in the same direction.
As shown in FIG. 1B, two transistors of the memory cells MC3 and MC4 are formed in a p-type well W on a silicon substrate. The gates of the two transistors are respectively connected to the word lines WL1 and WL2; the source regions share an n-type diffusion region; and the source regions are electrically connected to the source line SL2 via contacts CT11, vias V1, vias V2, and an intermediate metal IM1 and an intermediate metal IM2 of the substrate. The drain regions of the two transistors are respectively connected to corresponding variable resistance elements RE3 and RE4 via the contacts CT12 and the intermediate metal IM1 of the substrate, and the variable resistance element RE3 is connected to the shared bit line S_BL1 via the via hole contact V1. The drain region of the variable resistance element RE4 is also connected to the shared bit line S_BL2 in the same manner.
A memory array employing shared source lines can provide improved high integration, but it is still limited by the pitch of the transistors. Therefore, in order to realize further high integration, it is necessary to further reduce the transistor size, but the size reduction of the transistor is approaching a limit.
SUMMARY
The disclosure has been made to solve the above problems, and an object of the disclosure is to provide a resistance variable random access memory that can realize higher integration than conventional ones.
A resistance variable memory of the disclosure stores data in a reversible and non-volatile variable resistance element and includes: a plurality of transistors formed on a surface of a substrate; and a plurality of variable resistance elements stacked on the surface of the substrate in a vertical direction, one electrode of each of the plurality of variable resistance elements being commonly electrically connected to one electrode of one transistor, wherein another electrode of each of the plurality of variable resistance elements is electrically connected to a bit line, another electrode of each of the plurality of transistors is electrically connected to a source line, and each gate of transistors in a row direction is commonly connected to a word line.
According to the disclosure, a plurality of variable resistance elements are stacked on a surface of a substrate in a vertical direction, whereby high integration and high density of a memory array can be realized. Further, since a plurality of variable resistance elements share one transistor, compared with a memory cell formed by 1T×1R, high integration and high density of the memory array can be realized. In addition, by simultaneously integrating a diode and a variable resistance element, interference at the time of read or write and the sneak current issue can be more effectively suppressed.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a circuit diagram of a part of a memory array including shared bit lines of a conventional resistance variable memory, and FIG. 1B is a schematic cross-sectional diagram taken along the line X1-X1 in FIG. 1A.
FIG. 2 is a block diagram showing a schematic configuration of a resistance variable random access memory according to an embodiment of the disclosure.
FIG. 3A is a circuit diagram of a part of a vertically stacked memory array according to the first embodiment of the disclosure, and FIG. 3B is a schematic cross-sectional diagram taken along the line X2-X2 in FIG. 3A.
FIG. 4 is a circuit diagram of a part of a vertically stacked memory array according to the second embodiment of the disclosure.
FIG. 5 is a diagram showing a bias voltage at the time of a read operation from the bit line side of the resistance variable memory according to the first embodiment of the disclosure.
FIG. 6 is a diagram showing a bias voltage at the time of a read operation from the source line side of the resistance variable memory according to the first embodiment of the disclosure.
FIG. 7 is a diagram showing a bias voltage at the time of a SET write operation of the resistance variable memory according to the first embodiment of the disclosure.
FIG. 8 is a diagram showing a bias voltage at the time of a RESET write operation of the resistance variable memory according to the first embodiment of the disclosure.
FIG. 9A shows an example of a diode integrated to a variable resistance element of a resistance variable memory according to a preferred embodiment of the disclosure, and FIG. 9B is a graph showing a current-voltage (I-V) characteristic of the diode.
FIG. 10 is a diagram showing a bias voltage at the time of a read operation from the bit line side of the resistance variable memory according to the second embodiment of the disclosure.
FIG. 11 is a diagram showing a bias voltage at the time of a read operation from the source line side of the resistance variable memory according to the second embodiment of the disclosure.
FIG. 12 is a diagram showing a bias voltage at the time of a SET write operation of the resistance variable memory according to the second embodiment of the disclosure.
FIG. 13 is a diagram showing a bias voltage at the time of a RESET write operation of the resistance variable memory according to the second embodiment of the disclosure.
FIGS. 14A to 14J are diagrams for illustrating manufacturing steps of the resistance variable memory according to the first embodiment of the disclosure.
FIGS. 15A to 15G are diagrams for illustrating manufacturing steps of the resistance variable memory according to the second embodiment of the disclosure.
 DESCRIPTION OF THE EMBODIMENTS
Next, embodiments of the disclosure will be described in detail with reference to the drawings. In a preferred embodiment of the disclosure, a resistance variable memory has a memory array with a three-dimensional structure in which variable resistance elements are stacked in a vertical direction.
FIG. 2 is a block diagram showing a schematic configuration of a resistance variable random access memory according to an embodiment of the disclosure. A resistance variable memory 100 of the embodiment includes: a memory array 110 in which a plurality of memory cells including variable resistance elements and transistors are arranged in a matrix; a column decoder and driver circuit 120 which selects and drives word lines WL based on a column address X-Add; a row decoder and driver circuit 130 which generates a selection signal SSL/SBL for selecting global bit lines GBL and global source lines GSL based on a row address Y-Add; a row selection circuit 140 which respectively selects a connection between the global bit lines GBL and the bit lines BL and a connection between the global source lines GSL and the source lines SL based on the selection signal SSL/SBL; a control circuit 150 which controls each part based on a command CMD and data DQ received from the outside; sense amplifiers 160 which read read data of the memory cells via the GBL/BL; and write driver and read bias circuits 170 which apply a bias voltage at the time of a read operation or a voltage corresponding to set and reset at the time of a write operation via the GBL/BL.
The memory array 110 includes an m number of sub-arrays 110-1 to 110-m which are respectively and correspondingly connected to an m number of row selectors YMUX of the row selection circuit 140. The m number of row selectors YMUX are connected to the sense amplifiers 160 and the write driver and read bias circuits 170, respectively. Each of the sense amplifiers 160 is connected to the control circuit 150 via an internal data bus DO, and results read by the sense amplifiers 160 are output to the control circuit 150 via the internal data bus DO. Further, each of the write driver and read bias circuits 170 is connected to the control circuit 150 via an internal data bus DI, and each of the write driver and read bias circuits 170 receives the write data via the internal data bus DI.
Next, a three-dimensional array structure of the resistance variable memory according to the first embodiment of the disclosure will be described. FIG. 3A is a circuit diagram of a part of a memory array with a three-dimensional structure of the embodiment, and FIG. 3B is a schematic cross-sectional diagram taken along the line X2-X2 in FIG. 3A.
As shown in FIG. 3A, word lines WL1 to WL2 and bit lines BL1 to BL8 extend in parallel with one another, and source lines SL1 to SL2 extend in a direction orthogonal thereto. The word line WL1 is connected to gates of transistors Q1 and Q3, and the word line WL2 is connected to gates of transistors Q2 and Q4. In the embodiment, four variable resistance elements are commonly connected to one transistor. One electrode of each of the variable resistance elements RE1 to RE4 connected to the transistor Q1 is commonly connected to one electrode of the transistor Q1, and another electrode of each of the variable resistance elements RE1 to RE4 is connected to the bit lines BL1 to BL4, respectively. The four variable resistance elements connected to the transistor Q3 are also configured in the same manner.
Similar to the dispositions of the transistor Q1 and the variable resistance elements RE1 to RE4 connected to the transistor Q1, one electrode of each of the four variable resistance elements connected to the transistor Q2 is commonly connected to one electrode of the transistor Q2, and another electrode of each of the four variable resistance elements connected to the transistor Q2 is connected to the bit lines BL5 to BL8, respectively. The four variable resistance elements connected to the transistor Q4 are also configured in the same manner. Moreover, another electrode of the transistor Q1 and another electrode of the transistor Q2 are commonly connected, and the connection node thereof is connected to the source line SL1; another electrode of the transistor Q3 and another electrode of the transistor Q4 are commonly connected, and the connection node thereof is connected to the source line SL2.
The memory array structure of the disclosure is configured, for example, by using a multilayer wiring structure on a silicon substrate. As shown in FIG. 3B, n-type diffusion regions for serving as source/drain electrodes of the transistors are formed in a P-type well W on the silicon substrate. The word lines WL1 to WL2 connected to the gates of the transistors are formed, for example, by a polysilicon layer. The four variable resistance elements commonly connected to one transistor are stacked on the silicon substrate in the vertical direction by using five layers of metal wiring.
An interlayer insulating film is formed on the polysilicon layer forming the word lines WL1 to WL2, and a first-layer metal wiring is formed thereon. The first-layer metal wiring forms the source line SL2 and an intermediate metal IM1, and a shared n-type diffusion region of the transistors Q3 and Q4 is electrically connected to the source line SL2 via a contact CT11 for the substrate formed on the interlayer insulating film. Further, another n-type diffusion region of each of the transistors Q3 and Q4 is electrically connected to the corresponding intermediate metal IM1 via a contact CT12 for the substrate formed on the interlayer insulating film.
An interlayer insulating film is formed on the first-layer metal wiring, and a second-layer metal wiring is formed on the interlayer insulating film. The second-layer metal wiring forms the bit line BL1 and an intermediate metal IM2. It should be noted here that the intermediate metal IM2 has the same shape as the intermediate metal IM1 and is formed at a position above the intermediate metal IM1 and partially shifting away therefrom, and the bit line BL1 is formed on the intermediate metal IM1. A contact V11 is formed in the interlayer insulating film between the intermediate metal IM1 and the intermediate metal IM2. The variable resistance element RE1 and a contact V12 are formed in the interlayer insulating film between the intermediate metal IM1 and the bit line BL1. The variable resistance element includes, for example, a transition metal oxide (TMO), such as hafnium oxide.
An interlayer insulating film is formed on the second-layer metal wiring, and a third-layer metal wiring is formed on the interlayer insulating film. The third-layer metal wiring forms the bit line BL2 and an intermediate metal IM3, and the intermediate metal IM3 has the same shape as the intermediate metal IM1 and is formed at a corresponding position above the intermediate metal IM1, and the bit line BL2 is formed on the intermediate metal IM2. A contact V21 is formed in the interlayer insulating film between the intermediate metal IM1 and the intermediate metal IM2. The variable resistance element RE2 and a contact V22 are formed in the interlayer insulating film between the intermediate metal IM2 and the bit line BL2.
Thereafter, similarly, a fourth-layer metal wiring forms the bit line BL3 and an intermediate metal IM4, and a fifth-layer metal wiring forms the bit line BL4. Thus, for one transistor, the four variable resistance elements RE1 to RE4 stacked in the vertical direction from the surface of the semiconductor substrate are formed. For example, when read of the variable resistance element RE3 is performed, the transistor Q3 is turned on via the word line WL1, and a read voltage is applied to the bit line BL3, and GND is applied to the source line SL2. When the variable resistance element RE3 is in a high resistance state, a small current flows from the bit line BL3 to the source line SL2, and if the variable resistance element RE3 is in a low resistance state, a large current flows from the bit line BL3 to the source line SL2. The detailed operations of read or write will be described later.
According to the embodiment, a plurality of variable resistance elements can be stacked on the surface of the semiconductor substrate in the vertical direction, and the plurality of stacked variable resistance elements share one transistor, so high integration and high density of the memory array can be realized.
Further, in the above embodiment, an example in which four variable resistance elements are commonly connected to one transistor is shown, but the disclosure is not limited thereto; for example, two or three variable resistance elements may be commonly connected to one transistor, or five or more variable resistance elements may be commonly connected. At this time, the number of stacked metal wirings also changes depending on the number of stacked variable resistance elements.
Next, a configuration of a memory array according to a second embodiment of the disclosure will be described. FIG. 4 shows the configuration of the memory array of the second embodiment, and here, eight transistors and 32 variable resistance elements connected thereto are shown. This embodiment is different from the first embodiment in that the bit lines are parallel to the source lines, and the word lines extend in a direction orthogonal thereto. In such a configuration, since the bit lines are parallel to the source lines, the layout is easier than in the first embodiment. In the second embodiment, four variable resistance elements are also connected to one transistor, and the four variable resistance elements are stacked in the vertical direction from the surface of the semiconductor substrate by five layers of metal wirings.
Next, the operation of the memory array configuration of the first embodiment will be described. FIG. 5 shows a bias voltage when read is performed from the bit line side in the memory array of the first embodiment. A read voltage VWLREAD is applied to the selected word line WL1 so that the transistor connected to the selected word line WL1 is turned on. 0 V is applied to the unselected word line WL2 so that the transistor connected to the unselected word line WL2 is turned off. A read voltage VBLREAD is applied to the bit line BL1 of the selected variable resistance element connected to the selected transistor, and an inhibit voltage INHIBIT is applied to the bit lines BL2 to BL4 of other unselected variable resistance elements commonly connected to the selected transistor. In the case of performing integration on a diode, the inhibit voltage INHIBIT is applied via the diode to suppress a sneak current. 0 V is applied to the selected source line SL3. The bit lines BL5 to BL8 of the unselected variable resistance elements connected to the unselected transistor are applied with 0 V or are set to a floating state F, and the unselected source lines SL1 to SL2 and SL4 are set to the floating state F or are applied with the read voltage VBLREAD.
Here, the inhibit voltage INHIBIT applied to the bit lines BL2 to BL4 of the remaining three unselected variable resistance elements connected to the selected transistor is an intermediate voltage lower than the read voltage VBLREAD and higher than 0 V applied to the source lines. Thereby, the bias voltage required for reading is not applied to the unselected three variable resistance elements from the unselected bit lines BL2 to BL4. Further, when the selected variable resistance element is in a low resistance state, a large bias voltage is applied from the selected variable resistance element to the unselected variable resistance elements, or when the unselected variable resistance elements are in a low resistance state, it is ensured that the current does not flow into them.
In this manner, the read voltage VBLREAD is applied to the selected variable resistance element from the bit line side, and the sense amplifier 160 reads out a voltage or current corresponding to the high resistance state or the low resistance state of the selected variable resistance element.
FIG. 6 shows a bias voltage when read is performed from the source line side in the memory array of the first embodiment. The read voltage VWLREAD is applied to the selected word line WL1, and 0 V is applied to the unselected word line WL2. 0 V is applied to the bit line BL1 of the selected variable resistance element connected to the selected transistor, and an inhibit voltage INHIBIT is applied to the bit lines BL2 to BL4 of other unselected variable resistance elements commonly connected to the selected transistor. In the case of performing integration on the diode, the inhibit voltage INHIBIT is applied via the diode to suppress a sneak current. A read voltage VSLREAD is applied to the selected source line SL3. The bit lines BL5 to BL8 of the unselected variable resistance elements connected to the unselected transistor are applied with 0 V or are set to the floating state F, and the unselected source lines SL1 to SL2 and SL4 are applied with 0 V.
In this manner, the sense amplifier 160 reads out a voltage or current corresponding to the high resistance state or the low resistance state of the selected variable resistance element.
Next, the bias voltage at the time of performing SET write in the memory array of the first embodiment is shown in FIG. 7. A write voltage VWLSET is applied to the selected word line WL1 so that the transistor connected to the selected word line WL1 is turned on. 0 V is applied to the unselected word line WL2 so that the transistor connected to the unselected word line WL2 is turned off. A write voltage VBLSET is applied to the bit line BL1 of the selected variable resistance element connected to the selected transistor, and the bit lines BL2 to BL4 of other unselected variable resistance elements commonly connected to the selected transistor are set to the floating state F or are applied with the inhibit voltage INHIBIT. 0 V is applied to the selected source line SL3. The bit lines BL5 to BL8 of the unselected variable resistance elements connected to the unselected transistor are set to the floating state F or are applied with 0 V, and the unselected source lines SL1 to SL2 and SL4 are applied with the write voltage VBLSET or are set to the floating state F.
In the embodiment, the bit lines BL2 to BL4 of the unselected variable resistance elements commonly connected to the selected transistor are set to the floating state F or are applied with the inhibit voltage INHIBIT, whereby the unselected variable resistance elements are not applied with a SET write bias voltage, and only the selected variable resistance element is applied with the SET write bias voltage, and the selected variable resistance element becomes the low resistance state. At the same time, since the inhibit voltage INHIBIT is an intermediate voltage lower than the write voltage VBLSET and higher than 0 V, it is possible to suppress the unselected variable resistance elements from being affected by the application of the SET write bias voltage.
Next, the bias voltage at the time of performing RESET write in the memory array of the first embodiment is shown in FIG. 8. A write voltage VWLRESET is applied to the selected word line WL1 so that the transistor connected to the selected word line WL1 is turned on. 0 V is applied to the unselected word line WL2 so that the transistor connected to the unselected word line WL2 is turned off. 0 V is applied to the bit line BL1 of the selected variable resistance element connected to the selected transistor, and the bit lines BL2 to BL4 of other unselected variable resistance elements commonly connected to the selected transistor are set to the floating state F or are applied with the inhibit voltage INHIBIT. A write voltage VSLRESET is applied to the selected source line SL3. The bit lines BL5 to BL8 of the unselected variable resistance elements connected to the unselected transistor are set to the floating state F or are applied with 0 V, and the unselected source lines SL1 to SL2 and SL4 are applied with 0 V.
In the embodiment, the bit lines BL2 to BL4 of the unselected variable resistance elements commonly connected to the selected transistor are set to the floating state F or are applied with the inhibit voltage INHIBIT, whereby the unselected variable resistance elements are not applied with a RESET write bias voltage, and only the selected variable resistance element is applied with the RESET write bias voltage, and the selected variable resistance element becomes the high resistance state. At the same time, since the inhibit voltage INHIBIT is an intermediate voltage lower than the write voltage VSLRESET and higher than 0 V, it is possible to suppress the unselected variable resistance elements from being affected by the application of the RESET write bias voltage.
In the first embodiment, in order to prevent interference with other unselected variable resistance elements commonly connected to the selected transistor, the inhibit voltage INHIBIT is applied to the unselected bit lines, but with the high integration development of the memory array, the bias voltage control may not be sufficient to prevent interference. Therefore, in another embodiment, a diode SEL can be integrated with all of the variable resistance elements to prevent an undesired current from flowing to the unselected variable resistance elements.
As shown in FIG. 9A, the diode SEL is, for example, simultaneously formed when a variable resistance element RE is formed in a via hole formed in a lower electrode of the interlayer insulating film. In detail, a first electrode of the variable resistance element RE, a transition metal oxide of the variable resistance element RE, a second electrode of the variable resistance element RE, the diode SEL, and a metal plug may be sequentially formed in the via hole, wherein the diode SEL includes, for example, a stack of a p-type semiconductor layer and an n-type semiconductor layer. In this manner, the bit line and the intermediate metal are electrically connected via the variable resistance element RE, the diode SEL, and the metal plug in the via hole. In an embodiment, the diode SEL may also be formed on both sides of the second electrode of the variable resistance element or formed on both sides of the first electrode and the second electrode.
FIG. 9B is a graph showing an I-V characteristic of the diode SEL. As shown in the figure, the diode SEL has a characteristic of flowing a forward current when a forward bias voltage is greater than a threshold, and flowing a reverse current when a reverse bias voltage is greater than a threshold. Therefore, by applying an inhibit voltage, which is lower than the threshold voltage that causes the diode SEL to flow the forward/reverse current, to the bit lines of the unselected variable resistance elements, interference or the sneak current at the time of read or write can be more effectively suppressed.
Next, the operation of the resistance variable memory according to the second embodiment of the disclosure will be described. FIG. 10 shows the bias voltage at the time of the read operation from the bit line side; FIG. 11 shows the bias voltage at the time of the read operation from the source line side; FIG. 12 shows the bias voltage at the time of the SET write operation; and FIG. 13 shows the bias voltage at the time of the RESET write operation. Further, in the second embodiment, the diode and the variable resistance element may be simultaneously integrated to more effectively suppress interference with the unselected variable resistance elements at the time of read and write.
Next, manufacturing steps of the resistance variable memory according to the first embodiment of the disclosure will be described with reference to FIGS. 14A to 14J. FIG. 14A is a plan view showing the case where eight transistors are formed on the substrate. In the P-type well of the semiconductor substrate, n-type diffusion regions AA are formed, and the word lines WL including conductive polysilicon are formed in the row direction via a gate oxide film so as to be aligned therewith. An interlayer insulating film is formed on the entire substrate, and the contact holes CS for exposing the n-type diffusion regions AA are formed in the interlayer insulating film.
Next, as shown in FIG. 14B, a first-layer metal wiring M1 (indicated by a solid line in the figure) is formed on the interlayer insulating film. The first-layer metal wiring M1 includes: the source line SL that extends in the column direction and is electrically connected to the n-type diffusion regions (sources) between the two word lines via the contact holes CS, and the rectangular intermediate metal IM1 that is spaced apart from the source line SL in the row direction, extends in the row direction for a certain length and is electrically connected to the n-type diffusion regions (drains) on the outer side of the two word lines via the contact holes CS. The source line SL and the intermediate metal IM1 may be directly electrically connected to the n-type diffusion regions, or may be electrically connected to the n-type diffusion regions via a barrier metal or the like in the contact holes.
Next, as shown in FIG. 14C, an interlayer insulating film is formed on the entire substrate, and two via holes for exposing the intermediate metal IM1 are formed in the interlayer insulating film. A metal plug for electrically connecting to a second-layer metal wiring M2 is buried in one of the via holes to form a via hole V11. In one embodiment, the variable resistance element RE1 and a via hole V12 are buried in the other via hole. In the embodiment in which the diode and the variable resistance element RE1 are integrated at the same time, the variable resistance element RE1, the diode, and the via hole V12 are sequentially buried in the other via hole, wherein the diode may be formed, for example, by stacking a p-type polysilicon layer and an n-type polysilicon layer on the variable resistance element RE1.
Next, as shown in FIG. 14D, the second-layer metal wiring M2 (indicated by a solid line in the figure) is formed. The second-layer metal wiring M2 includes the bit line BL1 extending in the column direction on the intermediate metal IM1, and the intermediate metal IM2 spaced apart from the bit line BL1 in the row direction and extending in the row direction for a certain length. The bit line BL1 is electrically connected to the variable resistance element RE1 via the via hole V12. The intermediate metal IM2 is electrically connected to the intermediate metal IM1 via the via hole V11, and has the same shape as the intermediate metal IM1, but is slightly shifted from the intermediate metal IM1 in the row direction.
Next, as shown in FIG. 14E, an interlayer insulating film is formed on the entire substrate, and two via holes for exposing the intermediate metal IM2 are formed in the interlayer insulating film. A metal plug for electrically connecting to a third-layer metal wiring M3 is buried in one of the via holes to form a via hole V21. In one embodiment, the variable resistance element RE2 and a via hole V22 are buried in the other via hole. In the embodiment in which the diode and the variable resistance element RE2 are integrated at the same time, the variable resistance element RE2, the diode, and the via hole V22 are sequentially buried in the other via hole. In particular, the variable resistance element RE2 is, for example, disposed at a position (a position which is line-symmetric in the column direction) where the variable resistance element RE1 is reversed by 180 degrees in the row direction with the via hole V21 as the center.
Next, as shown in FIG. 14F, the third-layer metal wiring M3 (indicated by a solid line in the figure) having the same wiring pattern as that of the first-layer metal wiring M1 is formed, and the metal wiring M3 forms the intermediate metal IM3 and the bit line BL2. The bit line BL2 is electrically connected to the variable resistance element RE2 via the via hole V22, and the intermediate metal IM3 is electrically connected to the intermediate metal IM2 via the via hole V21. Further, as shown in FIG. 14G, the variable resistance element RE3 and a via hole V32 are formed on the intermediate metal IM3, and a via hole V31 is formed.
Next, as shown in FIG. 14H, a fourth-layer metal wiring M4 (indicated by a solid line in the figure) having the same wiring pattern as that of the second-layer metal wiring M2 is formed, and the metal wiring M4 forms the intermediate metal IM4 and the bit line BL3. The bit line BL3 is electrically connected to the variable resistance element RE3 via the via hole V32, and the intermediate metal IM4 is electrically connected to the intermediate metal IM3 via the via hole V31. Further, as shown in FIG. 14I, the variable resistance element RE4 and a via hole V42 are formed on the intermediate metal IM4.
Next, as shown in FIG. 14J, a fifth-layer metal wiring M5 (indicated by a solid line in the figure) is formed. The metal wiring M5 forms the bit line BL4. The bit line BL4 is electrically connected to the variable resistance element RE4 via the via hole V42. As described above, the resistance variable memory of the first embodiment including eight transistors and 32 variable resistance elements is formed by five layers of multilayer metal wirings.
In the above embodiment, an example in which the variable resistance elements are formed in the via holes on the intermediate metals is shown, but the disclosure is not limited thereto. In other embodiments, the variable resistance elements may be formed on the intermediate metals by patterning first, and then the via holes electrically connected thereto may be formed on the variable resistance elements later. At this time, the size of the variable resistance element is not limited by the size of the via hole. Similarly, for the diode, the diode may also be formed by patterning first, and then a via hole electrically connected thereto may be formed on the diode later.
FIGS. 15A to 15G show manufacturing steps of the resistance variable memory according to the second embodiment of the disclosure. FIG. 15A is a plan view showing the case where two transistors are formed. In the P-type well W of the semiconductor substrate, the n-type diffusion regions AA are formed, and the word lines WL including conductive polysilicon are formed in the column direction via a gate oxide film so as to be aligned therewith. Then, an interlayer insulating film is formed on the entire substrate, and the contact holes CS for exposing the n-type diffusion regions AA are formed in the interlayer insulating film.
FIG. 15B is a plan view of the first-layer metal wiring M1. The first-layer metal wiring M1 includes the source line SL extending in the row direction and having a protruding portion protruding in the column direction, and the rectangular intermediate metal IM1 spaced apart from the source line SL in the column direction and extending in the row direction for a certain length. The protruding portion of the source line SL is electrically connected to the two n-type diffusion regions (sources) between two adjacent word lines via the contact holes CS, and the intermediate metal IM1 is electrically connected to the n-type diffusion regions (drains) on the outer side of two adjacent word lines via the contact hole CS. Further, the variable resistance element RE1, the via hole V12, and the via hole V11 are formed on the intermediate metal IM1.
FIG. 15C is a plan view of the second-layer metal wiring M2. The second-layer metal wiring M2 includes the bit line BL1 extending in the column direction, and the intermediate metal IM2 spaced apart from the bit line BL1 in the row direction and extending in the row direction for a certain length. The bit line BL1 is electrically connected to the variable resistance element RE1 via the via hole V12. The intermediate metal IM2 is electrically connected to the intermediate metal IM1 via the via hole V11, and has the same shape as the intermediate metal IM1, but is slightly shifted from the intermediate metal IM1 in the row direction. Further, the variable resistance element RE2, the via hole V22, and the via hole V21 are formed on the intermediate metal IM2.
FIG. 15D is a plan view of the third-layer metal wiring M3. The third-layer metal wiring M3 includes the bit line BL2 extending in the column direction, and the intermediate metal IM3 spaced apart from the bit line BL2 in the row direction and extending in the row direction for a certain length. The bit line BL2 is electrically connected to the variable resistance element RE2 via the via hole V22. The intermediate metal IM3 is electrically connected to the intermediate metal IM2 via the via hole V21. Further, the variable resistance element RE3, the via hole V32, and the via hole V31 are formed on the intermediate metal IM3. The intermediate metal IM3, the variable resistance element RE3, the via hole V32, and the via hole V31 are disposed at positions substantially coinciding with the positions at which the intermediate metal IM1, the variable resistance element RE1, the via hole V12, and the via hole V11 are disposed.
FIG. 15E is a plan view of the fourth-layer metal wiring M4. The fourth-layer metal wiring M4 has the same pattern as that of the second-layer metal wiring M2, and includes the bit line BL3 and the intermediate metal IM4. The bit line BL3 is electrically connected to the variable resistance element RE3 via the via hole V32. Further, the variable resistance element RE4 and the via hole V42 are formed on the intermediate metal IM4.
FIG. 15F is a plan view of the fifth-layer metal wiring M5. The fifth-layer metal wiring M5 forms the bit line BL4, and is electrically connected to the variable resistance element RE4 via the via hole V42. As described above, the resistance variable memory of the second embodiment including two transistors and eight variable resistance elements is formed by five layers of multilayer metal wirings.
In some embodiments, it is desirable to minimize the gate width of the transistor on the basis of having achieved high integration of the memory array, but on the other hand, for performing write to the variable resistance element, it is necessary to apply a certain current to the variable resistance element. Therefore, it is also possible to increase the gate width of the transistor as in the example of FIG. 15G, compared with the minimum gate width that can be manufactured using design rules. In other words, since the size of the memory cell is limited by the wiring, a more suitable value is set to the gate width for accessing the transistor.
The preferred embodiments of the disclosure have been described in detail above, but the disclosure is not limited thereto, and various modifications and changes may be made by persons skilled in the art without departing from the scope of the disclosure defined by the attached claims.

Claims (20)

What is claimed is:
1. A resistance variable memory for storing data in a reversible and non-volatile variable resistance element, the resistance variable memory comprising:
a plurality of transistors formed on a surface of a substrate; and
a plurality of variable resistance elements stacked on the surface of the substrate in a vertical direction, one electrode of each of the plurality of variable resistance elements being commonly electrically connected to one electrode of one transistor,
wherein another electrode of each of the plurality of variable resistance elements is electrically connected to a bit line, another electrode of each of the plurality of transistors is electrically connected to a source line, and each gate of transistors in a row direction is commonly connected to a word line,
wherein the plurality of variable resistance elements corresponding to the same transistor are deposited in different interlayer insulating film layers, wherein a first variable resistance element among the plurality of variable resistance elements is formed between a first bit line and a first intermediate metal, wherein a second variable resistance element among the plurality of variable resistance elements is formed between a second bit line and a second intermediate metal, wherein the second intermediate metal and the first bit line are formed as one metal wiring layer.
2. The resistance variable memory according to claim 1, wherein each of the plurality of variable resistance elements is connected to a corresponding diode.
3. The resistance variable memory according to claim 2, wherein the diode flows a forward current when a forward bias voltage is applied, and flows a reverse current when a reverse bias voltage is applied.
4. The resistance variable memory according to claim 1, wherein the plurality of variable resistance elements are respectively formed on wirings of respective layers of a multilayer wiring structure.
5. The resistance variable memory according to claim 1, wherein the plurality of variable resistance elements are formed at positions different from one another in respective layers.
6. The resistance variable memory according to claim 2, wherein the variable resistance element and the diode are stacked in a via hole contact.
7. The resistance variable memory according to claim 1, wherein the variable resistance element comprises a transition metal oxide.
8. The resistance variable memory according to claim 1, wherein the bit lines and the source lines are parallel on a memory array.
9. The resistance variable memory according to claim 1, wherein the bit lines and the source lines are orthogonal on a memory array.
10. The resistance variable memory according to claim 1, wherein during a read operation, a selected variable resistance element of the plurality of variable resistance elements is selected, a selected transistor connected to the selected variable resistance of the plurality of transistors is selected, wherein a bit line connected to the selected variable resistance element is applied a first read voltage, wherein a bit line connected to an unselected variable resistance element connected to the selected transistor is applied an inhibit voltage.
11. The resistance variable memory according to claim 10, wherein during the read operation, the inhibit voltage is an intermediate voltage lower than the first read voltage and higher than 0 V.
12. The resistance variable memory according to claim 10, wherein during the read operation, the selected transistor is turned on by a second read voltage, wherein a source line connected to a source of the selected transistor is applied a voltage of 0 V.
13. The resistance variable memory according to claim 10, wherein during the read operation, a plurality of bit lines connected to the plurality of variable resistance elements connected to the unselected transistor are floated or are applied a voltage of 0 V.
14. The resistance variable memory according to claim 1, wherein during a read operation, a selected variable resistance element of the plurality of variable resistance elements is selected, a selected transistor connected to the selected variable resistance of the plurality of transistors is selected, wherein a bit line connected to the selected variable resistance element is applied a voltage of 0 V, wherein a bit line connected to an unselected variable resistance element connected to the selected transistor is applied an inhibit voltage.
15. The resistance variable memory according to claim 14, wherein during the read operation, the selected transistor is turned on by a first read voltage, wherein a source line connected to a source of the selected transistor is applied a second read voltage.
16. The resistance variable memory according to claim 1, wherein during a set write operation, a selected variable resistance element of the plurality of variable resistance elements is selected, a selected transistor connected to the selected variable resistance of the plurality of transistors is selected, wherein a bit line connected to the selected variable resistance element is applied a first write voltage, wherein a bit line connected to an unselected variable resistance element connected to the selected transistor is floated or are applied an inhibit voltage.
17. The resistance variable memory according to claim 16, wherein during the set write operation, the selected transistor is turned on by a second write voltage, wherein a source line connected to a source of the selected transistor is applied a voltage of 0 V.
18. The resistance variable memory according to claim 16, wherein during the set write operation, a plurality of bit lines connected to the plurality of variable resistance elements connected to the unselected transistor are floated or are applied a voltage of 0 V.
19. The resistance variable memory according to claim 1, wherein during a reset write operation, a selected variable resistance element of the plurality of variable resistance elements is selected, a selected transistor connected to the selected variable resistance of the plurality of transistors is selected, and wherein a bit line connected to the selected variable resistance element is applied a voltage of 0 V, wherein a bit line connected to an unselected variable resistance element connected to the selected transistor is floated or are applied an inhibit voltage.
20. The resistance variable memory according to claim 19, wherein during the reset write operation, the selected transistor is turned on by a first write voltage, wherein a source line connected to a source of the selected transistor is applied a second write voltage, wherein the inhibit voltage is an intermediate voltage lower than the second write voltage and higher than 0 V.
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021039815A (en) * 2019-09-05 2021-03-11 キオクシア株式会社 Semiconductor storage device
US11417375B2 (en) * 2019-12-17 2022-08-16 Micron Technology, Inc. Discharge current mitigation in a memory array
US11711926B2 (en) * 2020-09-18 2023-07-25 Macronix International Co., Ltd. Memory array and memory structure
US20220399059A1 (en) * 2021-06-10 2022-12-15 National Central University Memory circuit, memory device and operation method thereof
US11776595B2 (en) * 2022-01-25 2023-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device with source line control

Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748877B2 (en) 1979-08-03 1982-10-19
JP2003249073A (en) 2001-12-21 2003-09-05 Toshiba Corp Magnetic random access memory
KR20050074328A (en) 2004-01-13 2005-07-18 샤프 가부시키가이샤 Method for manufacturing nonvolatile semiconductor memory device
JP2005203463A (en) 2004-01-14 2005-07-28 Sharp Corp Nonvolatile semiconductor memory
KR100564637B1 (en) 2004-10-26 2006-03-29 삼성전자주식회사 Semiconductor memory device and programming method thereof
WO2007023569A1 (en) 2005-08-26 2007-03-01 Fujitsu Limited Nonvolatile semiconductor storage device and its write method
JP2008269741A (en) 2007-04-24 2008-11-06 Spansion Llc Nonvolatile memory device and its control method
JP2009224778A (en) 2008-03-13 2009-10-01 Samsung Electronics Co Ltd Nonvolatile memory device using resistance material and inner electrode, method of manufacturing the same, and processing system including the same
JP2010108595A (en) 2003-12-26 2010-05-13 Panasonic Corp Memory element
US7859885B2 (en) 2003-03-18 2010-12-28 Kabushiki Kaisha Toshiba Phase changing memory device
WO2011152061A1 (en) 2010-06-03 2011-12-08 パナソニック株式会社 Cross-point variable-resistance nonvolatile storage device
US20120087169A1 (en) 2010-10-07 2012-04-12 Crossbar, Inc. Circuit for concurrent read operation and method therefor
TWI415132B (en) 2008-09-12 2013-11-11 Macronix Int Co Ltd Novel sensing circuit for pcram applications
US20150070965A1 (en) 2013-09-12 2015-03-12 Sandisk 3D Llc FET LOW CURRENT 3D ReRAM NON-VOLATILE STORAGE
US20150070966A1 (en) 2013-09-12 2015-03-12 Sandisk 3D Llc Method of operating fet low current 3d re-ram
US9042153B2 (en) * 2010-08-20 2015-05-26 Shine C. Chung Programmable resistive memory unit with multiple cells to improve yield and reliability
JP5748877B1 (en) 2014-03-07 2015-07-15 ウィンボンド エレクトロニクス コーポレーション Resistance change memory
US20150357032A1 (en) * 2013-07-26 2015-12-10 Kabushiki Kaisha Toshiba Multi-context configuration memory
US20160180929A1 (en) * 2014-12-18 2016-06-23 YounSeon KANG Variable Resistance Memory Device
JP2016134193A (en) 2015-01-21 2016-07-25 力旺電子股▲分▼有限公司 Memory cell array of resistance change type random access memory
US9514810B1 (en) 2016-02-08 2016-12-06 Freescale Semiconductor, Inc. Resistive non-volatile memory cell and method for programming same
CN106205681A (en) 2015-04-29 2016-12-07 复旦大学 The framework disturbed for three-dimensional vertical stacking resistance-variable storing device suppression IR drop voltage drop and read-write and operative algorithm
US20160380030A1 (en) * 2015-06-23 2016-12-29 Stmicroelectronics (Crolles 2) Sas Resistive memory cell having a compact structure
TWI597833B (en) 2013-03-15 2017-09-01 愛思開海力士有限公司 Variable resistance memory device
US9972386B2 (en) 2011-12-23 2018-05-15 Imec Stacked RRAM array with integrated transistor selector
CN108735262A (en) 2017-04-19 2018-11-02 华邦电子股份有限公司 Variable resistance type random access memory

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9087572B2 (en) * 2012-11-29 2015-07-21 Rambus Inc. Content addressable memory

Patent Citations (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748877B2 (en) 1979-08-03 1982-10-19
JP2003249073A (en) 2001-12-21 2003-09-05 Toshiba Corp Magnetic random access memory
US7859885B2 (en) 2003-03-18 2010-12-28 Kabushiki Kaisha Toshiba Phase changing memory device
JP2010108595A (en) 2003-12-26 2010-05-13 Panasonic Corp Memory element
KR20050074328A (en) 2004-01-13 2005-07-18 샤프 가부시키가이샤 Method for manufacturing nonvolatile semiconductor memory device
JP2005203463A (en) 2004-01-14 2005-07-28 Sharp Corp Nonvolatile semiconductor memory
KR100564637B1 (en) 2004-10-26 2006-03-29 삼성전자주식회사 Semiconductor memory device and programming method thereof
JP2006127747A (en) 2004-10-26 2006-05-18 Samsung Electronics Co Ltd Semiconductor memory device and its programming method
WO2007023569A1 (en) 2005-08-26 2007-03-01 Fujitsu Limited Nonvolatile semiconductor storage device and its write method
JP2008269741A (en) 2007-04-24 2008-11-06 Spansion Llc Nonvolatile memory device and its control method
JP2009224778A (en) 2008-03-13 2009-10-01 Samsung Electronics Co Ltd Nonvolatile memory device using resistance material and inner electrode, method of manufacturing the same, and processing system including the same
TWI415132B (en) 2008-09-12 2013-11-11 Macronix Int Co Ltd Novel sensing circuit for pcram applications
WO2011152061A1 (en) 2010-06-03 2011-12-08 パナソニック株式会社 Cross-point variable-resistance nonvolatile storage device
JP4860787B1 (en) 2010-06-03 2012-01-25 パナソニック株式会社 Cross-point variable resistance nonvolatile memory device
US9042153B2 (en) * 2010-08-20 2015-05-26 Shine C. Chung Programmable resistive memory unit with multiple cells to improve yield and reliability
US20120087169A1 (en) 2010-10-07 2012-04-12 Crossbar, Inc. Circuit for concurrent read operation and method therefor
US9972386B2 (en) 2011-12-23 2018-05-15 Imec Stacked RRAM array with integrated transistor selector
TWI597833B (en) 2013-03-15 2017-09-01 愛思開海力士有限公司 Variable resistance memory device
US20150357032A1 (en) * 2013-07-26 2015-12-10 Kabushiki Kaisha Toshiba Multi-context configuration memory
US20150070965A1 (en) 2013-09-12 2015-03-12 Sandisk 3D Llc FET LOW CURRENT 3D ReRAM NON-VOLATILE STORAGE
US20150070966A1 (en) 2013-09-12 2015-03-12 Sandisk 3D Llc Method of operating fet low current 3d re-ram
JP5748877B1 (en) 2014-03-07 2015-07-15 ウィンボンド エレクトロニクス コーポレーション Resistance change memory
US20160180929A1 (en) * 2014-12-18 2016-06-23 YounSeon KANG Variable Resistance Memory Device
JP2016134193A (en) 2015-01-21 2016-07-25 力旺電子股▲分▼有限公司 Memory cell array of resistance change type random access memory
CN106205681A (en) 2015-04-29 2016-12-07 复旦大学 The framework disturbed for three-dimensional vertical stacking resistance-variable storing device suppression IR drop voltage drop and read-write and operative algorithm
US20160380030A1 (en) * 2015-06-23 2016-12-29 Stmicroelectronics (Crolles 2) Sas Resistive memory cell having a compact structure
US9514810B1 (en) 2016-02-08 2016-12-06 Freescale Semiconductor, Inc. Resistive non-volatile memory cell and method for programming same
CN108735262A (en) 2017-04-19 2018-11-02 华邦电子股份有限公司 Variable resistance type random access memory

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
"Office Action of China Counterpart Application", dated Sep. 10, 2021, p. 1-p. 18.
"Office Action of Japan Counterpart Application", dated Aug. 26, 2020, p. 1-p. 5.
"Office Action of Japan Counterpart Application", dated Feb. 12, 2020, p. 1-p. 6.
"Office Action of Korea Counterpart Application", dated Sep. 18, 2021, p. 1-p. 10.
Office Action of Korean Counterpart Application, with English translation thereof, dated Mar. 24, 2021, pp. 1-9.
Office Action of Taiwan Counterpart Application, dated Mar. 25, 2021, pp. 1-7.

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