JP2003249073A - Magnetic random access memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MRAM having cell array structure being suitable for high integration of a cell. <P>SOLUTION: A read block BK11 is constituted of a plurality of TMR elements 12 laminated in the longitudinal direction. One end of the TMR elements 12 in the read block BK11 is connected to a source line SL1 through a read selection switch RSW. The source line SL1 is extended in the direction of Y and connected to a ground point through a column selection switch 29C. The other end of the TMR element 12 is connected respectively and independently to read/write bit lines BL1, BL2, BL3, BL4. The read/write bit lines BL1, BL2, BL3, BL4 are extended in the direction of Y, and connected to a read circuit 29 through the column selection switch 29C. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a magnetic resistance (Magnet)
o "1", "0" -magnetic random access memory (MRAM: Ma) that stores data by utilizing the Resistive effect
gnetic Random Access Memory).

[0002]

2. Description of the Related Art In recent years, many memories for storing data have been proposed based on a new principle. One of them is a tunneling magnetoresistive (Tunneling Magneto Resistiv
e: Hereinafter, referred to as TMR. ) There is a magnetic random access memory for storing "1", "0" -data by utilizing the effect.

As a proposal of a magnetic random access memory, for example, ISSCC2000 by Roy Scheuerlein et.al.
Technical Digest p.128 `` A 10ns Read and Write Non
-Volatile Memory Array Using a Magnetic Tunnel Jun
"ction and FET Switch in each Cell" is known.

The magnetic random access memory stores "1", "0" -data by the TMR element. TMR
The basic structure of the element is a structure in which an insulating layer (tunnel barrier) is sandwiched between two magnetic layers (ferromagnetic layers). However, regarding the structure of the TMR element, MR (Magneto Resi
Various structures have been proposed in order to optimize the stive ratio (for the MR ratio and the structure of the TMR element, for example, Japanese Patent Application Nos. 2000-296082 and 2001-3).
7140).

The data stored in the TMR element is judged by whether the magnetization states of the two magnetic layers are parallel or antiparallel. Here, parallel means that the magnetization directions of the two magnetic layers are the same, and antiparallel means that the magnetization directions of the two magnetic layers are opposite.

Usually, an antiferromagnetic layer is attached to one (fixed layer) of the two magnetic layers. The antiferromagnetic layer is a member for fixing the magnetization direction of the fixed layer. Therefore, in reality, the data (“1” or “0”) stored in the TMR element is determined by the magnetization direction of the other one (free layer) of the two magnetic layers.

When the magnetization states of the TMR element are parallel, the tunnel resistance of the insulating layer (tunnel barrier) sandwiched between the two magnetic layers constituting the TMR element is the lowest. For example, let this state be a "1" -state. Further, when the magnetization states of the TMR element are antiparallel, the tunnel resistance of the insulating layer (tunnel barrier) sandwiched between the two magnetic layers forming the TMR element becomes the highest. For example, let this state be a "0" -state.

[0008]

Regarding the cell array structure of the magnetic random access memory, various structures are currently being studied from the viewpoint of increasing the memory capacity and stabilizing the write / read operation.

For example, at present, one memory cell is
One MOS transistor and one TMR element (or MT
A cell array structure composed of J (Magnetic Tunnel Junction) elements is known. In addition, a magnetic random access memory having such a cell array structure and storing 1-bit data by using two memory cell arrays is also known in order to realize stabilization of the read operation.

However, it is difficult to increase the memory capacity of these magnetic random access memories. This is because in these cell array structures, one TMR element corresponds to one MOS transistor.

By the way, for example, Japanese Patent Application No. 2000-296.
No. 082 and Japanese Patent Application No. 2001-350013 propose an array structure in which a plurality of TMR elements are connected in parallel. According to this cell array structure, since one MOS transistor corresponds to a plurality of TMR elements, the memory capacity is larger than that of a cell array structure in which one memory cell is composed of one TMR element and one MOS transistor. Can be increased.

However, even in the techniques disclosed in Japanese Patent Application Nos. 2000-296082 and 2001-350013, the TMR elements are arranged two-dimensionally in one plane, so that the TMR elements are integrated with high density. Can't do enough.

Therefore, a technique proposed to solve this problem is a technique for arranging TMR elements three-dimensionally on a semiconductor substrate. That is, in this technique, one MOS transistor (selection transistor) formed in the surface region of the semiconductor substrate is associated with a plurality of TMR elements connected in series or in parallel, and these TMR elements are associated with each other. A plurality of layers are stacked on one MOS transistor.

Regarding this technique, for example, Japanese Patent Application No. 200
No. 1-365236. According to this technique, a plurality of TMR elements are stacked on one MOS transistor in a plurality of stages, which is convenient for increasing the memory capacity of the memory cell array.

By the way, in the techniques disclosed in Japanese Patent Application No. 2000-296082 and Japanese Patent Application No. 2001-350013, the so-called destructive read operation principle is applied to the read operation. As described in detail in these documents, the destructive read operation principle is such that one read operation basically consists of two read steps and two write steps, so that the read time becomes long. , There is a problem.

On the other hand, Japanese Patent Application No. 2001-365236
In the technique disclosed in JP-A No. 2004-242242, the resistance ratios of a plurality of TMR elements connected in series or in parallel in the read block are made different from each other, so that a plurality of TMR elements in the read block can be formed by only one read step. The data of can be read at once.

However, in the technique disclosed in Japanese Patent Application No. 2001-365236, the resistance ratios of a plurality of TMR elements connected in series or in parallel in the read block must be different from each other, so that the structure of the TMR element and The manufacturing method becomes complicated. Further, since the read data is a mixture of data of a plurality of TMR elements, an A / D conversion circuit and a logic circuit for extracting the data of each TMR element from the read data are required, which complicates the read circuit. Become.

The present invention has been made in view of the above problems, and an object thereof is to propose a magnetic random access memory having a novel cell array structure suitable for increasing the memory capacity and a manufacturing method thereof. , Proposing a new read operation principle suitable for the new cell array structure and capable of high-speed read, and proposing a read circuit for realizing the new read operation principle.

[0019]

Means for Solving the Problems (1) Magnetic Random Access Memory A magnetic random access memory according to the present invention includes a plurality of memory cells for storing data by utilizing a magnetoresistive effect stacked in a plurality of stages, and a plurality of the plurality of memory cells. A read selection switch commonly connected to one end of the memory cell, and a plurality of bit lines provided corresponding to the plurality of memory cells and extending in the first direction, each of the plurality of memory cells being The ends are independently connected to one of the plurality of bit lines, and the plurality of bit lines are electrically isolated from each other during a read operation.

The read selection switch is arranged immediately below the plurality of memory cells.

The magnetic random access memory of the present invention comprises:
The memory cell further includes a plurality of contact plugs that connect one end of the plurality of memory cells and the read selection switch.

The magnetic random access memory of the present invention comprises:
It further comprises a source line connected to the read selection switch and extending in the first direction.

The magnetic random access memory of the present invention comprises:
A power supply terminal and a column selection switch connected between the source line and the power supply terminal are further provided.

The magnetic random access memory of the present invention comprises:
A read word line connected to a control terminal of the read selection switch and extending in a second direction intersecting the first direction is further provided.

The read selection switch is controlled by a row address signal.

The magnetic random access memory of the present invention comprises:
A read word line connected to the read selection switch and extending in a second direction intersecting the first direction is further provided.

The magnetic random access memory of the present invention comprises:
A decode line connected to the control terminal of the read selection switch and extending in the first direction is further provided.

The read selection switch is controlled by a column address signal.

The magnetic random access memory of the present invention comprises:
It further comprises a read circuit and a column selection switch connected between the plurality of bit lines and the read circuit.

The read selection switch and the column selection switch perform the same operation.

The read circuit is composed of a plurality of sense amplifiers provided corresponding to the plurality of bit lines and a plurality of output buffers provided corresponding to the plurality of sense amplifiers.

The read circuit includes a plurality of sense amplifiers provided corresponding to the plurality of bit lines, an output buffer for outputting data of one of the plurality of sense amplifiers, and the plurality of sense amplifiers. And a selector connected between the output buffer and the output buffer.

The magnetic random access memory of the present invention comprises:
A write bit line driver / sinker, which is connected to both ends of each of the plurality of bit lines and is configured to flow a write current in a direction corresponding to write data to the plurality of bit lines, is further provided.

The plurality of bit lines function as a read bit line and a write bit line.

The magnetic random access memory of the present invention comprises:
A plurality of write word lines provided corresponding to the plurality of memory cells and extending in a second direction intersecting the first direction are further provided.

Each of the plurality of write word lines is arranged on one end side of the plurality of memory cells.

The magnetic random access memory of the present invention comprises:
The memory cell further includes a plurality of block selection switches connected between the other ends of the plurality of memory cells and the plurality of bit lines.

The block selection switch is controlled by a row address signal.

The read selection switch and the block selection switch perform the same operation.

The plurality of memory cells form one read block, and the data of the plurality of memory cells are
It is read at the same time.

Each of the plurality of memory cells has a pinned layer whose magnetization direction is fixed, a storage layer whose magnetization direction changes according to write data, and a tunnel which is arranged between the pinned layer and the storage layer. It is composed of a magnetic memory element including a barrier layer.

The easy axis of magnetization of the magnetic memory element is oriented in the second direction intersecting with the first direction.

The read selection switch is any one of a MIS transistor, a MES transistor, a junction transistor, a bipolar transistor and a diode.

The value of the data to be written in the memory cells is determined by the direction of the write current flowing in the bit lines.

The magnetic random access memory of the present invention is
Stacked first and second memory cells for storing data using a magnetoresistive effect, a read selection switch connected to one end of the first and second memory cells, and the other end of the first memory cell And a second bit line connected to the other end of the second memory cell, the first and second bit lines being electrically separated from each other during a read operation. It

(2) Read Method The read method of the magnetic random access memory according to the present invention corresponds to a read block composed of a plurality of memory cells for storing data by utilizing a magnetoresistive effect and the plurality of memory cells. Applied to a magnetic random access memory having a plurality of sense amplifiers provided, a step of causing a read current to flow simultaneously and independently to the plurality of memory cells; and based on the read current, the data of the plurality of memory cells The method comprises the steps of detecting with a plurality of sense amplifiers, and the step of outputting the data of the plurality of sense amplifiers simultaneously.

The read method of the magnetic random access memory of the present invention comprises a read block composed of a plurality of memory cells for storing data by utilizing a magnetoresistive effect, and a plurality of sense blocks provided corresponding to the plurality of memory cells. Applied to a magnetic random access memory having an amplifier, and applying a read current to the plurality of memory cells simultaneously and independently, and based on the read current, data of the plurality of memory cells is read by the plurality of sense amplifiers. And a step of selectively outputting data of one of the plurality of sense amplifiers.

The data of the plurality of memory cells are independently detected by the plurality of sense amplifiers.

The other ends of the plurality of memory cells are short-circuited, and the read current flows from one end side to the other end side of the plurality of memory cells.

The plurality of sense amplifiers detect the data in the plurality of memory cells by comparing the read potential generated from the read current with the reference potential.

The reference potential is generated by using a resistance element having the same structure as the memory cell.

When reading data from the plurality of memory cells, a ground potential is applied to one end of the plurality of memory cells.

When the data of the plurality of memory cells is not read, one end of the plurality of memory cells is in a short-circuited state and the other end is in a floating state.

(3) Manufacturing Method A method of manufacturing a magnetic random access memory according to the present invention comprises a step of forming a read selection switch in a surface region of a semiconductor substrate, and a first write word extending on the read selection switch in a first direction. Forming a line, forming a first MTJ element directly above the first write word line, and directly above the first MTJ element, contacting the first MTJ element and crossing the first direction. Forming a first read / write bit line extending in a direction, forming a second write word line extending in the first direction directly above the first write word line, and forming a second write word line immediately above the second write word line. Forming a second MTJ element on the second MTJ element, and contacting the second MTJ element directly above the second MTJ element in the second direction. Forming a second read / write bit line extending.

At least one of the first and second write word lines and the first and second read / write bit lines is formed by a damascene process.

At least one of the first and second write word lines and the first and second read / write bit lines includes a step of forming a wiring groove in an insulating layer, and a metal layer which completely fills the wiring groove. Forming a
And a step of removing the metal layer other than in the wiring groove.

The method of manufacturing a magnetic random access memory according to the present invention comprises a step of forming a barrier metal layer before forming the metal layer.

In the method of manufacturing a magnetic random access memory according to the present invention, before forming the barrier metal layer, a step of forming a sidewall insulating layer on the side wall of the wiring groove, and the metal layer other than in the wiring groove are formed. Is removed, and a cap insulating layer made of the same material as the sidewall insulating layer is formed on the metal layer.

The sidewall insulating layer and the cap insulating layer are composed of silicon nitride.

[0060]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The magnetic random access memory of the present invention will be described in detail below with reference to the drawings.

1. The first feature of the magnetic random access memory of the present invention is
It has a cell array structure of a memory cell array.

The magnetic random access memory of the present invention has a cell array structure in which a plurality of TMR elements (or MTJ elements) are stacked in a plurality of stages in a direction (vertical direction) perpendicular to the surface of the semiconductor substrate. In addition, a plurality of Ts stacked in a plurality of stages forming the read block are provided.
One ends of the MR elements are commonly connected, and the other ends are independently connected to the read bit line. That is, the TMR elements and the read bit lines in the read block have a one-to-one correspondence.

The second characteristic of the magnetic random access memory of the present invention is the read operation principle.

As the read operation principle of the magnetic random access memory, at present, the destructive read operation principle disclosed in Japanese Patent Application No. 2000-296082 and Japanese Patent Application No. 2001-350013, and the collective read operation disclosed in Japanese Patent Application No. 2001-365236. The operating principle is also known. The present invention proposes the optimum read operation principle for the magnetic random access memory having the above-mentioned first characteristic, which is different from these read operation principles.

The third feature of the magnetic random access memory of the present invention is the configuration of the read circuit. In the magnetic random access memory having the first feature, when the read operation principle which is the second feature is adopted, a read circuit for executing the read operation principle is required. Therefore, the present invention proposes a specific example of a read circuit for executing the read operation principle which is the second feature.

The fourth characteristic of the magnetic random access memory of the present invention is the method of manufacturing the magnetic random access memory. In the magnetic random access memory having the first feature, the plurality of TMR elements forming the read block are stacked in a plurality of stages, one end of each of the plurality of TMR elements is commonly connected, and the other ends are independently connected. It is connected to the read bit line. The present invention proposes a manufacturing method for realizing such a cell array structure.

2. Cell Array Structure First, the cell array structure of the magnetic random access memory of the present invention will be described.

The features of the cell array structure relating to the present invention are as follows.
First, a plurality of TMR elements (or MTJ elements) are stacked in a plurality of stages in a direction (vertical direction) perpendicular to the surface of a semiconductor substrate, and secondly, a plurality of these read elements constituting one read block. This is in that one end of a plurality of TMR elements stacked in a row is commonly connected and the other ends are independently connected to a read bit line. That is, the TMR elements and the read bit lines in the read block have a one-to-one correspondence.

With this cell array structure, TM
Since the R element is three-dimensionally arranged on the semiconductor substrate and one MOS transistor (readout selection switch) can be associated with a plurality of TMR elements, as a result, it contributes to an increase in memory capacity. You can

Further, since the other ends of the plurality of TMR elements stacked in a plurality of stages forming the read block are independently connected to the read bit line, the destructive read operation principle or the batch read operation principle does not apply. The data of the TMR element can be read at high speed by a simple read operation principle.

(1) Structural Example 1 Structural example 1 shows an example in which one read block is composed of four TMR elements.

Circuit Structure First, the circuit structure will be described. FIG. 1 shows a main part of a magnetic random access memory as Structural Example 1 of the present invention. FIG. 2 shows an example of the column selection switch of FIG.

The memory cell array 11 comprises a plurality of TMR elements 1 arranged in an array in the X, Y and Z directions.
Have two. Here, the Z direction means a direction perpendicular to the paper surface orthogonal to the X direction and the Y direction.

In this example, the memory cell array 11 includes j TMR elements 12 arranged in the X direction, n TMR elements 12 arranged in the Y direction, and four TMR elements stacked in the Z direction. (MTJ1, MTJ2, MTJ3,
MTJ4) 12.

The number of TMR elements 12 stacked in the Z direction is four in this example, but the number may be any number as long as it is plural.

The four TMR elements 12 stacked in the Z direction form one read block BKik (i = 1, 1).
2, ... J, k = 1, 2, ... N). Four TMR elements 1 in the read block BKik
2 actually overlap each other in the direction perpendicular to the paper surface (Z direction).

In this example, one row is composed of j read blocks BKik arranged in the X direction.
The memory cell array 11 has n rows. Also,
One column is composed of n read blocks BKik arranged in the Y direction. Memory cell array 11
Has j columns.

Four TMR elements 1 in the block BKik
One end of 2 is commonly connected and, for example, via a read selection switch (block selection switch or row selection switch) RSW composed of a MOS transistor, a source line SLi (i = 1, 2, ... J). Connected to.
The source line SLi extends in the Y direction and, for example, only one source line is provided in one column.

The source line SLi is connected to the ground point VSS via the column selection switch 29C composed of, for example, a MOS transistor.

In the read operation, in the selected row, the read selection switch RS in the read block BKik is selected.
W is turned on. In the selected column, the column selection switch 29C is turned on, so that the potential of the source line SLi becomes the ground potential VSS. That is, the read current flows only to the TMR element 12 in the read block BKik located at the intersection of the selected row and the selected column.

At the time of reading, in the non-selected columns,
Since the column selection switch 29C is in the off state, the other ends of the TMR elements 12 in the read block BKik of the non-selected column are short-circuited with each other.

In this case, read bit lines BL4 (j-1) +1, BL4 (j-1) +2, B in the non-selected columns
If the potentials of L4 (j-1) +3 and BL4 (j-1) +4 are different, it may affect the read operation.
Read bit line BL4 (j-1) + in the non-selected column
1, BL4 (j-1) +2, BL4 (j-1) + 3, B
The potentials of L4 (j-1) +4 are set to the same potential (for example, ground potential).

During the read operation, the TMR element 12 in the read block BKik of the non-selected row is in the non-selected row because the block selection switch RSW is in the off state.
The other ends of are also short-circuited with each other.

Here, the TMR element 1 in the read block BKik belonging to the selected column and unselected row.
It is also possible that the short circuit of 2 affects the read operation of the TMR element 12 in the selected read block BKik belonging to the selected row and column.

Therefore, for example, as shown in FIG. 3, a block selection switch BSW composed of a MOS transistor is newly provided in each read block BKik, and the selected read belonging to the selected row and column is selected. Only the TMR elements 12 in the block BKik have read bit lines BL4 (j-1) +1 and BL4 (j-1).
Alternatively, +2, BL4 (j-1) +3, BL4 (j-1) +4 may be electrically connected, and the read current may flow only to these TMR elements.

Four TMs in the read block BKik
The other ends of the R elements 12 are independently read bit lines BL4 (j-1) +1, BL4 (j-1) +2, BL4.
(J-1) +3, BL4 (j-1) +4.
That is, four TMs in one read block BKik
Corresponding to the R element 12, four read bit lines BL4 (j-1) +1, BL4 (j- are provided in one column.
1) +2, BL4 (j-1) +3, BL4 (j-1) +
4 are arranged.

Read bit line BL4 (j-1) +1,
BL4 (j-1) +2, BL4 (j-1) +3, BL4
(J-1) +4 extends in the Y direction, and one end thereof is connected to the common data line 30 via the column selection switch (MOS transistor) 29C. Common data line 30
Is connected to a read circuit (including, for example, a sense amplifier, a selector, and an output buffer) 29B.

A column selection line signal CSLi (i = 0, 1, ... J) is input to the column selection switch 29C. The column decoder 32 uses the column selection line signal CSLi.
Is output.

In this example, the read bit line BL4 (j-
1) +1, BL4 (j-1) +2, BL4 (j-1) +
3, BL4 (j-1) +4 also function as a write bit line.

That is, the read / write bit line BL4
(J-1) +1, BL4 (j-1) +2, BL4 (j-
1) +3, BL4 (j-1) +4 has one end connected to a circuit block 29A including a column decoder and a write bit line driver / sinker, and the other end connected to a circuit block including a column decoder and a write bit line driver / sinker. 31 is connected.

At the time of writing operation, the circuit block 29
A and 31 are in the operating state. Then, the read / write bit lines BL4 (j-1) +1, BL4 (j-1) +
A write current flows through 2, BL4 (j-1) +3, BL4 (j-1) +4 in the direction toward the circuit block 29A or the circuit block 31, depending on the write data.

In the vicinity of the four TMR elements 12 forming the read block BKik, a plurality of (4 in this example) write word lines WWL4 (n-1) +1 extending in the X direction and stacked in the Z direction are provided. , WWL4 (n-1) +
2, WWL4 (n-1) +3, WWL4 (n-1) +4
Are placed. However, n is a row number, and n =
1, 2, ...

In this example, with respect to the write word lines extending in the X direction, one write word line is arranged in one stage in one row. That is, one write word line is made to correspond to one TMR element in the selected read block BKik. In this case, the number of write word lines in one row extending in the X direction is the same as the number of stages in which the TMR elements 12 are stacked.

As shown in FIGS. 95 and 96, with respect to the write word line, a plurality of TMR elements (in the upper stage) are taken into consideration in consideration of flattening of the insulating film immediately below the TMR element 12 and reduction in manufacturing cost. (TMR element and lower TMR element)
Therefore, one write word line may be shared.

The specific structure of the TMR element in the block and its vicinity will be described in detail in the item of device structure.

Write word line WWL4 (n-1) +
1, WWL4 (n-1) +2, WWL4 (n-1) +
3, WWL4 (n-1) +4 has one end connected to the write word line driver 23A-n and the other end connected to the write word line sinker 24-n.

The gate of the read selection switch (MOS transistor) RSW has a read word line RWLn (n
= 1, 2, ...). Read word line R
Only one WLn is arranged in one row and it is common to a plurality of blocks BKjk arranged in the X direction.

For example, when one column is composed of four blocks, the number of read word lines RWLn is
It will be four. The read word line RWLn extends in the X direction, and one end thereof is read word line driver 23B-n.
Connected to.

By the way, one read block BKj
When k has a circuit structure as shown in FIG. 3, the read word line RWLn is also connected to the gate of the block selection switch (MOS transistor) BSW.

That is, when the circuit structure as shown in FIG. 3 is adopted, the selected row, that is, the read word line R is selected.
Only the read selection switch RSW and the block selection switch BSW in the block BKjk existing in the row in which the potential of WLn becomes the “H” level are turned on.

The row decoder 25-n selects one of the plurality of rows based on the row address signal during the write operation. Write word line driver 23A-n
Is the write word line WWL4 (n
-1) +1, WWL4 (n-1) +2, WWL4 (n-
1) Supply write current to +3, WWL4 (n-1) +4. The write current is the write word line sinker 2
It is absorbed by 4-n.

The row decoder 25-n selects one of the plurality of rows based on the row address signal during the read operation. Read word line driver 23B-n
Supplies the read voltage (= "H") to the read word line RWLn in the selected row.

In the magnetic random access memory of this example,
One column is composed of a plurality of read blocks, and the plurality of TMR elements in each read block are connected to different read bit lines. Therefore, the data of a plurality of TMR elements in the read block can be read at once by one read step.

In addition, a plurality of TMRs in the read block
The elements are stacked in multiple stages on the semiconductor substrate, and
The read bit line also functions as a write bit line. That is, since it is not necessary to provide a wiring functioning only as a write bit line in the cell array, the cell array structure can be simplified.

Further, a read selection switch RSW and a block selection switch (in the case of FIG. 3) are provided in the read block, and a column selection switch is connected between the source line and the ground point. Therefore, during the read operation, the TMR elements in the unselected read block do not affect the read operation, and the read operation can be stabilized.

Device Structure 1 Next, the device structure will be described. 4 and 5
2 shows a device structure for one block of the magnetic random access memory as Structural Example 1 of the present invention.

FIG. 4 shows a magnetic random access memory 1
FIG. 5 shows a Y-direction cross section of a block, and FIG. 5 shows a X-direction cross section of one block of the magnetic random access memory. The elements shown in FIGS. 4 and 5 are denoted by the same reference numerals as those in FIGS. 1 to 3 so as to correspond to the elements of the circuits in FIGS. 1 to 3.

In the surface area of the semiconductor substrate 41, a read selection switch (MOS transistor) RSW is arranged. The source of the read selection switch RSW is connected to the source line SLi via the contact plug 42F.
The source line SLi extends, for example, in a straight line in the Y direction (column direction), and is connected to a ground point via a column selection switch provided in the peripheral portion of the memory cell array region.

The gate of the read selection switch (MOS transistor) RSW is the read word line RWLn. The read word line RWLn extends in the X direction. Four T's are provided on the read selection switch RSW.
MR element (MTJ (Magnetic Tunnel Junction) element) M
TJ1, MTJ2, MTJ3, MTJ4 are stacked in a plurality of stages.

TMR elements MTJ1, MTJ2, MTJ
3, one end (lower end in this example) of MTJ4 is lower electrode 4
4A, 44B, 44C, 44D. The contact plugs 42A, 42B, 42C, 42D, 42E and the intermediate layer 43 include lower electrodes 44A, 44B, 44C, 44.
D is electrically connected to each other, and the lower electrodes 44A,
44B, 44C and 44D are read out and selected switch RSW
Electrically connected to the drain of.

TMR elements MTJ1, MTJ2, MTJ
3, the other end of MTJ4 (upper end in this example) is read /
It is electrically connected to the write bit lines BL1, BL2, BL3, BL4. Read / write bit line BL
1, BL2, BL3, BL4 are in Y direction (column direction)
Extends to.

TMR elements MTJ1, MTJ2, MTJ
3, MTJ4 are independently connected to the read / write bit lines BL1, BL2, BL3, BL4.
That is, the four TMR elements MTJ1, MTJ2, MTJ
For 3, MTJ4, four read / write bit lines BL1, BL2, BL3, BL4 are provided.

Write word lines WWL1, WWL2, W
WL3 and WWL4 are TMR elements MTJ1, MTJ2,
It is arranged immediately below MTJ3 and MTJ4 and in the vicinity thereof. Write word lines WWL1, WWL2, W
WL3 and WWL4 extend in the X direction (row direction).

In this example, four TMR elements MTJ1, M
Four write word lines WWL1, WWL2, WWL3, WWL4 are provided for TJ2, MTJ3, MTJ4.

In this example, the TMR elements MTJ1, MJ
On top of TJ2, MTJ3, MTJ4, Y
Read / write bit lines BL1, BL extending in the direction
2, BL3, BL4 are arranged, and write word lines WWL1, WWL2, WWL extending in the X direction are arranged below them.
3, WWL4 are arranged.

However, the read / write bit lines BL1, BL2, BL3, BL4 and the write word lines WWL1, WWL2, WWL3, WWL4 for the TMR element are used.
The positional relationship of is not limited to this.

For example, as shown in FIGS. 97 and 98,
Read / write bit lines BL1, BL2, BL3, BL4 extending in the Y direction are arranged below the TMR elements MTJ1, MTJ2, MTJ3, MTJ4.
A write word line WWL extending in the X direction is provided above it.
1, WWL2, WWL3, WWL4 may be arranged.

Further, as shown in FIGS. 99 and 100,
With respect to the write word line, one write word is composed of a plurality of TMR elements (upper TMR element and lower TMR element) in consideration of flattening of the insulating film immediately below the TMR element 12 and reduction of manufacturing cost. You may make it share a line.

According to such a device structure, the plurality of TMR elements MTJ1, MTJ2 in the read block are
MTJ3 and MTJ4 are connected to different read / write bit lines BL1, BL2, BL3 and BL4, respectively. Therefore, a plurality of TMR elements MTJ1, MTJ2 in the read block are read by one read step.
The data of MTJ3 and MTJ4 can be read at one time.

In addition, a plurality of TMRs in the read block
The elements MTJ1, MTJ2, MTJ3, MTJ4 are stacked in a plurality of stages on the semiconductor substrate 41, and the wirings extending in the Y direction are read / write bit lines BL1, B.
Only L2, BL3 and BL4. Therefore, even if the number of stacked stages of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 is increased, the cell array structure does not become complicated.

FIG. 6 shows the positional relationship between the TMR element, the write word line, and the read / write bit line in the device structure shown in FIGS. 4 and 5. 4 and 5
In the device structure, the lower electrodes 44A, 44B, 44C, 44D, the write word lines WWL1, WWL2, WWL3, WWL4 are arranged in each stage of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 stacked in a plurality of stages.
And read / write bit lines BL1, BL2, BL
3, BL4 are arranged.

These layouts are set to be the same in each stage of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4, for example.

Lower electrodes 44A, 44B, 44C, 44D
Has, for example, a rectangular pattern, and a contact region for the contact plugs 42A to 42E is provided in a part thereof. In addition, the lower electrodes 44A, 44B, 44
The other parts of C and 44D have TMR elements MTJ1 and MT
J2, MTJ3 and MTJ4 are arranged.

TMR elements MTJ1, MTJ2, MTJ
3, MTJ4 are write word lines WWL1, WWL
2, WWL3, WWL4 and read / write bit lines BL1, BL2, BL3, BL4.

Structural Example of TMR Element FIGS. 7 to 9 show structural examples of a TMR element. The TMR element shown in the example of FIG. 7 has the most basic structure,
It has two ferromagnetic layers and a tunnel barrier layer sandwiched between them.

Among the two ferromagnetic layers, an antiferromagnetic layer for fixing the magnetization direction is added to the fixed layer (pin layer) whose magnetization direction is fixed. Of the two ferromagnetic layers
The magnetization direction of the free layer (memory layer) whose magnetization direction can be freely changed is determined by the synthetic magnetic field created by the write word line and the write bit line.

The TMR element shown in the example of FIG. 8 is provided with two tunnel barrier layers in the TMR element for the purpose of increasing the bias voltage as compared with the TMR element of the example of FIG.

It can be said that the TMR element of FIG. 8 has a structure (double junction structure) in which two TMR elements of FIG. 7 are connected in series.

In this example, the TMR element has three ferromagnetic layers, and a tunnel barrier layer is arranged between them. An antiferromagnetic layer is added to each of the two ferromagnetic layers (pin layers) at both ends. Of the three ferromagnetic layers, the free layer (memory layer) whose magnetization direction can be changed freely.
Is the middle ferromagnetic layer.

The TMR element shown in the example of FIG. 9 makes it easier to close the lines of magnetic force in the ferromagnetic layer as the storage layer than the TMR element of the example of FIG.

In the TMR element of this example, the memory layer of the TMR element of FIG. 7 is replaced with a memory layer composed of two ferromagnetic layers and a nonmagnetic metal layer (eg, aluminum) sandwiched between them. It can be said that

Since the storage layer of the TMR element has a three-layer structure consisting of two ferromagnetic layers and a non-magnetic metal layer sandwiched between them, the storage layer has two ferromagnetic layers. The lines of magnetic force are easier to close. That is, since it is possible to prevent the demagnetizing field component from being generated in the two ferromagnetic layers forming the storage layer, it is possible to improve the MR ratio.

Although the structural example of the TMR element has been described above, the present invention (circuit structure, device structure, read operation principle, read circuit and manufacturing method) is related to the TMR element.
The structure of the element is not particularly limited. The three structural examples described above are merely shown as typical examples of the structure of the TMR element.

(2) Structural Example 2 Structural example 2 is a modification of structural example 1. The characteristic of the structure example 2 is in the direction of the read selection switch as compared with the structure example 1. That is, the structure example 2 has a structure in which the read selection switch of the structure example 1 is rotated by 90 °.

Circuit Structure First, the circuit structure will be described. FIG. 10 shows a main part of a magnetic random access memory as Structural Example 2 of the present invention. The circuit diagram of FIG. 10 corresponds to the circuit diagram of FIG. The outline of the memory cell array and its peripheral portion in Structural Example 2 is the same as that in FIG.

Four TMR elements M in the block BK11
One end of each of TJ1, MTJ2, MTJ3 and MTJ4 has, for example, a read selection switch (block selection switch or row selection switch) composed of a MOS transistor.
It is connected to the source line SL1 via RSW.

In the read selection switch RSW, the line connecting the source and the drain is parallel to the X direction. That is, the channel length of the read selection switch RSW is the length in the X direction of the channel of the read selection switch RSW, and the channel width is the read selection switch RSW.
It is the width of the SW channel in the Y direction.

The gate of the read selection switch RSW is
The read word line RWL1 extending in the Y direction and extending in the X direction is coupled at a predetermined position.

The source line SL1 extends in the Y direction and, for example, only one source line SL1 is arranged in one column. Source line SL1
Is connected to a ground point via a column selection switch 29C composed of a MOS transistor, for example.

During the read operation, the read block BK1
If 1 is selected, the read selection switch RSW in the read block 11 is turned on. Further, since the column selection switch 29C is turned on, the potential of the source line SL1 becomes the ground potential. That is, the TMR elements MTJ1, MTJ2, M in the read block BK11
A read current flows through TJ3 and MTJ4.

Four TMs in the read block BK11
The other ends of the R elements MTJ1, MTJ2, MTJ3, MTJ4 are independently read bit lines BL1, BL2.
It is connected to BL3 and BL4. That is, the four TMR elements MTJ1, MTJ2, M in the read block BK11 are
Four read bit lines BL1, BL2, BL3, BL4 are arranged corresponding to TJ3, MTJ4.

Read bit lines BL1, BL2, BL
3 and BL4 extend in the Y direction, and one ends thereof are connected to the common data line 30 via a column selection switch (MOS transistor) 29C. The common data line 30 is connected to a read circuit (including, for example, a sense amplifier, a selector, and an output buffer) 29B.

A column selection line signal CSL1 is input to the column selection switch 29C. Column decoder 32
Outputs a column selection line signal CSL1.

In this example, the read bit lines BL1, BL
2, BL3 and BL4 also function as write bit lines.

That is, the read / write bit line BL
1, BL2, BL3, BL4 have one ends connected to a circuit block 29A including a column decoder and a write bit line driver / sinker, and the other ends connected to a circuit block 31 including a column decoder and a write bit line driver / sinker. It

In the write operation, the circuit block 29
A and 31 are in the operating state. Then, a write current flows through the read / write bit lines BL1, BL2, BL3, BL4 in the direction toward the circuit block 29A or the circuit block 31, depending on the write data.

Four TMR elements MTJ1, MTJ2, MTJ3, MTJ4 constituting the read block BK11.
In the vicinity of the plurality of (4 in this example) write word lines WWL1, which extend in the X direction and are stacked in the Z direction.
WWL2, WWL3 and WWL4 are arranged.

In this example, with respect to the write word lines extending in the X direction, one write word line is arranged in one stage in one row. That is, the read block BK1
One TMR element in 1 corresponds to one write word line. In this case, 1 extending in the X direction
The number of write word lines in a row depends on the TMR element MTJ.
It is the same as the number of stacking 1, MTJ2, MTJ3, MTJ4.

As shown in FIG. 101, for the write word line, the TMR elements MTJ1, MTJ2, M are used.
In consideration of the flattening of the insulating film immediately below TJ3 and MTJ4 and the reduction of manufacturing cost, a plurality of TMR elements (the upper TM
One write word line may be shared by the R element and the lower TMR element.

Write word lines WWL1, WWL2, W
One end of WL3 and WWL4 is connected to the write word line driver 23A-n, and the other end is connected to the write word line sinker 24-n.

The gate of the read selection switch (MOS transistor) RSW is connected to the read word line RWL1. Only one read word line RWL1 is arranged in one row and it is common to a plurality of blocks arranged in the X direction.

Row decoder 25-1 selects one of a plurality of rows based on a row address signal during a write operation. Write word line driver 23A-n
Is the write word lines WWL1, W in the selected row.
A write current is supplied to WL2, WWL3 and WWL4. The write current is absorbed by the write word line sinker.

Row decoder 25-1 selects one of a plurality of rows based on a row address signal during a read operation. Read word line driver 23B-1
Supplies a read voltage (= “H”) to the read word line RWL1 in the selected row.

In the magnetic random access memory of this example,
One column is composed of a plurality of read blocks, and the plurality of TMR elements in each read block are connected to different read bit lines. Therefore, the data of a plurality of TMR elements in the read block can be read at once by one read step.

In addition, a plurality of TMRs in the read block
The elements are stacked in multiple stages on the semiconductor substrate, and
The read bit line also functions as a write bit line. That is, since it is not necessary to provide a wiring functioning only as a write bit line in the cell array, the cell array structure can be simplified.

A read selection switch RSW is provided in the read block, and a column selection switch is connected between the source line and the ground point. Therefore, during the read operation, the TMR elements in the unselected read block rarely affect the read operation, and the read operation can be stabilized.

Device Structure Next, the device structure will be described. 11 and 1
2 shows the device structure for one block of the magnetic random access memory as Structural Example 2 of the present invention.

FIG. 11 shows a Y-direction cross section of one block of the magnetic random access memory, and FIG. 12 shows a X-direction cross section of one block of the magnetic random access memory. The elements shown in FIGS. 11 and 12 are denoted by the same reference numerals as those in FIG. 9 so as to correspond to the elements of the circuit in FIG.

In the surface area of the semiconductor substrate 41, a read selection switch (MOS transistor) RSW is arranged. The source of the read selection switch RSW is connected to the source line SLi via the contact plug 42F.
The source line SLi extends, for example, in a straight line in the Y direction (column direction), and is connected to a ground point via a column selection switch provided in the peripheral portion of the memory cell array region.

The gate of the read selection switch (MOS transistor) RSW is the read word line RWLn. The read word line RWLn extends in the X direction. Four T's are provided on the read selection switch RSW.
MR element (MTJ (Magnetic Tunnel Junction) element) M
TJ1, MTJ2, MTJ3, MTJ4 are stacked in a plurality of stages.

TMR elements MTJ1, MTJ2, MTJ
3, one end (lower end in this example) of MTJ4 is lower electrode 4
4A, 44B, 44C, 44D. The contact plugs 42A, 42B, 42C, 42D, 42E and the intermediate layer 43 include lower electrodes 44A, 44B, 44C, 44.
D is electrically connected to each other, and the lower electrodes 44A,
44B, 44C and 44D are read out and selected switch RSW
Electrically connected to the drain of.

TMR elements MTJ1, MTJ2, MTJ
3, the other end of MTJ4 (upper end in this example) is read /
It is electrically connected to the write bit lines BL1, BL2, BL3, BL4. Read / write bit line BL
1, BL2, BL3, BL4 are in Y direction (column direction)
Extends to.

TMR elements MTJ1, MTJ2, MTJ
3, MTJ4 are independently connected to the read / write bit lines BL1, BL2, BL3, BL4.
That is, the four TMR elements MTJ1, MTJ2, MTJ
For 3, MTJ4, four read / write bit lines BL1, BL2, BL3, BL4 are provided.

Write word lines WWL1, WWL2, W
WL3 and WWL4 are TMR elements MTJ1, MTJ2,
It is arranged immediately below MTJ3 and MTJ4 and in the vicinity thereof. Write word lines WWL1, WWL2, W
WL3 and WWL4 extend in the X direction (row direction).

In this example, four TMR elements MTJ1, M
Four write word lines WWL1, WWL2, WWL3, WWL4 are provided for TJ2, MTJ3, MTJ4.

In this example, the TMR elements MTJ1, MJ
On top of TJ2, MTJ3, MTJ4, Y
Read / write bit lines BL1, BL extending in the direction
2, BL3, BL4 are arranged, and write word lines WWL1, WWL2, WWL extending in the X direction are arranged below them.
3, WWL4 are arranged.

However, the read / write bit lines BL1, BL2, BL3, BL4 and the write word lines WWL1, WWL2, WWL3, WWL4 for the TMR element are used.
The positional relationship of is not limited to this.

For example, as shown in FIGS. 102 and 103, TMR elements MTJ1, MTJ2, MTJ3, MTJ.
4, the read / write bit lines BL1, BL2, BL3, BL4 extending in the Y direction are arranged below and the write word line WW extending in the X direction is arranged above them.
L1, WWL2, WWL3, WWL4 may be arranged.

Further, as shown in FIGS. 104 and 105, regarding the write word line, a plurality of TMR elements (in the upper stage) are taken into consideration in consideration of flattening of the insulating film immediately below the TMR element 12 and reduction of manufacturing cost. TMR element and lower TM
One write word line may be shared by R elements.

According to such a device structure, a plurality of TMR elements MTJ1, MTJ2 in the read block are arranged.
MTJ3 and MTJ4 are connected to different read / write bit lines BL1, BL2, BL3 and BL4, respectively. Therefore, a plurality of TMR elements MTJ1, MTJ2 in the read block are read by one read step.
The data of MTJ3 and MTJ4 can be read at one time.

Also, a plurality of TMRs in the read block
The elements MTJ1, MTJ2, MTJ3, MTJ4 are stacked in a plurality of stages on the semiconductor substrate 41, and the wirings extending in the Y direction are read / write bit lines BL1, B.
Only L2, BL3 and BL4. Therefore, even if the number of stacked stages of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 is increased, the cell array structure does not become complicated.

(3) Structural Example 3 Structural Example 3 is a modification of Structural Example 1. The feature of Structural Example 3 lies in the wiring connected to the gate and the source of the read selection switch, as compared with Structural Example 1.

That is, in Structural Example 3, the gate of the read selection switch is connected to the decode line, and the source thereof is
It is connected to the read word line. The read selection switch in the read block is selected by the column address signal.

Circuit Structure First, the circuit structure will be described. FIG. 13 shows a main part of a magnetic random access memory as Structural Example 3 of the present invention. FIG. 14 shows an example of the column selection switch shown in FIG.

The memory cell array 11 comprises a plurality of TMR elements 1 arranged in an array in the X, Y and Z directions.
Have two. Here, the Z direction means a direction perpendicular to the paper surface orthogonal to the X direction and the Y direction.

The memory cell array 11 includes j TMR elements 12 arranged in the X direction, n TMR elements 12 arranged in the Y direction, and four TMR elements 12 stacked in the Z direction.
It has a cell array structure including the MR element 12. The number of TMR elements 12 stacked in the Z direction is four, but the number may be any number as long as it is plural.

The four TMR elements 12 stacked in the Z direction form one read block BKik (i = 0,
1, ... J, k = 0, 1, ... N). Four TMR elements 1 in the read block BKik
2 actually overlap each other in the direction perpendicular to the paper surface (Z direction).

In this example, j read blocks BKik arranged in the X direction form one row.
The memory cell array 11 has n rows. Also,
One column is composed of n read blocks BKik arranged in the Y direction. Memory cell array 11
Has j columns.

Four TMR elements 1 in the block BKik
One end of 2 is connected to a read word line RWLn (n = 1, 2, ...) Through a read selection switch (block selection switch or row selection switch) RSW composed of a MOS transistor, for example. . The read word line RWLn extends in the X direction, and for example, only one read word line RWLn is provided in one row.

The gate of the read selection switch RSW is
It is connected to the decode line DLi (i = 1, 2, ... J). The decode line DLi extends in the Y direction, and for example, only one decode line is provided in one column. One end of the decode line DLi is connected to the column decoder 32.

In this example, the decode line DLi is connected to the column decoder 32. That is, the column selection switch existing in the same column and the read selection switch in the read block perform the same operation.

For example, when the column decoder 32 sets the column selection signal CSL1 to the "H" level, the column selection switch of the column to which the read blocks BK11, ... BK1n belong is turned on and the read blocks BK11 ,. The read selection switch RSW in BK1n is turned on.

In this example, the column selection signal CSLi (i = 1, 2, ... J) output from the column decoder 32 is used.
Is used to control both the column selection switch 29C and the read selection switch RSW in the read block BKik.

However, instead of this, for example, as shown in FIG. 15, a signal for controlling the column selection switch 29C and the read selection switch R in the read block BKik.
The signal controlling the SW may be different.

That is, in the example of FIG. 15, the column selection switch 29C is controlled by the column selection signal CSL1 output from the column decoder 32A, and the read selection switch RSW in the read block BK11 is output from the column decoder 32B. Block selection signal BSL1
Controlled by.

The read circuit will be described below.
The column decoder 32A and the column decoder 32B have exactly the same configuration.

In the read operation, the potential of the read word line RWLn becomes the “L” level in the selected row.
Further, in the selected column, the read selection switch RSW in the read block BKik is turned on as described above.

Therefore, T in the read block BKik located at the intersection of the selected row and the selected column.
A read current flows only in the MR element 12.

[0189] Note that at the time of reading, in the non-selected columns,
Read selection switch R in the read block BKik
Since the SW is in the OFF state, the other ends of the TMR elements 12 in the read block BKik of the non-selected column are short-circuited with each other.

In this case, read bit lines BL4 (j-1) +1, BL4 (j-1) +2, B in the non-selected column
If the potentials of L4 (j-1) +3 and BL4 (j-1) +4 are different, it may affect the read operation.
Read bit line BL4 (j-1) + in the non-selected column
1, BL4 (j-1) +2, BL4 (j-1) + 3, B
The potentials of L4 (j-1) +4 are set to the same potential (for example, ground potential).

In the read operation, in the selected column and unselected row, for example, the read word line RWLn is
It is set to a floating state (fixed potential, for example, the same potential as the selected bit line). in this case,
In the selected column and unselected row, the read selection switch RSW in the read block BKik is in the ON state, so that the other ends of the TMR elements 12 in the block BKik are short-circuited to each other.

Here, the TMR element 1 in the read block BKik belonging to the selected column and unselected row.
It is also possible that the short circuit of 2 affects the read operation of the TMR element 12 in the selected read block BKik belonging to the selected row and column.

Therefore, for example, as shown in FIG. 16, in each read block BKik, a block selection switch BSW newly formed of a MOS transistor is provided.
And the read bit lines BL4 (j−1) +1, BL4 (j−) are provided only to the TMR elements 12 in the selected read block BKik belonging to the selected row and column.
1) +2, BL4 (j-1) +3, BL4 (j-1) +
4 may be electrically connected, and the read current may flow through only these TMR elements.

Four TMs in the read block BKik
The other ends of the R elements 12 are independently read bit lines BL4 (j-1) +1, BL4 (j-1) +2, BL4.
(J-1) +3, BL4 (j-1) +4.
That is, four TMs in one read block BKik
Corresponding to the R element 12, four read bit lines BL4 (j-1) +1, BL4 (j- are provided in one column.
1) +2, BL4 (j-1) +3, BL4 (j-1) +
4 are arranged.

Read bit line BL4 (j-1) +1,
BL4 (j-1) +2, BL4 (j-1) +3, BL4
(J-1) +4 extends in the Y direction, and one end thereof is connected to the common data line 30 via the column selection switch (MOS transistor) 29C. Common data line 30
Is connected to a read circuit (including, for example, a sense amplifier, a selector, and an output buffer) 29B.

A column selection line signal CSLi (i = 1, 2, ... J) is input to the column selection switch 29C. The column decoder 32 uses the column selection line signal CSLi.
Is output.

In this example, the read bit line BL4 (j-
1) +1, BL4 (j-1) +2, BL4 (j-1) +
3, BL4 (j-1) +4 also function as a write bit line.

That is, the read / write bit line BL4
(J-1) +1, BL4 (j-1) +2, BL4 (j-
1) +3, BL4 (j-1) +4 has one end connected to a circuit block 29A including a column decoder and a write bit line driver / sinker, and the other end connected to a circuit block including a column decoder and a write bit line driver / sinker. 31 is connected.

In the write operation, the circuit block 29
A and 31 are in the operating state. Then, the read / write bit lines BL4 (j-1) +1, BL4 (j-1) +
A write current flows through 2, BL4 (j-1) +3, BL4 (j-1) +4 in the direction toward the circuit block 29A or the circuit block 31, depending on the write data.

In the vicinity of the four TMR elements 12 forming the read block BKik, a plurality of (4 in this example) write word lines WWL4 (n-1) +1 extending in the X direction and stacked in the Z direction are provided. , WWL4 (n-1) +
2, WWL4 (n-1) +3, WWL4 (n-1) +4
Are placed. However, n is a row number, and n =
1, 2, ...

In this example, with respect to the write word lines extending in the X direction, one write word line is arranged in one stage in one row. That is, one write word line is made to correspond to one TMR element in the selected read block BKik. In this case, the number of write word lines in one row extending in the X direction is the same as the number of stages in which the TMR elements 12 are stacked.

As shown in FIGS. 106 and 107, with respect to the write word line, a plurality of TMR elements (upper row in the upper stage are taken into consideration in consideration of flattening of the insulating film immediately below the TMR element 12 and reduction in manufacturing cost. TMR element and lower TM
One write word line may be shared by R elements.

The specific structure of the TMR element in the block and its vicinity will be described in detail in the item of device structure.

Write word line WWL4 (n-1) +
1, WWL4 (n-1) +2, WWL4 (n-1) +
3, WWL4 (n-1) +4 has one end connected to the write word line driver 23A-n and the other end connected to the write word line sinker 24-n.

The source of the read selection switch (MOS transistor) RSW is the read word line RWLn (n
= 1, 2, ...). Read word line R
Only one WLn is arranged in one row and it is common to a plurality of blocks BKjk arranged in the X direction.

By the way, one read block BKj
When k has a circuit structure as shown in FIG. 16, the read word line RWLn is connected to the block selection switch (MOS transistor) BS via an inverter, for example.
It is also connected to the W gate.

That is, when the circuit structure as shown in FIG. 16 is adopted, the block selection switch in the block BKjk existing in the selected row, that is, the row in which the potential of the read word line RWLn becomes the “L” level. BSW is turned on.

Further, the potential of the read word line RWLn of the selected row is at “L” level, and the read selection switch RS in the read block BKik of the selected column.
Since W is turned on, TMR in the selected read block BKik belonging to the selected row and column
Read bit line BL4 (j-1) + only for element 12
1, BL4 (j-1) +2, BL4 (j-1) + 3, B
L4 (j-1) +4 is electrically connected, and the read current flows only in these TMR elements.

The row decoder 25-n selects one of the plurality of rows based on the row address signal during the write operation. Write word line driver 23A-n
Is the write word line WWL4 (n
-1) +1, WWL4 (n-1) +2, WWL4 (n-
1) Supply write current to +3, WWL4 (n-1) +4. The write current is the write word line sinker 2
It is absorbed by 4-n.

The row decoder 25-n selects one of the plurality of rows based on the row address signal during the read operation. Read word line driver 23B-n
Supplies the read voltage (= "L") to the read word line RWLn in the selected row.

In the magnetic random access memory of this example,
One column is composed of a plurality of read blocks, and the plurality of TMR elements in each read block are connected to different read bit lines. Therefore, the data of a plurality of TMR elements in the read block can be read at once by one read step.

Also, a plurality of TMRs in the read block
The elements are stacked in multiple stages on the semiconductor substrate, and
The read bit line also functions as a write bit line. That is, since it is not necessary to provide a wiring functioning only as a write bit line in the cell array, the cell array structure can be simplified.

Further, a read selection switch RSW and a block selection switch (in the case of FIG. 16) are provided in the read block, the read selection switch is controlled by the output signal of the column decoder, and the block selection switch is It is controlled by the output signal of the row decoder. Therefore, during the read operation, the TMR elements in the unselected read block do not affect the read operation, and the read operation can be stabilized.

Device Structure Next, the device structure will be described. 17 and 1
8 shows the device structure for one block of the magnetic random access memory as Structural Example 3 of the present invention.

FIG. 17 shows a Y-direction cross section of one block of the magnetic random access memory, and FIG. 18 shows a X-direction cross section of one block of the magnetic random access memory. The elements shown in FIGS. 17 and 18 are denoted by the same reference numerals as those in FIGS. 13 to 16 so as to correspond to the elements of the circuits in FIGS. 13 to 16.

In the surface area of the semiconductor substrate 41, a read selection switch (MOS transistor) RSW is arranged. The source of the read selection switch RSW is connected to the read word line RWLn via the contact plug 42F. The read word line RWLn extends, for example, in a straight line in the X direction (row direction) and is connected to a read word line driver provided in the peripheral portion of the memory cell array region.

The gate of the read selection switch (MOS transistor) RSW is the decode line DLj. The decode line DLj extends in the Y direction in a part other than the cross section shown in the drawing. Readout selection switch RSW
Above the four TMR elements (MTJ (Magnetic Tunnel J
unction) element) MTJ1, MTJ2, MTJ3, MTJ
4 are stacked in multiple stages.

TMR elements MTJ1, MTJ2, MTJ
3, one end (lower end in this example) of MTJ4 is lower electrode 4
4A, 44B, 44C, 44D. The contact plugs 42A, 42B, 42C, 42D, 42E and the intermediate layer 43 include lower electrodes 44A, 44B, 44C, 44.
D is electrically connected to each other, and the lower electrodes 44A,
44B, 44C and 44D are read out and selected switch RSW
Electrically connected to the drain of.

TMR elements MTJ1, MTJ2, MTJ
3, the other end of MTJ4 (upper end in this example) is read /
It is electrically connected to the write bit lines BL1, BL2, BL3, BL4. Read / write bit line BL
1, BL2, BL3, BL4 are in Y direction (column direction)
Extends to.

TMR elements MTJ1, MTJ2, MTJ
3, MTJ4 are independently connected to the read / write bit lines BL1, BL2, BL3, BL4.
That is, the four TMR elements MTJ1, MTJ2, MTJ
For 3, MTJ4, four read / write bit lines BL1, BL2, BL3, BL4 are provided.

Write word lines WWL1, WWL2, W
WL3 and WWL4 are TMR elements MTJ1, MTJ2,
It is arranged immediately below MTJ3 and MTJ4 and in the vicinity thereof. Write word lines WWL1, WWL2, W
WL3 and WWL4 extend in the X direction (row direction).

In this example, four TMR elements MTJ1, M
Four write word lines WWL1, WWL2, WWL3, WWL4 are provided for TJ2, MTJ3, MTJ4.

In this example, the read / write bit lines BL1, BL2, BL3, BL4 extending in the Y direction are arranged above the TMR element and the write word line extending in the X direction is arranged below the TMR element. WWL1, WWL
2, WWL3 and WWL4 are arranged.

However, the read / write bit lines BL1, BL2, BL3, BL4 and the write word lines WWL1, WWL2, WWL3, WWL4 for the TMR element are used.
The positional relationship of is not limited to this.

For example, a read / write bit line BL extending in the Y direction is provided below the TMR element.
1, BL2, BL3, BL4 are placed and X
Write word lines WWL1, WWL2, W extending in the direction
WL3 and WWL4 may be arranged.

According to such a device structure, the plurality of TMR elements MTJ1, MTJ2 in the read block are
MTJ3 and MTJ4 are connected to different read / write bit lines BL1, BL2, BL3 and BL4, respectively. Therefore, a plurality of TMR elements MTJ1, MTJ2 in the read block are read by one read step.
The data of MTJ3 and MTJ4 can be read at one time.

Also, a plurality of TMRs in the read block
The elements MTJ1, MTJ2, MTJ3, MTJ4 are stacked in a plurality of stages on the semiconductor substrate 41, and the wirings extending in the Y direction are read / write bit lines BL1, B.
Only L2, BL3 and BL4. Therefore, even if the number of stacked stages of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 is increased, the cell array structure does not become complicated.

FIG. 19 shows the positional relationship between the TMR element, the write word line, and the read / write bit line in the device structure shown in FIGS. 17 and 18. FIG. 17
18 and the device structure of FIG. 18, the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 stacked in a plurality of stages.
Lower electrode 44A, 44B, 44C, 4
4D, write word lines WWL1, WWL2, WWL
3, WWL4 and read / write bit line BL1,
BL2, BL3, BL4 are arranged.

These layouts are set to be the same in each stage of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4, for example.

Lower electrodes 44A, 44B, 44C, 44D
Has, for example, a rectangular pattern, and a contact region for the contact plugs 42A to 42E is provided in a part thereof. In addition, the lower electrodes 44A, 44B, 44
The other parts of C and 44D have TMR elements MTJ1 and MT
J2, MTJ3 and MTJ4 are arranged.

TMR elements MTJ1, MTJ2, MTJ
3, MTJ4 are write word lines WWL1, WWL
2, WWL3, WWL4 and read / write bit lines BL1, BL2, BL3, BL4.

(4) Structural Example 4 Structural Example 4 is a modification of Structural Example 3. The characteristic of Structural Example 4 lies in the direction of the read selection switch, as compared with Structural Example 3. That is, the structure example 4 has a structure in which the read selection switch of the structure example 3 is rotated by 90 °.

Circuit Structure First, the circuit structure will be described. FIG. 20 shows a main part of a magnetic random access memory as Structural Example 4 of the present invention. The circuit diagram of FIG. 20 corresponds to the circuit diagram of FIG. The outline of the memory cell array and its peripheral portion in Structural Example 4 is the same as in FIG.

Four TMR elements M in the block BK11
One end of each of TJ1, MTJ2, MTJ3 and MTJ4 has, for example, a read selection switch (block selection switch or row selection switch) composed of a MOS transistor.
It is connected to the read word line RWL1 via RSW. The read word line RWL1 extends in the X direction.

In the read selection switch RSW, the line connecting the source and the drain is parallel to the X direction. That is, the channel length of the read selection switch RSW is the length in the X direction of the channel of the read selection switch RSW, and the channel width is the read selection switch RSW.
It is the width of the SW channel in the Y direction.

The gate of the read selection switch RSW is
It is connected to the decode line DL1. The decode line DL1 is
It extends in the Y direction. The decode line DL1 is connected to the column decoder 32. That is, the read selection switch R
SW is controlled by a decode signal CSL1 obtained by decoding the column address signal.

During the read operation, the read block BK1
If 1 is selected, CSL1 becomes “H”, and thus the read selection switch R in the read block 11 is selected.
SW is turned on. In addition, the read word line RWL
1 becomes "L (ground potential VSS)". Further, the column selection switch 29C is turned on.

Therefore, T in the read block BK11
A read current flows through the MR elements MTJ1, MTJ2, MTJ3, MTJ4.

Four TMs in the read block BK11
The other ends of the R elements MTJ1, MTJ2, MTJ3, MTJ4 are independently read bit lines BL1, BL2.
It is connected to BL3 and BL4. That is, the four TMR elements MTJ1, MTJ2, M in the read block BK11 are
Four read bit lines BL1, BL2, BL3, BL4 are arranged corresponding to TJ3, MTJ4.

Read bit lines BL1, BL2, BL
3 and BL4 extend in the Y direction, and one ends thereof are connected to the common data line 30 via a column selection switch (MOS transistor) 29C. The common data line 30 is connected to a read circuit (including, for example, a sense amplifier, a selector, and an output buffer) 29B.

A column selection line signal CSL1 is input to the column selection switch 29C. Column decoder 32
Outputs a column selection line signal CSL1.

In this example, the read bit lines BL1, BL
2, BL3 and BL4 also function as write bit lines.

That is, the read / write bit line BL
1, BL2, BL3, BL4 have one ends connected to a circuit block 29A including a column decoder and a write bit line driver / sinker, and the other ends connected to a circuit block 31 including a column decoder and a write bit line driver / sinker. It

In the write operation, the circuit block 29
A and 31 are in the operating state. Then, a write current flows through the read / write bit lines BL1, BL2, BL3, BL4 in the direction toward the circuit block 29A or the circuit block 31, depending on the write data.

Four TMR elements MTJ1, MTJ2, MTJ3, MTJ4 constituting the read block BK11.
In the vicinity of the plurality of (4 in this example) write word lines WWL1, which extend in the X direction and are stacked in the Z direction.
WWL2, WWL3 and WWL4 are arranged.

In this example, with respect to the write word lines extending in the X direction, one write word line is arranged in one stage in one row. That is, the read block BK1
One TMR element in 1 corresponds to one write word line. In this case, 1 extending in the X direction
The number of write word lines in a row depends on the TMR element MTJ.
It is the same as the number of stacking 1, MTJ2, MTJ3, MTJ4.

As shown in FIG. 112, regarding the write word line, TMR elements MTJ1, MTJ2, M are used.
In consideration of the flattening of the insulating film immediately below TJ3 and MTJ4 and the reduction of manufacturing cost, a plurality of TMR elements (the upper TM
One write word line may be shared by the R element and the lower TMR element.

Write word lines WWL1, WWL2, W
One end of WL3 and WWL4 is connected to the write word line driver 23A-n, and the other end is connected to the write word line sinker 24-n.

The gate of the read selection switch (MOS transistor) RSW is connected to the read word line RWL1. Only one read word line RWL1 is arranged in one row and it is common to a plurality of blocks arranged in the X direction.

Row decoder 25-1 selects one of a plurality of rows based on a row address signal during a write operation. Write word line driver 23A-n
Is the write word lines WWL1, W in the selected row.
A write current is supplied to WL2, WWL3 and WWL4. The write current is absorbed by the write word line sinker.

Row decoder 25-1 selects one of a plurality of rows based on a row address signal during a read operation. Read word line driver 23B-1
Supplies a read voltage (= "L") to the read word line RWL1 in the selected row.

In the magnetic random access memory of this example,
One column is composed of a plurality of read blocks, and the plurality of TMR elements in each read block are connected to different read bit lines. Therefore, the data of a plurality of TMR elements in the read block can be read at once by one read step.

In addition, a plurality of TMRs in the read block
The elements are stacked in multiple stages on the semiconductor substrate, and
The read bit line also functions as a write bit line. That is, since it is not necessary to provide a wiring functioning only as a write bit line in the cell array, the cell array structure can be simplified.

A read selection switch RSW is provided in the read block, and the read selection switch RSW is controlled by a decode signal CSL1 obtained by decoding the column address signal. The source of the read selection switch RSW is connected to the read word line. Therefore, the read operation can be stably performed with a simple configuration.

Device Structure Next, the device structure will be described. 21 and 2
2 shows a device structure for one block of the magnetic random access memory as Structural Example 4 of the present invention.

FIG. 21 shows a Y-direction section of one block of the magnetic random access memory, and FIG. 22 shows an X-direction section of one block of the magnetic random access memory. The elements shown in FIGS. 21 and 22 are denoted by the same reference numerals as those in FIG. 20 so as to correspond to the elements of the circuit in FIG.

In the surface area of the semiconductor substrate 41, a read selection switch (MOS transistor) RSW is arranged. The source of the read selection switch RSW is connected to the read word line RWLn via the contact plug 42F. The read word line RWLn extends in, for example, the X direction (row direction), and is connected to the read word line driver arranged in the peripheral portion of the memory cell array region.

The gate of the read selection switch (MOS transistor) RSW is the decode line DLj. The decode line DLj extends in the Y direction. The decode line DL1 is connected to a column decoder arranged in the peripheral portion of the memory cell array. Readout selection switch R
On the SW, four TMR elements (MTJ (Magnetic Tunn
el Junction) element) MTJ1, MTJ2, MTJ3, M
TJ4s are stacked in multiple stages.

TMR elements MTJ1, MTJ2, MTJ
3, one end (lower end in this example) of MTJ4 is lower electrode 4
4A, 44B, 44C, 44D. The contact plugs 42A, 42B, 42C, 42D, 42E and the intermediate layer 43 include lower electrodes 44A, 44B, 44C, 44.
D is electrically connected to each other, and the lower electrodes 44A,
44B, 44C and 44D are read out and selected switch RSW
Electrically connected to the drain of.

TMR elements MTJ1, MTJ2, MTJ
3, the other end of MTJ4 (upper end in this example) is read /
It is electrically connected to the write bit lines BL1, BL2, BL3, BL4. Read / write bit line BL
1, BL2, BL3, BL4 are in Y direction (column direction)
Extends to.

TMR elements MTJ1, MTJ2, MTJ
3, MTJ4 are independently connected to the read / write bit lines BL1, BL2, BL3, BL4.
That is, the four TMR elements MTJ1, MTJ2, MTJ
For 3, MTJ4, four read / write bit lines BL1, BL2, BL3, BL4 are provided.

Write word lines WWL1, WWL2, W
WL3 and WWL4 are TMR elements MTJ1, MTJ2,
It is arranged immediately below MTJ3 and MTJ4 and in the vicinity thereof. Write word lines WWL1, WWL2, W
WL3 and WWL4 extend in the X direction (row direction).

In this example, four TMR elements MTJ1, M
Four write word lines WWL1, WWL2, WWL3, WWL4 are provided for TJ2, MTJ3, MTJ4.

In this example, read / write bit lines BL1, BL2, BL3, BL4 extending in the Y direction are arranged above the TMR element, and write word lines extending in the X direction are arranged below the TMR element. WWL1, WWL
2, WWL3 and WWL4 are arranged.

However, the read / write bit lines BL1, BL2, BL3, BL4 and the write word lines WWL1, WWL2, WWL3, WWL4 for the TMR element are used.
The positional relationship of is not limited to this.

For example, as shown in FIGS. 113 and 114, a read / write bit line BL1, BL2, BL3 extending in the Y direction is provided below the TMR element.
BL4 may be arranged, and write word lines WWL1, WWL2, WWL3, WWL4 extending in the X direction may be arranged above the BL4.

As shown in FIGS. 115 and 116, regarding the write word line, a plurality of TMR elements (in the upper stage) are taken into consideration in consideration of flattening of the insulating film immediately below the TMR element 12 and reduction in manufacturing cost. TMR element and lower TM
One write word line may be shared by R elements.

According to such a device structure, the plurality of TMR elements MTJ1, MTJ2 in the read block are
MTJ3 and MTJ4 are connected to different read / write bit lines BL1, BL2, BL3 and BL4, respectively. Therefore, a plurality of TMR elements MTJ1, MTJ2 in the read block are read by one read step.
The data of MTJ3 and MTJ4 can be read at one time.

In addition, a plurality of TMRs in the read block
The elements MTJ1, MTJ2, MTJ3, MTJ4 are stacked in a plurality of stages on the semiconductor substrate 41, and the wirings extending in the Y direction are read / write bit lines BL1, B.
Only L2, BL3 and BL4. Therefore, even if the number of stacked stages of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 is increased, the cell array structure does not become complicated.

(5) Structural Examples 5, 6, 7, 8   Structure example 5 Structural example 5 is a modification of structural examples 1, 2, 3, and 4.

23, 24, and 25 show a fifth structural example. The circuit diagram of FIG. 23 corresponds to the circuit diagram of FIG. 1 or FIG. 13, and the sectional view of the device structure of FIG.
Corresponding to the sectional views of the device structure of FIGS. 4, 11, 17, and 21, and the sectional view of the device structure of FIG.
It corresponds to the cross-sectional view of the device structure of FIGS. 12, 18 and 22.

The structural example 5 is different from the structural examples 1, 2, 3, and 4 in the element that realizes the read selection switch.

That is, in the structural examples 1, 2, 3, and 4, the read selection switch is composed of MOS transistors. On the other hand, in Structural Example 5, the read selection switch is composed of the diode DI.

The anode of the diode DI is the TMR elements MTJ1, MTJ2, M in the read block BKik.
The cathode of the diode DI is connected to one end of the TJ3 and MTJ4, and the read word line RWLn (n = 1, 2,
...) is connected.

When the structure of this example is adopted, the read word line RWLn of the selected row is set to "L", that is, the ground potential during the read operation. As a result, the TMR elements MTJ1, which form the selected row block,
A read current can be passed through MTJ2, MTJ3, and MTJ4.

With regard to the device structure of Structural Example 5, the element formed in the surface region of the semiconductor substrate 41 is the diode D.
Except for point I, the structural examples 1, 2, 3, 4
Can be considered the same as.

Structural Example 6 Structural example 6 is also a modification of structural examples 1, 2, 3, and 4.

26, 27 and 28 show a sixth structural example. The circuit diagram of FIG. 26 corresponds to the circuit diagram of FIG. 1 or FIG. 13, and the sectional view of the device structure of FIG.
Corresponding to the sectional views of the device structure of FIGS. 4, 11, 17, and 21, and the sectional view of the device structure of FIG. 28 is shown in FIG.
It corresponds to the cross-sectional view of the device structure of FIGS. 12, 18 and 22.

The structure example 6 is different from the structure examples 1, 2, 3, and 4 in that it is an element for realizing the read selection switch. Specifically, in Structural Example 6, the direction of the diode DI in Structural Example 5 is changed.

That is, in the structure example 6, the cathode of the diode DI is the TMR element M in the read block BKik.
It is connected to one end of TJ1, MTJ2, MTJ3, MTJ4, and the anode of the diode DI is the read word line R.
It is connected to WLn (n = 1, 2, ...).

When the structure of this example is adopted, the read word line RWLn of the selected row is set to "H" during the read operation. As a result, the TMR elements MTJ1, MTJ2, MTJ that form the selected row block
3, a read current can be passed through MTJ4.

In the structure example 5, the read current flows from the read circuit 29B to the diode DI via the TMR element, but in the structure example 6, the read current flows from the diode DI to the TMR element. In the structural examples 1, 2, 3, and 4 that flow toward the read circuit 29B,
In particular, the direction of the read current was not explained. This is because, in these structural examples, whether the read current flows in the direction emitted by the read circuit 29B or in the direction absorbed by the read circuit 29B,
Either is fine.

Structural Example 7 Structural example 7 is a modification of structural examples 1 and 2.

29 and 30 show a seventh structural example. The circuit diagram of FIG. 29 corresponds to the circuit diagram of FIG.
The sectional view of the device structure of FIG. 30 corresponds to the sectional view of the device structure of FIGS. 4 and 11.

The structure example 7 is different from the structure examples 1 and 2 in that the read selection switch is realized.

That is, in the structural examples 1 and 2, the read selection switch is composed of the MOS transistor. On the other hand, in Structural Example 7, the read selection switch is composed of the bipolar transistor BT.

In Structural Example 7, the bipolar transistor B
The collector of T is the TMR in the read block BKik.
The emitter of the bipolar transistor BT is connected to one end of the elements MTJ1, MTJ2, MTJ3, MTJ4, and
It is connected to the source line SLi (i = 1, 2, ... J). The base of the bipolar transistor BT is connected to the read word line RWLn (n = 1, 2, ...).

When the structure of this example is adopted, the read word line RWLn of the selected row is set to "H" during the read operation. As a result, the TMR elements MTJ1, MTJ2, MTJ that form the selected row block
3, a read current can be passed through MTJ4.

Regarding the device structure of Structural Example 7, it is considered to be substantially the same as Structural Examples 1 and 2 except that the element formed in the surface region of the semiconductor substrate 41 is the bipolar transistor BT. Good.

In the case of the structure of this example, the memory cell array 11
Also, all of the transistors forming the peripheral circuit may be bipolar transistors, or some of them may be bipolar transistors.

Structural Example 8 Structural Example 8 is a modification of Structural Examples 3 and 4.

31 and 32 show a structural example 8. The circuit diagram of FIG. 31 corresponds to the circuit diagram of FIG. 13, and cross-sectional views of the device structure of FIG. 32 are shown in FIGS.
1 corresponds to a cross-sectional view of the device structure.

The structure example 8 is different from the structure examples 3 and 4 in that the element realizing the read selection switch is characterized.

That is, in the structure examples 3 and 4, the read selection switch is composed of the MOS transistor. On the other hand, in Structural Example 8, the read selection switch is composed of the bipolar transistor BT.

In Structural Example 8, the bipolar transistor B
The collector of T is the TMR in the read block BKik.
The emitter of the bipolar transistor BT is connected to one end of the elements MTJ1, MTJ2, MTJ3, MTJ4, and
It is connected to the read word line RWLn (n = 1, 2, ...). The base of the bipolar transistor BT is connected to the decode line DLi (i = 1, 2, ... J).

When the structure of this example is adopted, the read word line RWLn of the selected row is set to "L" during the read operation. As a result, the TMR elements MTJ1, MTJ2, MTJ that form the selected row block
3, a read current can be passed through MTJ4.

The device structure of Structural Example 8 is considered to be substantially the same as that of Structural Examples 3 and 4 except that the element formed in the surface region of the semiconductor substrate 41 is the bipolar transistor BT. Good.

In the case of the structure of this example, the memory cell array 11
Also, all of the transistors forming the peripheral circuit may be bipolar transistors, or some of them may be bipolar transistors.

(6) In the other structural examples 1 to 8, the read bit line and the write bit line are combined into one and used as the read / write bit line. However, the present invention is based on the TMR in the read block. The structure is not limited to this as long as the elements are connected to different read bit lines.

For example, in the structural examples 1 to 8, the read bit line and the write bit line may be individually provided, or the write word line may be used as the read word line.

3. Write / Read Operation Principle The write / read operation principle of the magnetic random access memory of the present invention will be briefly described. (1) Write Operation Principle Writing to the TMR element is performed randomly.
For example, one row is selected by the row address signal, and one column is selected by the upper column address signal. Further, one of the plurality of TMR elements in the read block in the selected row is selected by the lower column address signal.

To write data to the selected TMR element, a write current is passed through the write word line arranged immediately below the selected TMR element. In addition, a write current is passed through the read / write bit line arranged on the selected TMR element. The direction of the write current flowing through the read / write bit line is determined according to the write data.

The direction of magnetization of the free layer (storage layer) of the selected TMR element is determined by the combined magnetic field generated by the write current flowing in the write word line and the write current flowing in the read / write bit line, and "1" / "0" information is stored.

(2) Reading Operation Principle Reading from the TMR element is performed in reading block units. For example, one row is selected by the row address signal, and one column is selected by the upper column address signal.

In order to read the data of the plurality of TMR elements in the selected read block existing in the selected row and column, a read current is passed through the plurality of read / write bit lines arranged in the selected column. .
The direction of the read current supplied to the read / write bit line is not particularly limited.

At this time, it is preferable that the plurality of read / write bit lines arranged in the selected column are electrically connected only to the selected read block (for example, the circuit example of FIG. 3). .

The potentials of the plurality of read / write bit lines have values corresponding to the data of the plurality of TMR elements in the read block. This potential is sensed by the sense amplifier.

Multiple T's in the selected read block
The data of the MR element is sensed by a sense amplifier and then output to the outside of the magnetic random access memory.
Here, the data of the plurality of TMR elements is 1 bit at a time,
It may be output, or may be output at the same time.

When the data of the plurality of TMR elements is sequentially output bit by bit, for example, one of the data of the plurality of TMR elements is selected using the lower column address signal.

4. Circuit Example of Peripheral Circuit Below is a circuit example of the write word line driver / sinker,
A circuit example of a write bit line driver / sinker, a circuit example of a read word line driver, a circuit example of a column decoder, and a circuit example of a read circuit (including a sense amplifier) will be sequentially described.

(1) Write Word Line Driver / Sinker FIG. 33 shows a circuit example of the write word line driver / sinker. In this example, it is assumed that the read block is composed of four TMR elements stacked in four stages, and the four TMR elements in the read block are selected by the lower 2 bits CA0 and CA1 of the column address signal. . In the figure, write word line driver /
Only one row of sinker is shown.

The write word line driver 23A-1 is
P-channel MOS transistors QP1, QP2, QP
3, QP4 and NAND gate circuits ND1, ND2, N
D3 and ND4 are included. The write word line sinker 24-1 includes N channel MOS transistors QN1 and QN.
It is composed of N2, QN3 and QN4.

The P channel MOS transistor QP1 is
It is connected between the power supply terminal VDD and one end of the write word line WWL1 in the lowermost stage (first stage). The output signal of the NAND gate circuit ND1 is supplied to the gate of the P-channel MOS transistor QP1. The N-channel MOS transistor QN1 is connected between the other end of the lowermost write word line WWL1 and the ground terminal VSS.

When the output signal of the NAND gate circuit ND1 is "0", the write current flows in the write word line WWL1.

P-channel MOS transistor QP2 is
It is connected between the power supply terminal VDD and one end of the second-stage write word line WWL2. The output signal of the NAND gate circuit ND2 is supplied to the gate of the P-channel MOS transistor QP2. N-channel MOS transistor QN
2 is connected between the other end of the write word line WWL2 in the second stage and the ground terminal VSS.

When the output signal of the NAND gate circuit ND2 is "0", the write current flows through the write word line WWL2.

The P-channel MOS transistor QP3 is
It is connected between the power supply terminal VDD and one end of the third-stage write word line WWL3. The output signal of the NAND gate circuit ND3 is supplied to the gate of the P-channel MOS transistor QP3. N-channel MOS transistor QN
3 is connected between the other end of the third-stage write word line WWL3 and the ground terminal VSS.

When the output signal of the NAND gate circuit ND3 is "0", the write current flows through the write word line WWL3.

The P-channel MOS transistor QP4 is
It is connected between the power supply terminal VDD and one end of the uppermost (fourth) write word line WWL4. The output signal of the NAND gate circuit ND4 is supplied to the gate of the P-channel MOS transistor QP4. The N-channel MOS transistor QN4 is connected between the other end of the uppermost write word line WWL4 and the ground terminal VSS.

When the output signal of the NAND gate circuit ND4 is "0", the write current flows in the write word line WWL4.

Write word lines WWL1, WW2, WW
Since L3 and WWL4 belong to the same row, NAN
The same row address signal is input to the D gate circuits NA1, NA2, NA3, and NA4. In the selected row, all the bits of the row address signal are "H".

NAND gate circuits NA1 and NA
A write signal is input to 2, NA3 and NA4.
The write signal becomes "H" during the write operation. Further, NAND gate circuits NA1, NA2, NA3, NA
Different lower column address signals are input to 4, respectively.

That is, in this example, the column address signal bC
A0 and bCA1 are used to select the write word line WWL1 at the bottom (first stage), and the NAND circuit N
Input to D1.

Similarly, the column address signals CA0, bC
A1 is input to the NAND circuit ND2 to select the write word line WWL1 in the second stage, and the column address signals bCA0 and CA1 are written word line W in the third stage.
The column address signals CA0 and CA1 are input to the NAND circuit ND3 to select WL3, and the column address signals CA0 and CA1
N to select the write word line WWL4 of the
It is input to the AND circuit ND4.

Note that bCA0 and bCA1 are inversion signals having the levels obtained by inverting the levels of CA0 and CA1.

In such a write word line driver / sinker, the write signal WR is generated during the write operation.
ITE becomes "1", and, for example, the output signal of one of the four NAND gate circuits ND1, ND2, ND3, ND4 becomes "L".

For example, when both CA0 and CA1 are "0", the input signals of the NAND gate circuit ND1 are all "1" and the output signal of the NAND gate circuit ND1 is "0". As a result, the P-channel MOS transistor QP1 is turned on and the write word line WWL1
Write current flows to.

When CA0 is "1" and CA1 is "0", all the input signals of the NAND gate circuit ND2 are "1" and the output signal of the NAND gate circuit ND2 is "0". As a result, the P-channel MOS transistor QP2 is turned on, and the write word line WWL2
Write current flows to.

When CA0 is "0" and CA1 is "1", the input signals of the NAND gate circuit ND3 are all "1" and the output signal of the NAND gate circuit ND3 is "0". As a result, the P-channel MOS transistor QP3 is turned on, and the write word line WWL3
Write current flows to.

When both CA0 and CA1 are "1", all the input signals of the NAND gate circuit ND4 are "1".
And the output signal of the NAND gate circuit ND4 is "0".
Becomes As a result, the P-channel MOS transistor QP
4 is turned on, and a write current flows through the write word line WWL4.

(2) Write Bit Line Driver / Sinker FIGS. 34 and 35 show an example of the circuit of the write bit line driver / sinker. In this example, it is assumed that the read block is composed of four TMR elements stacked in four stages, and the four TMR elements in the read block are selected by the lower 2 bits CA0 and CA1 of the column address signal. . Further, the column of the memory cell array is selected by the upper column address signal, that is, the column address signal excluding the lower 2 bits CA0 and CA1 of the column address signal.

In the figure, only one column of the write bit line driver / sinker is shown.

Write bit line driver / sinker 29
A is a P-channel MOS transistor QP5, QP6,
QP7, QP8, N-channel MOS transistor QN
5, QN6, QN7, QN8, NAND gate circuit ND
5, ND6, ND7, ND8, AND gate circuit AD
1, AD2, AD3, AD4 and inverter INV1,
It is composed of INV2, INV3 and INV4.

P-channel MOS transistor QP5 is
It is connected between the power supply terminal VDD and one end of the write bit line BL1 at the lowest stage (first stage). The output signal of the NAND gate circuit ND5 is the P-channel MOS transistor Q.
It is supplied to the gate of P5. The N-channel MOS transistor QN5 is connected between one end of the lowermost write bit line BL1 and the ground terminal VSS. The output signal of the AND gate circuit AD1 is an N-channel MOS transistor Q.
It is supplied to the gate of N5.

P-channel MOS transistor QP6 is
It is connected between the power supply terminal VDD and one end of the write bit line BL2 of the second stage. The output signal of the NAND gate circuit ND6 is supplied to the gate of the P-channel MOS transistor QP6. N-channel MOS transistor QN6
Is connected between one end of the second-stage write bit line BL2 and the ground terminal VSS. The output signal of the AND gate circuit AD2 is supplied to the gate of the N-channel MOS transistor QN6.

The P-channel MOS transistor QP7 is
It is connected between the power supply terminal VDD and one end of the third-stage write bit line BL3. The output signal of the NAND gate circuit ND7 is supplied to the gate of the P-channel MOS transistor QP7. N-channel MOS transistor QN7
Is connected between one end of the third-stage write bit line BL3 and the ground terminal VSS. The output signal of the AND gate circuit AD3 is supplied to the gate of the N-channel MOS transistor QN7.

P-channel MOS transistor QP8 is
It is connected between the power supply terminal VDD and one end of the uppermost (fourth) write bit line BL4. The output signal of the NAND gate circuit ND8 is the P-channel MOS transistor Q.
It is supplied to the gate of P8. The N-channel MOS transistor QN8 is connected between one end of the uppermost write bit line BL4 and the ground terminal VSS. The output signal of the AND gate circuit AD4 is an N-channel MOS transistor Q.
It is supplied to the gate of N8.

Write bit line driver / sinker 31
Are P-channel MOS transistors QP9, QP10,
QP11, QP12, N-channel MOS transistor Q
N9, QN10, QN11, QN12, NAND gate circuits ND9, ND10, ND11, ND12, AND gate circuits AD5, AD6, AD7, AD8 and inverters INV5, INV6, INV7, INV8.

The P-channel MOS transistor QP9 is
It is connected between the power supply terminal VDD and the other end of the write bit line BL1 in the lowermost stage (first stage). The output signal of the NAND gate circuit ND9 is the P-channel MOS transistor Q.
It is supplied to the gate of P9. The N-channel MOS transistor QN9 is connected between the other end of the lowermost write bit line BL1 and the ground terminal VSS. The output signal of the AND gate circuit AD5 is an N-channel MOS transistor Q.
It is supplied to the gate of N9.

P-channel MOS transistor QP10
Is the power supply terminal VDD and the second-stage write bit line BL2
Is connected to the other end of. NAND gate circuit ND1
The output signal of 0 is the P-channel MOS transistor QP1.
It is supplied to the 0 gate. The N-channel MOS transistor QN10 is connected between the other end of the second-stage write bit line BL2 and the ground terminal VSS. The output signal of the AND gate circuit AD6 is an N-channel MOS transistor Q.
It is supplied to the gate of N10.

P-channel MOS transistor QP11
Is the power supply terminal VDD and the third-stage write bit line BL3
Is connected to the other end of. NAND gate circuit ND1
The output signal of 1 is the P-channel MOS transistor QP1.
1 is supplied to the gate. The N-channel MOS transistor QN11 is connected between the other end of the third-stage write bit line BL3 and the ground terminal VSS. The output signal of the AND gate circuit AD7 is the N-channel MOS transistor Q.
It is supplied to the gate of N11.

P-channel MOS transistor QP12
Is connected between the power supply terminal VDD and the other end of the uppermost (fourth) write bit line BL4. The output signal of the NAND gate circuit ND12 is supplied to the gate of the P-channel MOS transistor QP12. N channel MOS
The transistor QN12 is the uppermost write bit line B
It is connected between the other end of L4 and the ground terminal VSS. AND
The output signal of the gate circuit AD8 is supplied to the gate of the N-channel MOS transistor QN12.

In the write bit line drivers / sinkers 29A and 31 having such a configuration, when the output signal of the NAND gate circuit ND5 is "0" and the output signal of the AND gate circuit AD5 is "1", the write bit line B is
Write bit line driver / sinker 29A for L1
A write current flows from the write bit line driver / sinker 31 to the write bit line driver / sinker 31.

When the output signal of the NAND gate circuit ND9 is "0" and the output signal of the AND gate circuit AD1 is "1", the write bit line BL1 includes the write bit line driver / sinker 31 to the write bit line driver. / A write current flows to the sinker 29A.

When the output signal of the NAND gate circuit ND6 is "0" and the output signal of the AND gate circuit AD6 is "1", the write bit line BL2 includes the write bit line driver / sinker 29A to the write bit line driver. / Write current flows toward the sinker 31.

When the output signal of the NAND gate circuit ND10 is "0" and the output signal of the AND gate circuit AD2 is "1", the write bit line BL2 includes the write bit line driver / sinker 31 to the write bit line driver. / A write current flows to the sinker 29A.

When the output signal of the NAND gate circuit ND7 is "0" and the output signal of the AND gate circuit AD7 is "1", the write bit line BL3 is connected to the write bit line driver / sinker 29A. / Write current flows toward the sinker 31.

When the output signal of the NAND gate circuit ND11 is "0" and the output signal of the AND gate circuit AD3 is "1", the write bit line BL3 is connected to the write bit line driver / sinker 31 to the write bit line driver. / A write current flows to the sinker 29A.

Further, when the output signal of the NAND gate circuit ND8 is "0" and the output signal of the AND gate circuit AD8 is "1", the write bit line BL4 is connected to the write bit line driver / sinker 29A to the write bit line driver. / Write current flows toward the sinker 31.

When the output signal of the NAND gate circuit ND12 is "0" and the output signal of the AND gate circuit AD4 is "1", the write bit line BL4 includes the write bit line driver / sinker 31 to the write bit line driver. / A write current flows to the sinker 29A.

Write bit line driver / sinker 29
In A and 31, in the write operation, the write signal W
RITE becomes “1”. Further, in the selected column, all the bits of the upper column address signal, that is, all the bits of the column address signal except the lower two bits CA0 and CA1 of the column address signal become "1".

Lower column address signals CA0, CA1
Is the four write bit lines BL in the selected column.
This is a signal for selecting one of 1, BL2, BL3 and BL4. A write current having a direction corresponding to the value of the write data DATA flows through the selected bit line.

The direction of the write current flowing through the selected write bit line in the selected column is determined according to the value of write data DATA.

For example, when the write bit line BL1 is selected (when CA0 = "0" and CA1 = "0"), when the write data DATA is "1", NA is set.
The output signal of the ND gate circuit ND5 becomes "0", and AN
The output signal of the D gate circuit AD5 becomes "1". As a result, a write current flows from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 in the write bit line BL1.

On the contrary, when the write data DATA is "0", the output signal of the NAND gate circuit ND9 is "0".
And the output signal of the AND gate circuit AD1 becomes "1". As a result, a write current flows from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A in the write bit line BL1.

When the write bit line BL2 is selected (when CA0 = "1" and CA1 = "0"), when the write data DATA is "1", NA is set.
The output signal of the ND gate circuit ND6 becomes "0", and AN
The output signal of the D gate circuit AD6 becomes "1". As a result, a write current flows from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 in the write bit line BL2.

On the contrary, when the write data DATA is "0", the output signal of the NAND gate circuit ND10 becomes "0" and the output signal of the AND gate circuit AD2 becomes "1". As a result, a write current flows from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A in the write bit line BL2.

When the write bit line BL3 is selected (when CA0 = "0" and CA1 = "1"), when the write data DATA is "1", NA is set.
The output signal of the ND gate circuit ND7 becomes "0", and AN
The output signal of the D gate circuit AD7 becomes "1". As a result, a write current flows from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 in the write bit line BL3.

On the contrary, when the write data DATA is "0", the output signal of the NAND gate circuit ND11 becomes "0" and the output signal of the AND gate circuit AD3 becomes "1". As a result, a write current flows from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A in the write bit line BL3.

When the write bit line BL4 is selected (when CA0 = "1" and CA1 = "1"), when the write data DATA is "1", NA is set.
The output signal of the ND gate circuit ND8 becomes "0", and AN
The output signal of the D gate circuit AD8 becomes "1". As a result, a write current flows from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 in the write bit line BL4.

On the contrary, when the write data DATA is "0", the output signal of the NAND gate circuit ND12 becomes "0" and the output signal of the AND gate circuit AD4 becomes "1". As a result, a write current flows from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A in the write bit line BL4.

(3) Read Word Line Driver FIGS. 36 and 37 show a circuit example of the read word line driver. The read word line driver is applied to the structural examples 1, 2, 6, 7 and the structural examples 3, 4, 5, 8
The circuit structure is different when applied to.

FIG. 36 shows an example of a read word line driver applied to Structural Examples 1, 2, 6, and 7. The read word line driver 23B-1 is composed of an AND gate circuit AD9. The read signal READ and the row address signal are input to the AND gate circuit AD9.

The read signal is
This signal is "1". The row address signal is the same as the row address signal in the write word line driver / sinker (FIG. 33).

In the read operation, in the selected row, all the bits of the row address signal are "1", so that the potential of the read word line RWL1 is "1".

FIG. 37 shows an example of a read word line driver applied to Structural Examples 3, 4, 5, and 8. The read word line driver 23B-1 is composed of a NAND gate circuit ND13. NAND gate circuit ND
A read signal READ and a row address signal are input to 13.

The read signal is
This signal is "1". The row address signal is the same as the row address signal in the write word line driver / sinker (FIG. 33).

In the read operation, in the selected row, all the bits of the row address signal are "1", so that the potential of the read word line RWL1 is "0".

(4) Column Decoder FIGS. 38 and 39 show examples of column decoder circuits. The column decoders 32, 32A and 32B are ANDed
It is composed of a gate circuit AD10. The read signal READ and the upper column address signal are input to the AND gate circuit AD10. The read signal is a signal that becomes “1” during the read operation. In addition, in the selected column, all bits of the upper column address signal are
It becomes "1".

Therefore, the column decoders 32 and 32A are
The potential of the column selection signal CSLj that is the output signal thereof is set to "1", and the column decoder 32B sets the potential of the decode signal DL1 that is the output signal thereof to "1".

(5) Read Circuit FIG. 40 shows a circuit example of the read circuit. In this example, in one column, in the read block, 4
It is premised that two TMR elements are arranged and that each TMR element is independently connected to the read bit line. That is, four read bit lines are arranged in one column, and these read bit lines are connected to the read circuit 29B via the column selection switch.

The read circuit 29B of this example is applied to a 1-bit type magnetic random access memory which outputs read data bit by bit.

Therefore, the read circuit 29B has four sense amplifier & bias circuits 29B11, 29B12, 2
9B13 and 29B14, a selector 29B2, and an output buffer 29B3.

In the read operation, read data is simultaneously read from the four TMR elements of the selected read block. These four read data are the sense amplifier & bias circuits 29B11, 29B12, 29B1.
3, 29B14 is input and sensed.

Selector 29B2 sense amplifier & bias circuits 29B11, 29B12, 29B1 based on the lower 2 bits CA0, CA1 of the column address signal.
One of the four read data output from 3, 29B14 is selected. The selected read data is
The data is output from the magnetic random access memory as output data via the output buffer 29B3.

By the way, in this example, the read circuit 29B is used.
Was applied to a 1-bit type magnetic random access memory.

However, for example, the read circuit 29B is
When applied to a 4-bit type magnetic random access memory that outputs read data in units of 4 bits, the selector 29B2 becomes unnecessary. On the other hand, the output buffer 29
For B3, the sense amplifier & bias circuit 29B1
Four are required corresponding to 1, 29B12, 29B13, 29B14.

FIG. 41 shows a circuit example of a read circuit applied to a 4-bit type magnetic random access memory. The read circuit 29B has four sense amplifiers &
Bias circuits 29B11, 29B12, 29B13, 2
9B14 and four output buffers 29B31 and 29B3
2, 29B33, 29B34.

In the read operation, read data is read out simultaneously from the four TMR elements of the selected read block. These four read data are the sense amplifier & bias circuits 29B11, 29B12, 29B1.
3, 29B14 is input and sensed.

Then, the sense amplifier & bias circuit 29
The output data of B11, 29B12, 29B13, 29B14 are output buffers 29B31, 29B32, 29B.
The data is output from the magnetic random access memory via 33, 29B34.

FIG. 42 shows a circuit example of the sense amplifier & bias circuit. This sense amplifier & bias circuit corresponds to one of the four sense amplifier & bias circuits of FIGS. 40 and 41.

The sense amplifier S / A is composed of, for example, a differential amplifier.

Power supply terminal VDD and column selection switch 29
Between C and P channel MOS transistor QP14
And N channel MOS transistor QN13 are connected in series. The negative input terminal of the operational amplifier OP is connected to the node n2, and its output terminal is an N-channel MO.
It is connected to the gate of the S-transistor QN13, and the clamp potential VC is input to its positive input terminal.

The operational amplifier OP plays a role of making the potential of the node n2 equal to the clamp potential VC. The value of the clamp potential VC is set to a predetermined positive value.

The constant current source Is has a read current Iread.
To generate. The read current Iread is P channel M
The current flows to the bit line BLi via the current mirror circuit including the OS transistors QP13 and QP14. For example, the sense amplifier including a differential amplifier senses the data in the memory cell (TMR element) based on the potential of the node n1 when the read current Iread is flowing.

FIG. 43 shows a circuit example of the sense amplifier. FIG. 44 shows a circuit example of the reference potential generation circuit of the sense amplifier. The sense amplifier S / A is composed of, for example, a differential amplifier. Sense amplifier S / A
Is the potential Vn1 of the node n1 and the reference potential Vre
Compare with f.

The reference potential Vref is a TMR element for storing "1" data and a TM for storing "0" data.
It is generated from the R element.

Between the power supply terminal VDD and the TMR element which stores "1" data, a P-channel MOS transistor QP16 and an N-channel MOS transistor QN14,
QN15 is connected in series. In addition, a P-channel MOS transistor QP17 and an N-channel MOS transistor are provided between the power supply terminal VDD and the TMR element which stores “0” data.
Transistors QN16 and QN17 are connected in series.

P-channel MOS transistor QP16,
The drains of QP17 are connected to each other, and the drains of N-channel MOS transistors QN15 and QN17 are also connected to each other.

The operational amplifier OP plays a role of making the potential of the node n4 equal to the clamp potential VC. Constant current source I
S2 generates the read current Iread. The read current Iread is the P-channel MOS transistor QP.
The current flows through the TMR element storing "1" data and the TMR element storing "0" data via the current mirror circuit composed of 15 and QP16.

Reference potential Vref is the same as node n3.
Is output from.

Here, Is1 = Is2 and the transistor Q
P13, QP14, QP15, QP16, QP17 have the same size, and transistors QN13, QN14, QN16
Have the same size, and transistors QN15 and QN1
7 and CSL1, CSL2, ... If the same size N-channel MOS transistors are input, Vre
f can be set to an intermediate value between the potential of Vn1 when outputting "1" data and the potential of Vn1 when outputting "0" data.

FIG. 45 shows a circuit example of the operational amplifier OP shown in FIGS. 42 and 44. The operational amplifier OP includes P-channel MOS transistors QP18, QP19 and N-channel MOS transistors QN18, QN19, QN20.
Composed of. Enable signal Enable is "H"
Then, the operational amplifier OP is activated.

5. Manufacturing Method The cell array structure, read operation principle, and read circuit of the magnetic random access memory of the present invention are as described above. Therefore, finally, a manufacturing method for realizing the magnetic random access memory of the present invention will be described.

The manufacturing method described below relates to Structural Example 1. However, the structural examples 2 to 8 can be easily formed by using the following manufacturing method.

That is, the structure example 2 is different from the structure example 1 only in the direction of the read selection switch, and
This is because the structural examples 3 and 4 differ from the structural example 1 only in the type (purpose) of the wiring connected to the read selection switch. Further, the structural examples 5 to 8 are different from the structural example 1 in that
Only the elements forming the read selection switch are different.

(1) Target Cell Array Structure First, a cell array structure completed by the manufacturing method of the present invention will be briefly described. Then, a method of manufacturing the cell array structure will be described.

FIG. 46 shows a cell array structure relating to Structural Example 1. In this cell array structure, four vertically stacked TMR elements MTJ1, MTJ2, MTJ3, M
One read block is configured by TJ4.

In the surface area of the semiconductor substrate 51, a read selection switch (MOS transistor) RSW is arranged. The read selection switches RSW in the two read blocks adjacent in the column direction share one source with each other. The source of the read selection switch RSW is connected to the source line SL. The source line SL extends in a straight line in the Y direction, for example, and is commonly connected to the read selection switches RSW of the plurality of read blocks arranged in one column.

The gate of the read selection switch (MOS transistor) RSW has read word lines RWL1 and RWL.
WL2 and RWL3. Read word line RW
L1, RWL2 and RWL3 extend in the X direction. Four Ts are provided on each read selection switch RSW.
The MR elements MTJ1, MTJ2, MTJ3, MTJ4 are stacked.

TMR elements MTJ1, MTJ2, MTJ
3, MTJ4 has a structure as shown in FIG. 7, FIG. 8 or FIG. 9, for example. TMR element MTJ1, MTJ2, M
The vertical orientations of TJ3 and MTJ4 are set, for example, so that the free layer (storage layer) is at an equal distance from the write word line and the read / write bit line as much as possible, and the easy axis thereof is parallel to the X direction, for example. And set.

TMR elements MTJ1, MTJ2, MTJ
3, the lower surface of MTJ4 is connected to the lower electrode. The lower electrode is connected to the drain of the read selection switch (MOS transistor) RSW by the contact plug.

TMR elements MTJ1, MTJ2, MTJ
Immediately below 3, MTJ4, write word lines WWL1, WWL2, WWL3, WWL4 extending in the X direction are arranged. TMR elements MTJ1, MTJ2, MTJ3, MT
The upper surface of J4 is in contact with the read / write bit lines BL1, BL2, BL3, BL4 extending in the Y direction.

When the cell array structure is viewed from above the semiconductor substrate 51, for example, the TMR elements MTJ1 and MTJ are
2, MTJ3, MTJ4 are laid out so as to overlap each other. In addition, the write word line WW
The L1, WWL2, WWL3 and WWL4 are also laid out so as to overlap each other. Furthermore, read / write bit lines BL1, BL2, BL
3 and BL4 are also laid out so as to overlap each other.

TMR elements MTJ1, MTJ2, MTJ
3, contact plugs for connecting one end of MTJ4 to the drain of the read selection switch RSW include write word lines WWL1, WWL2, WWL3, WWL4 and read / write bit lines BL1, BL2, BL3, B.
The layout is such that it does not overlap L4.

(2) Each Step of Manufacturing Method Hereinafter, a manufacturing method for realizing the cell array structure of FIG. 46 will be described. It should be noted that since the embodied manufacturing method (for example, the adoption of the dual damascene process) will be described here, the elements not included in the cell array structure of FIG. 46 will also be described. However, the outline of the finally completed cell array structure is almost the same as the cell array structure of FIG.

[1] Element Separation Step First, as shown in FIG.
An element isolation insulating layer 52 having an I (Shallow Trench Isolation) structure is formed.

The element isolation insulating layer 52 can be formed by the following process, for example.

[0409] A mask pattern (silicon nitride or the like) is formed on the semiconductor substrate 51 by PEP (Photo Engraving Process). Using this mask pattern as a mask, the semiconductor substrate 51 is etched by RIE (Reactive Ion Etching) to form a trench in the semiconductor substrate 51. For example, CVD (Chemical Vapor Depositio)
By using the n) method and the CMP (Chemical Mechanical Polishing) method, the trench is filled with an insulating layer (silicon oxide or the like).

Thereafter, if necessary, a P-type impurity (B, BF ₂ or the like) or an N-type impurity (P, As or the like) is injected into the semiconductor substrate by, for example, an ion implantation method to form a P-type well region. Alternatively, an N-type well region is formed.

[2] Step of Forming MOSFET Next, as shown in FIG. 48, a MOS transistor functioning as a read selection switch is formed in the surface region of the semiconductor substrate 51.

The MOS transistor can be formed by the following process, for example.

Impurities for controlling the threshold value of the MOS transistor are ion-implanted into the channel portion in the element region surrounded by the element isolation insulating layer 52. By the thermal oxidation method,
A gate insulating film (silicon oxide or the like) 53 is formed in the element region. A gate electrode material (such as polysilicon containing impurities) and a cap insulating film (such as silicon nitride) 55 are formed over the gate insulating film 53 by a CVD method.

After the cap insulating film 55 is patterned by PEP, the gate insulating material and the gate insulating film 5 are formed by RIE using the cap insulating film 55 as a mask.
3 is processed (etched). As a result, the semiconductor substrate 5
A gate electrode 54 extending in the X direction is formed on the first electrode 1.

Using the cap insulating film 55 and the gate electrode 54 as a mask, the semiconductor substrate 51 is formed by ion implantation.
A P-type impurity or an N-type impurity is implanted therein. And
A low-concentration impurity region (LDD region or extension region) is formed in the semiconductor substrate.

After forming an insulating film (such as silicon nitride) on the entire surface of the semiconductor substrate 51 by the CVD method, RIE is performed.
Thus, the insulating film is etched, and the sidewall insulating layer 57 is formed on the sidewalls of the gate electrode 54 and the cap insulating film 55. Cap insulating film 55, gate electrode 54
Then, using the sidewall insulating layer 57 as a mask, a P-type impurity or an N-type impurity is implanted into the semiconductor substrate 51 by an ion implantation method. As a result, the source region 56A and the drain region 56B are formed in the semiconductor substrate 51. After that, an interlayer insulating film (for example, silicon oxide) that completely covers the MOS transistor is entirely formed on the semiconductor substrate 51 by the CVD method. Etc.) 58 is formed. Also, CMP
By utilizing the technique, the surface of the interlayer insulating film 58 is flattened.

[3] Step of Forming Contact Hole Next, as shown in FIGS. 49 and 50, a semiconductor substrate 51 is formed.
A contact hole 59 reaching the source region 56A and the drain region 56B of the MOS transistor is formed in the upper interlayer insulating film 58.

The contact hole 59 is, for example, PEP.
Thus, a resist pattern can be easily formed by forming a resist pattern on the interlayer insulating film 58 and using the resist pattern as a mask to etch the interlayer insulating film 58 by RIE. After this etching, the resist pattern is removed.

[4] Wiring Groove Forming Step Next, as shown in FIG. 51, a wiring groove 60 is formed in the interlayer insulating film 58 on the semiconductor substrate 51. In this example, the wiring groove 60 extends in the Y direction, but in the same cross section (cross section when the device is cut by a straight line extending in the Y direction),
The contact hole 59 on the source region 56A, the contact hole 59 on the drain region 56B, and the wiring groove 60 do not appear at the same time.

Therefore, in FIG. 51, the wiring groove 60 is shown by a broken line.

The wiring groove 60 can be easily formed by forming a resist pattern on the interlayer insulating film 58 by PEP and etching the interlayer insulating film 58 by RIE using this resist pattern as a mask. You can After this etching, the resist pattern is removed.

[5] Step of Forming First Wiring Layer Next, as shown in FIG. 52, on the interlayer insulating film 58, on the inner surface of the contact hole 59 and on the inner surface of the wiring groove 60, for example, by using a sputtering method. Then, a barrier metal layer (such as a stack of Ti and TiN) 61 is formed on each of them. continue,
For example, by sputtering, on the barrier metal layer 61,
A metal layer (W or the like) 62 that completely fills the contact hole 59 and the wiring groove 60 is formed.

Thereafter, as shown in FIG. 53, for example, C
Using the MP method, the metal layer 62 is polished to remove the metal layer 62.
It is left only in the contact hole 59 and the wiring groove 60.
The metal layer 62 remaining in the contact hole 59 becomes the contact plug 62A, and the metal layer 62 remaining in the wiring groove 60 is the first wiring layer (source line, decode line, etc.).
It becomes 62B. Further, the interlayer insulating film 58 is formed by the CVD method.
An interlayer insulating film (silicon oxide or the like) 63 is formed on top.

A step including a contact hole forming step, a wiring groove forming step, and a first wiring layer forming step is called a dual damascene process.

In fact, the contact plug 62A and the first wiring 62B do not appear at the same time in the same cross section (cross section when the device is cut by a straight line extending in the Y direction). However, in addition to the contact plug 62A, in FIG.
Actually, the first wiring 62B, which does not appear as a cross section, is also shown.

[6] Step of forming wiring groove Next, as shown in FIG. 54, a wiring groove 64 is formed in the interlayer insulating film 63. In this example, the wiring groove 64 is a groove for forming a write word line and extends in the X direction. When copper (Cu) is used as the wiring metal, a sidewall insulating layer (such as silicon nitride) 65 for preventing diffusion and oxidation of copper is formed on the side surface of the wiring groove 64.

The wiring trench 64 can be easily formed by forming a resist pattern on the interlayer insulating film 63 by PEP and etching the interlayer insulating film 63 by RIE using this resist pattern as a mask. You can After this etching, the resist pattern is removed.

The sidewall insulating layer 65 is easily formed by forming an insulating film (such as silicon nitride) on the entire surface of the interlayer insulating film 63 by the CVD method and then etching the insulating film by RIE. can do.

[7] Second Wiring Layer Forming Step Next, as shown in FIG. 55, for example, by sputtering, on the interlayer insulating film 63, on the inner surface of the wiring trench 64 and on the sidewall insulating layer 65. Then, a barrier metal layer (a stack of Ta and TaN, etc.) 66 is formed on each of them. continue,
For example, by sputtering, on the barrier metal layer 66,
A metal layer (Al, Cu, etc. C that completely fills the wiring groove 64. C
In the case of u, the electrolytic plating method is used instead of the sputtering method. ) 67 is formed.

Thereafter, as shown in FIG. 56, for example, C
Using the MP method, the metal layer 67 is polished to form the metal layer 67.
It is left only in the wiring groove 64. The metal layer 67 remaining in the wiring groove 64 becomes a second wiring layer that functions as a write word line.

An insulating layer (such as silicon nitride) 68 is formed on the interlayer insulating film 63 by the CVD method. Also,
The insulating layer 68 is polished by the CMP method to leave the insulating layer 68 on the metal layer 67 as the second wiring layer. An interlayer insulating film (such as silicon oxide) that completely covers the metal layer 67 as the second wiring layer is formed on the interlayer insulating film 63.
69 is formed.

The step including the step of forming the wiring groove and the step of forming the second wiring layer is called a damascene process.

[8] Step of Forming Lower Electrode of First MTJ Element Next, as shown in FIGS. 57 and 58, an interlayer insulating film 69 is formed.
Then, contact holes reaching the metal layers 62A and 62B as the first wiring layers are formed.

This contact hole is formed, for example, by PEP.
Thus, a resist pattern can be easily formed by forming a resist pattern on the interlayer insulating film 69 and using the resist pattern as a mask to etch the interlayer insulating films 63 and 69 by RIE. After this etching, the resist pattern is removed.

Also, for example, a barrier metal layer (Ti and TiN) is formed on the inner surface of the contact hole by using a sputtering method.
70) is formed. Subsequently, a metal layer (W or the like) 71 that completely fills the contact hole is formed on the barrier metal layer 70 by, for example, a sputtering method.

Thereafter, the metal layer 71 is polished by, for example, the CMP method, and the metal layer 71 is left only in the contact hole. Metal layer 71 remaining in the contact hole
Is a contact plug. Also, by the CVD method,
A metal layer (Ta or the like) 72 that will be a lower electrode of the first MTJ element is formed on the interlayer insulating film 69.

[9] Step of Forming First MTJ Element Next, as shown in FIGS. 59 and 60, the first MTJ element 73 is formed on the metal layer 72. First MTJ element 7
3 is composed mainly of a tunnel barrier and two ferromagnetic layers sandwiching the tunnel barrier, and has a structure as shown in FIG. 7, for example.

Further, the lower electrode 72 of the first MTJ element 73
Pattern.

The lower electrode 72 of the first MTJ element 73 is patterned by forming a resist pattern on the lower electrode 72 by PEP and then etching the lower electrode 72 by RIE using this resist pattern as a mask. Easy to do. Then, the resist pattern is removed.

After that, the interlayer insulating film 75 which completely covers the first MTJ element 73 is formed by the CVD method.

[10] Wiring Groove Forming Step Next, as shown in FIG. 61, a wiring groove 75 A is formed in the interlayer insulating film 75. In this example, the wiring groove 75A is a groove for forming a read / write bit line and extends in the Y direction. When copper (Cu) is used as the wiring metal, a sidewall insulating layer (such as silicon nitride) for preventing copper diffusion and oxidation is formed on the side surface of the wiring groove 75A.

The wiring groove 75A is formed by PEP, for example.
It can be easily formed by forming a resist pattern on the interlayer insulating film 75 and etching the interlayer insulating film 75 by RIE using the resist pattern as a mask. After this etching, the resist pattern is removed.

The sidewall insulating layer is easily formed by forming an insulating film (such as silicon nitride) on the entire surface of the interlayer insulating film 75 by the CVD method and then etching the insulating film by RIE. be able to.

[11] Step of Forming Third Wiring Layer Next, as shown in FIG. 62, the interlayer insulating film 75, the inner surface of the wiring trench 75A and the sidewall insulating layer are formed by, for example, a sputtering method. , The barrier metal layer (T
a) and a TaN laminated layer) are formed. Subsequently, for example, by sputtering, a metal layer (Al, Cu, etc. Cu completely filling the wiring groove 75A is formed on the barrier metal layer 76.
In this case, the electrolytic plating method is used instead of the sputtering method. ) 77 is formed.

Thereafter, as shown in FIG. 63, for example, C
Using the MP method, the metal layer 77 is polished to remove the metal layer 77.
It is left only in the wiring groove 75A. The metal layer 77 remaining in the wiring groove 75A becomes a third wiring layer that functions as a read / write bit line.

An insulating layer (silicon nitride or the like) 78 is formed on the interlayer insulating film 75 by the CVD method. Also,
The insulating layer 78 is polished by the CMP method to leave the insulating layer 78 on the metal layer 77 as the third wiring layer. An interlayer insulating film (such as silicon oxide) that completely covers the metal layer 77 as the third wiring layer is formed on the interlayer insulating film 75.
79 is formed.

[12] Step of Forming Wiring Trench Next, as shown in FIG. 64, a wiring trench 87 is formed in the interlayer insulating film 79. In this example, the wiring groove 87 is a groove for forming a write word line and extends in the X direction. When copper (Cu) is used as the wiring metal, a sidewall insulating layer (such as silicon nitride) 88 is formed on the side surface of the wiring groove 87 to prevent copper diffusion and oxidation.

The wiring groove 87 can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 86 by PEP and etching the interlayer insulating film 86 by RIE using this resist pattern as a mask. You can After this etching, the resist pattern is removed.

The sidewall insulating layer 88 is easily formed by forming an insulating film (such as silicon nitride) on the entire surface of the interlayer insulating film 86 by the CVD method and then etching the insulating film by RIE. can do.

[13] Step of Forming Fourth Wiring Layer Next, as shown in FIG. 65, for example, by sputtering, on the interlayer insulating film 79, on the inner surface of the wiring trench 87 and on the sidewall insulating layer 88. Then, a barrier metal layer (such as a stacked layer of Ta and TaN) 89 is formed on each of them. continue,
For example, by sputtering, on the barrier metal layer 89,
A metal layer (Al, Cu, etc. C that completely fills the wiring groove 87. C
In the case of u, the electrolytic plating method is used instead of the sputtering method. ) 91 is formed.

Thereafter, as shown in FIG. 66, for example, C
Using the MP method, the metal layer 91 is polished to form the metal layer 91.
It is left only in the wiring groove 87. The metal layer 91 remaining in the wiring groove 87 becomes a fourth wiring layer functioning as a write word line.

Further, an insulating layer (such as silicon nitride) 92 is formed on the interlayer insulating film 86 by the CVD method. Also,
The insulating layer 92 is polished by the CMP method to leave the insulating layer 92 on the metal layer 91 as the fourth wiring layer. An interlayer insulating film (such as silicon oxide) that completely covers the metal layer 91 as the fourth wiring layer is formed on the interlayer insulating film 86.
93 is formed.

[14] Step of Forming Lower Electrode of Second MTJ Element Next, as shown in FIGS. 67 and 68, the interlayer insulating film 7 is formed.
A contact hole reaching the lower electrode 72 of the first MTJ element is formed at 9, 93.

This contact hole is formed, for example, by PEP.
Thus, a resist pattern is formed on the interlayer insulating film 93, and the resist pattern is used as a mask to etch the interlayer insulating films 79 and 93 by RIE, whereby the resist pattern can be easily formed. After this etching, the resist pattern is removed.

Also, for example, a barrier metal layer (Ti and TiN) is formed on the inner surface of the contact hole by using the sputtering method.
And the like) 94 are formed. Subsequently, a metal layer (W or the like) 95 that completely fills the contact hole is formed on the barrier metal layer 94 by, for example, a sputtering method.

After that, the metal layer 95 is polished by, for example, the CMP method, and the metal layer 95 is left only in the contact hole. Metal layer 95 remaining in the contact hole
Is a contact plug. Further, a metal layer (Ta or the like) 96 to be a lower electrode of the second MTJ element is formed on the interlayer insulating film 93 by the sputtering method.

[15] Step of Forming Second MTJ Element Next, as shown in FIGS. 69 and 70, the second MTJ element 97 is formed on the metal layer 96. Second MTJ element 9
The main barrier 7 is composed of a tunnel barrier and two ferromagnetic layers sandwiching the tunnel barrier, and has a structure as shown in FIG. 7, for example.

Further, the lower electrode 96 of the second MTJ element 97
Pattern.

The lower electrode 96 of the second MTJ element 97 is patterned by forming a resist pattern on the lower electrode 96 by PEP and then etching the lower electrode 96 by RIE using this resist pattern as a mask. Easy to do. Then, the resist pattern is removed.

Thereafter, the interlayer insulating film 100 which completely covers the second MTJ element 97 is formed by the CVD method.

[16] Wiring Groove Forming Step Next, as shown in FIG. 71, a wiring groove 100 A is formed in the interlayer insulating film 100. In this example, the wiring groove 100A is
It is a groove for forming a read / write bit line and extends in the Y direction. Copper (C
When u) is used, a sidewall insulating layer (such as silicon nitride) for preventing copper diffusion and oxidation is formed on the side surface of the wiring groove 100A.

For the wiring groove 100A, a resist pattern is formed on the interlayer insulating film 100 by, for example, PEP,
By using this resist pattern as a mask, by RIE,
It can be easily formed by etching the interlayer insulating film 100. After this etching, the resist pattern is removed.

The sidewall insulating layer is easily formed by forming an insulating film (such as silicon nitride) on the entire surface of the interlayer insulating film 100 by the CVD method and then etching the insulating film by RIE. be able to.

[17] Step of Forming Fifth Wiring Layer Next, as shown in FIG. 72, on the interlayer insulating film 100, on the inner surface of the wiring groove 100A and on the sidewall insulating layer, for example, by using a sputtering method. A barrier metal layer (such as a Ta and TaN stacked layer) 101 is formed in each. Subsequently, the barrier metal layer 101 is formed by, for example, a sputtering method.
On top, a metal layer (Al, C
u etc. In the case of Cu, the electrolytic plating method is used instead of the sputtering method. ) 102 is formed.

Thereafter, as shown in FIG. 73, for example, C
The metal layer 102 is polished by using the MP method.
Are left only in the wiring groove 100A. The metal layer 102 remaining in the wiring groove 100A becomes a fifth wiring layer that functions as a read / write bit line.

Further, the interlayer insulating film 100 is formed by the CVD method.
An insulating layer (such as silicon nitride) 103 is formed thereover. The insulating layer 103 is polished by the CMP method so that the insulating layer 103 remains on the metal layer 102 as the fifth wiring layer. Further, an interlayer insulating film (silicon oxide or the like) 104 which completely covers the metal layer 102 as the fifth wiring layer is formed on the interlayer insulating film 100.

[18] Wiring Groove Forming Step Next, as shown in FIG. 74, a wiring groove 112 is formed in the interlayer insulating film 104. In this example, the wiring groove 112 is a groove for forming a write word line and extends in the X direction. When copper (Cu) is used as the wiring metal, a sidewall insulating layer (such as silicon nitride) 1 for preventing copper diffusion and oxidation is provided on the side surface of the wiring groove 112.
13 is formed.

The wiring groove 112 is formed by, for example, PEP.
It can be easily formed by forming a resist pattern on the interlayer insulating film 104 and etching the interlayer insulating film 104 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.

The sidewall insulating layer 113 is easily formed by forming an insulating film (such as silicon nitride) on the entire surface of the interlayer insulating film 104 by the CVD method and then etching the insulating film by RIE. can do.

[19] Step of forming sixth wiring layer Next, as shown in FIG. 75, for example, by sputtering, on the interlayer insulating film 104, on the inner surface of the wiring trench 112 and on the sidewall insulating layer 113. Then, a barrier metal layer (such as a stack of Ta and TaN) 114 is formed on each of them. Subsequently, the barrier metal layer 11 is formed by, for example, a sputtering method.
4 on which a metal layer (Al, C
u etc. In the case of Cu, the electrolytic plating method is used instead of the sputtering method. ) 115 is formed.

Thereafter, as shown in FIG. 76, for example, C
The metal layer 115 is polished by using the MP method to remove the metal layer 115.
Are left only in the wiring groove 112. The metal layer 115 remaining in the wiring groove 112 becomes a sixth wiring layer that functions as a write word line.

Also, the interlayer insulating film 104 is formed by the CVD method.
An insulating layer (such as silicon nitride) 116 is formed thereover. Further, the insulating layer 116 is polished by the CMP method to leave the insulating layer 116 on the metal layer 115 as the sixth wiring layer. Further, an interlayer insulating film (silicon oxide or the like) 117 is formed on the interlayer insulating film 104 so as to completely cover the metal layer 115 as the sixth wiring layer.

[20] Step of Forming Lower Electrode of Third MTJ Element Next, as shown in FIGS. 77 and 78, the interlayer insulating film 10 is formed.
At 0 and 104, contact holes reaching the lower electrode 96 of the second MTJ element are formed.

This contact hole is formed, for example, by PEP.
Thus, a resist pattern can be easily formed by forming a resist pattern on the interlayer insulating film 104 and using the resist pattern as a mask to etch the interlayer insulating films 100 and 104 by RIE. After this etching, the resist pattern is removed.

Also, for example, a barrier metal layer (Ti and TiN) is formed on the inner surface of the contact hole by using the sputtering method.
(E.g., a stack of layers) 118 are formed. Subsequently, a metal layer (W or the like) 119 that completely fills the contact hole is formed on the barrier metal layer 118 by, for example, a sputtering method.

Thereafter, the metal layer 119 is polished by, for example, the CMP method to leave the metal layer 119 only in the contact hole. Metal layer 1 remaining in the contact hole
19 is a contact plug. Further, a metal layer (Ta or the like) 120 to be the lower electrode of the third MTJ element is formed on the interlayer insulating film 117 by the sputtering method.

[21] Step of Forming Third MTJ Element Next, as shown in FIGS. 79 and 80, a third MTJ element 121 is formed on the metal layer 120. The third MTJ element 121 is mainly composed of a tunnel barrier and two ferromagnetic layers sandwiching the tunnel barrier, and has a structure as shown in FIG. 7, for example.

The lower electrode 1 of the third MTJ element 121
20 is patterned.

The lower electrode 120 of the third MTJ element 121 is patterned by forming a resist pattern on the lower electrode 120 by PEP and then etching the lower electrode 120 by RIE using this resist pattern as a mask. Easy to do. Then, the resist pattern is removed.

After that, the interlayer insulating film 122 which completely covers the third MTJ element 121 is formed by the CVD method.

[22] Step of Forming Wiring Groove Next, as shown in FIG. 81, a wiring groove 122A is formed in the interlayer insulating film 122. In this example, the wiring groove 122A is
It is a groove for forming a read / write bit line and extends in the Y direction. Copper (C
When u) is used, a sidewall insulating layer (such as silicon nitride) for preventing copper diffusion and oxidation is formed on the side surface of the wiring groove 122A.

For the wiring groove 122A, a resist pattern is formed on the interlayer insulating film 122 by PEP, for example.
By using this resist pattern as a mask, by RIE,
It can be easily formed by etching the interlayer insulating film 122. After this etching, the resist pattern is removed.

The sidewall insulating layer is easily formed by forming an insulating film (such as silicon nitride) on the entire surface of the interlayer insulating film 122 by the CVD method and then etching the insulating film by RIE. be able to.

[23] Step of Forming Seventh Wiring Layer Next, as shown in FIG. 82, on the interlayer insulating film 122, on the inner surface of the wiring groove 122A and on the sidewall insulating layer, for example, a sputtering method is used. A barrier metal layer (a stack of Ta and TaN, etc.) 123 is formed respectively. Subsequently, the barrier metal layer 123 is formed by, for example, a sputtering method.
On top, a metal layer (Al, C
u etc. In the case of Cu, the electrolytic plating method is used instead of the sputtering method. ) 124 is formed.

After that, as shown in FIG. 83, for example, C
The metal layer 124 is polished by using the MP method.
Are left only in the wiring groove 122A. The metal layer 124 remaining in the wiring groove 122A becomes a seventh wiring layer that functions as a read / write bit line.

Further, the interlayer insulating film 122 is formed by the CVD method.
An insulating layer (such as silicon nitride) 125 is formed thereover. The insulating layer 125 is polished by the CMP method so that the insulating layer 125 remains on the metal layer 124 as the seventh wiring layer. Further, an interlayer insulating film (silicon oxide or the like) 126 is formed on the interlayer insulating film 122 so as to completely cover the metal layer 124 as the seventh wiring layer.

[24] Wiring Groove Forming Step Next, as shown in FIG. 84, a wiring groove 127 is formed in the interlayer insulating film 126. In this example, the wiring groove 127 is a groove for forming a write word line and extends in the X direction. When copper (Cu) is used as the wiring metal, the sidewall insulating layer (such as silicon nitride) 1 for preventing diffusion and oxidation of copper is formed on the side surface of the wiring groove 127.
28 is formed.

The wiring groove 127 is formed by, for example, PEP.
It can be easily formed by forming a resist pattern on the interlayer insulating film 126 and etching the interlayer insulating film 126 by RIE using the resist pattern as a mask. After this etching, the resist pattern is removed.

The sidewall insulating layer 128 is easily formed by forming an insulating film (such as silicon nitride) on the entire surface of the interlayer insulating film 126 by the CVD method and then etching the insulating film by RIE. can do.

[25] Step of Forming Eighth Wiring Layer Next, as shown in FIG. 85, for example, by sputtering, on the interlayer insulating film 126, on the inner surface of the wiring groove 127 and on the sidewall insulating layer 128. Then, a barrier metal layer (such as a stacked layer of Ta and TaN) 129 is formed on each of them. Subsequently, the barrier metal layer 12 is formed by, for example, a sputtering method.
A metal layer (Al, C
u etc. In the case of Cu, the electrolytic plating method is used instead of the sputtering method. ) 130 is formed.

Thereafter, as shown in FIG. 86, for example, C
The metal layer 130 is polished by using the MP method,
Are left only in the wiring groove 127. The metal layer 130 remaining in the wiring groove 127 becomes an eighth wiring layer that functions as a write word line.

Further, the interlayer insulating film 126 is formed by the CVD method.
An insulating layer (such as silicon nitride) 131 is formed thereover. Further, the insulating layer 131 is polished by the CMP method to leave the insulating layer 131 on the metal layer 130 as the eighth wiring layer. Further, an interlayer insulating film (silicon oxide or the like) 132 which completely covers the metal layer 130 as the eighth wiring layer is formed on the interlayer insulating film 126.

[26] Step of Forming Lower Electrode of Fourth MTJ Element Next, as shown in FIGS. 87 and 88, the interlayer insulating film 12 is formed.
Contact holes 2 and 126 are formed to reach the lower electrode 120 of the third MTJ element.

This contact hole is formed, for example, by PEP.
Thus, a resist pattern is formed on the interlayer insulating film 126, and the resist pattern is used as a mask to etch the interlayer insulating films 122 and 126 by RIE, whereby the resist pattern can be easily formed. After this etching, the resist pattern is removed.

Also, for example, a barrier metal layer (Ti and TiN) is formed on the inner surface of the contact hole by using a sputtering method.
133) is formed. Subsequently, a metal layer (W or the like) 134 that completely fills the contact hole is formed on the barrier metal layer 133 by, for example, a sputtering method.

After that, the metal layer 134 is polished by, for example, the CMP method, and the metal layer 134 is left only in the contact hole. Metal layer 1 remaining in the contact hole
34 is a contact plug. Further, a metal layer (Ta or the like) 135 which will be the lower electrode of the fourth MTJ element is formed on the interlayer insulating film 132 by the sputtering method.

[27] Step of Forming Fourth MTJ Element Next, as shown in FIGS. 89 and 90, a fourth MTJ element 136 is formed on the metal layer 135. The fourth MTJ element 136 is mainly composed of a tunnel barrier and two ferromagnetic layers sandwiching the tunnel barrier, and has a structure as shown in FIG. 7, for example.

Also, the lower electrode 1 of the fourth MTJ element 136
35 is patterned.

The lower electrode 135 of the fourth MTJ element 136 is patterned by forming a resist pattern on the lower electrode 135 by PEP and then etching the lower electrode 135 by RIE using this resist pattern as a mask. Easy to do. Then, the resist pattern is removed.

After that, an interlayer insulating film 137 which completely covers the fourth MTJ element 136 is formed by the CVD method.

[28] Step of forming wiring groove Next, as shown in FIG. 91, a wiring groove 137A is formed in the interlayer insulating film 137. In this example, the wiring groove 137A is
It is a groove for forming a read / write bit line and extends in the Y direction. Copper (C
When u) is used, a sidewall insulating layer (such as silicon nitride) for preventing copper diffusion and oxidation is formed on the side surface of the wiring groove 137A.

For the wiring groove 137A, a resist pattern is formed on the interlayer insulating film 137 by PEP, for example.
By using this resist pattern as a mask, by RIE,
It can be easily formed by etching the interlayer insulating film 137. After this etching, the resist pattern is removed.

The sidewall insulating layer is easily formed by forming an insulating film (such as silicon nitride) on the entire surface of the interlayer insulating film 137 by the CVD method and then etching the insulating film by RIE. be able to.

[29] Step of Forming Ninth Wiring Layer Next, as shown in FIG. 92, on the interlayer insulating film 137, on the inner surface of the wiring groove 137A and on the sidewall insulating layer, for example, by using a sputtering method. A barrier metal layer (such as a stack of Ta and TaN) 138 is formed respectively. Subsequently, the barrier metal layer 138 is formed by, for example, a sputtering method.
On top of this, a metal layer (Al, C
u etc. In the case of Cu, the electrolytic plating method is used instead of the sputtering method. ) 139 is formed.

Thereafter, as shown in FIGS. 93 and 94,
For example, the metal layer 139 is polished by using the CMP method, and the metal layer 139 is left only in the wiring groove 137A. Wiring groove 1
The metal layer 139 remaining in 37A becomes a ninth wiring layer that functions as a read / write bit line.

[0506] Further, the interlayer insulating film 137 is formed by the CVD method.
An insulating layer (such as silicon nitride) 140 is formed thereover. The insulating layer 140 is polished by the CMP method so that the insulating layer 140 remains on the metal layer 139 serving as the ninth wiring layer.

Finally, for example, on the interlayer insulating film 137,
An interlayer insulating film (silicon oxide or the like) is formed to completely cover the metal layer 139 serving as the ninth wiring layer.

(3) Summary According to this manufacturing method, the read block is composed of a plurality of TMR elements stacked in a plurality of stages, and the plurality of TMR elements are each independently connected to the read bit line. Structure (1 switch-nMTJ
Structure) can be realized.

In this example, the damascene process and the dual damascene process are used to form the wiring layer. However, instead of this, for example, a process of etching the wiring layer by etching may be adopted.

6. Others In the above description, it is assumed that the TMR element is used as the memory cell of the magnetic random access memory.
Even when the memory cell is a GMR (Giant Magneto Resistance) element, the present invention, that is, various cell array structures, read operation principles, and specific examples of the read circuit can be applied.

Further, the structure of the TMR element and the GMR element,
There are no particular restrictions on the materials or the like that make up these elements in applying the present invention.

As the read selection switch of the magnetic random access memory, the MOS transistor, the bipolar transistor and the diode have been described, but other switch elements such as MIS (Metal I).
nsulator Semiconductor) transistor (including MOSFET), MES (Metal Semiconductor) transistor, junction
A (junction) transistor or the like can also be used as the read selection switch.

[0513]

As described above, according to the present invention, firstly, it is possible to provide a magnetic random access memory having a novel cell array structure suitable for increasing the memory capacity and a manufacturing method thereof. Secondly, it is possible to provide a novel read operation principle suitable for the new cell array structure and capable of high-speed read. Furthermore, thirdly, a read circuit for realizing the novel read operation principle can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram related to a structural example 1 of a magnetic random access memory of the present invention.

FIG. 2 is a circuit diagram relating to Structural Example 1 of the magnetic random access memory of the present invention.

FIG. 3 is a circuit diagram relating to a modification of Structural Example 1 of the magnetic random access memory of the present invention.

FIG. 4 is a cross-sectional view relating to Structural Example 1 of the magnetic random access memory of the present invention.

FIG. 5 is a cross-sectional view relating to Structural Example 1 of the magnetic random access memory of the present invention.

FIG. 6 is a plan view showing a layout of a TMR element of Structural Example 1 and its vicinity.

FIG. 7 is a diagram showing a structural example of a TMR element.

FIG. 8 is a diagram showing a structural example of a TMR element.

FIG. 9 is a diagram showing a structural example of a TMR element.

FIG. 10 is a circuit diagram relating to Structural Example 2 of the magnetic random access memory of the present invention.

FIG. 11 is a cross-sectional view relating to Structural Example 2 of the magnetic random access memory of the present invention.

FIG. 12 is a cross-sectional view relating to Structural Example 2 of the magnetic random access memory of the present invention.

FIG. 13 is a circuit diagram relating to Structural Example 3 of the magnetic random access memory of the present invention.

FIG. 14 is a circuit diagram relating to Structural Example 3 of the magnetic random access memory of the present invention.

FIG. 15 is a circuit diagram of a modified example of Structural Example 3 of the magnetic random access memory according to the present invention.

FIG. 16 is a circuit diagram of a modified example of Structural Example 3 of the magnetic random access memory according to the present invention.

FIG. 17 is a cross-sectional view relating to Structural Example 3 of the magnetic random access memory of the present invention.

FIG. 18 is a cross-sectional view relating to Structural Example 3 of the magnetic random access memory of the present invention.

19 is a plan view showing a layout of a TMR element of Structural Example 3 and its vicinity. FIG.

FIG. 20 is a circuit diagram of Structural Example 4 of the magnetic random access memory according to the present invention.

FIG. 21 is a cross-sectional view related to Structural Example 4 of the magnetic random access memory of the present invention.

FIG. 22 is a cross-sectional view related to Structural Example 4 of the magnetic random access memory of the present invention.

FIG. 23 is a circuit diagram relating to Structural Example 5 of the magnetic random access memory of the present invention.

FIG. 24 is a cross-sectional view related to Structural Example 5 of the magnetic random access memory of the present invention.

FIG. 25 is a cross-sectional view relating to Structural Example 5 of the magnetic random access memory of the present invention.

FIG. 26 is a circuit diagram relating to Structural Example 6 of the magnetic random access memory of the present invention.

FIG. 27 is a cross-sectional view related to Structural Example 6 of the magnetic random access memory of the present invention.

FIG. 28 is a cross-sectional view related to Structural Example 6 of the magnetic random access memory of the present invention.

FIG. 29 is a circuit diagram relating to Structural Example 7 of the magnetic random access memory of the present invention.

FIG. 30 is a cross-sectional view related to Structural Example 7 of the magnetic random access memory of the present invention.

FIG. 31 is a circuit diagram relating to Structural Example 8 of the magnetic random access memory of the present invention.

FIG. 32 is a cross-sectional view related to Structural Example 8 of the magnetic random access memory of the present invention.

FIG. 33 is a diagram showing a circuit example of a write word line driver / sinker.

FIG. 34 is a diagram showing a circuit example of a write bit line driver / sinker.

FIG. 35 is a diagram showing a circuit example of a write bit line driver / sinker.

FIG. 36 is a diagram showing a circuit example of a read word line driver.

FIG. 37 is a diagram showing a circuit example of a read word line driver.

FIG. 38 is a diagram showing a circuit example of a column decoder.

FIG. 39 is a diagram showing a circuit example of a column decoder.

FIG. 40 is a diagram showing a circuit example of a reading circuit.

FIG. 41 is a diagram showing a circuit example of a reading circuit.

FIG. 42 is a diagram showing a circuit example of a sense amplifier & bias circuit.

FIG. 43 is a diagram showing a circuit example of a sense amplifier.

FIG. 44 is a diagram showing a circuit example of a reference potential generation circuit.

FIG. 45 is a diagram showing a circuit example of an operational amplifier.

FIG. 46 is a view showing a device structure to which the manufacturing method of the present invention is applied.

FIG. 47 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 48 is a sectional view showing a step of the manufacturing method of the present invention.

FIG. 49 is a plan view showing one step of the manufacturing method of the present invention.

50 is a sectional view taken along the line LL in FIG. 49.

FIG. 51 is a cross-sectional view showing one step in the manufacturing method of the present invention.

FIG. 52 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 53 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 54 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 55 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 56 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 57 is a plan view showing one step of the manufacturing method of the present invention.

58 is a cross-sectional view taken along the line LVIII-LVIII in FIG. 57.

FIG. 59 is a plan view showing one step of the manufacturing method of the present invention.

FIG. 60 is a sectional view taken along line LX-LX in FIG. 59.

FIG. 61 is a sectional view showing a step of the manufacturing method of the present invention.

FIG. 62 is a sectional view showing a step of the manufacturing method of the present invention.

FIG. 63 is a cross-sectional view showing one step in the manufacturing method of the present invention.

FIG. 64 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 65 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 66 is a cross-sectional view showing one step of the manufacturing method of the present invention.

67 is a plan view showing one step of the manufacturing method of the present invention. FIG.

68 is a cross-sectional view taken along the line LXVIII-LXVIII in FIG. 67.

FIG. 69 is a plan view showing one step of the manufacturing method of the present invention.

70 is a cross-sectional view taken along the line LXX-LXX in FIG. 69.

FIG. 71 is a sectional view showing a step of the manufacturing method of the present invention.

FIG. 72 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 73 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 74 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 75 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 76 is a cross-sectional view showing one step of the manufacturing method of the present invention.

77 is a plan view showing one step of the manufacturing method of the present invention. FIG.

78 is a cross-sectional view taken along the line LXXVIII-LXXVIII in FIG. 77.

FIG. 79 is a plan view showing one step of the manufacturing method of the present invention.

80 is a cross-sectional view taken along the line LXXX-LXXX in FIG. 79.

FIG. 81 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 82 is a cross-sectional view showing one step in the manufacturing method of the present invention.

FIG. 83 is a cross-sectional view showing one step in the manufacturing method of the present invention.

FIG. 84 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 85 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 86 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 87 is a plan view showing one step of the manufacturing method of the present invention.

88 is the LXXXVIII-LXXXVII of FIG. 87.
Sectional drawing which follows the I line.

89 is a plan view showing one step of the manufacturing method of the present invention. FIG.

90 is a cross-sectional view taken along the line XL-XL in FIG. 89.

FIG. 91 is a cross-sectional view showing one step of the manufacturing method of the present invention.

FIG. 92 is a sectional view showing a step of the manufacturing method of the present invention.

FIG. 93 is a plan view showing one step of the manufacturing method of the present invention.

94 is a sectional view taken along line XCIV-XCIV in FIG. 93.

95 is a diagram showing a modification of the circuit structure of the memory according to structure example 1. FIG.

96 is a view showing a modified example of the circuit structure of the memory according to Structural Example 1. FIG.

97 is a view showing a modification of the device structure of the memory according to structure example 1. FIG.

98 is a diagram showing a modification of the device structure of the memory according to structure example 1. FIG.

99 is a view showing a modified example of the device structure of the memory according to Structural Example 1. FIG.

100 is a diagram showing a modification of the device structure of the memory according to structure example 1. FIG.

101 is a diagram showing a modified example of the circuit structure of the memory according to Structural Example 2; FIG.

102 is a view showing a modified example of the device structure of the memory according to Structural Example 2; FIG.

103 is a diagram showing a modification of the device structure of the memory according to structure example 2. FIG.

FIG. 104 is a diagram showing a modified example of the device structure of the memory according to Structural Example 2;

FIG. 105 is a view showing a modified example of the device structure of the memory according to Structural Example 2;

FIG. 106 is a diagram showing a modified example of the circuit structure of the memory according to Structural Example 3;

FIG. 107 is a diagram showing a modified example of the circuit structure of the memory according to Structural Example 3;

FIG. 108 is a view showing a modified example of the device structure of the memory according to Structural Example 3;

109 is a diagram showing a modification of the device structure of the memory according to structure example 3. FIG.

110 is a view showing a modified example of the device structure of the memory according to Structural Example 3; FIG.

111 is a diagram showing a modified example of the device structure of the memory according to Structural Example 3; FIG.

112 is a diagram showing a modification of the circuit structure of the memory according to structure example 4. FIG.

113 is a view showing a modified example of the device structure of the memory according to Structural Example 4; FIG.

FIG. 114 is a diagram showing a modification of the device structure of the memory according to structure example 4;

115 is a diagram showing a modification of the device structure of the memory according to structure example 4. FIG.

FIG. 116 is a diagram showing a modification of the device structure of the memory according to structure example 4;

[Explanation of symbols]

11: memory cell array, 12: TMR element, 23A-1, ... 23A-n: write word line driver, 24-1, ... 24-n: write word line sinker, 25-1, ... 25 -N: row decoder, 29A: write bit line driver / sinker, 29B: read circuit, 29B11, ... 29B14: sense amplifier & bias circuit, 29B2: selector, 29B3: output buffer, 29C: column selection switch, 30: Common data line, 31: write bit line driver / sinker, 32: column decoder, 41, 51: semiconductor substrate, 42A, ... 42E: contact plug, 43: intermediate layer, 44A, ... 44D: lower electrode, 52: Element isolation insulating layer, 53: Gate insulating film, 54: Gate electrode 55: cap insulating film, 56A: source regions, 56B: drain regions, 57,65,88: sidewall insulating layer, 58,63,69,75,79,93,100,10
4, 122, 126, 137: interlayer insulating film, 59: contact hole, 60, 64, 75A, 87, 100A, 112, 122
A, 127, 137A: wiring groove, 61, 66, 70, 76, 80, 89, 94, 114,
118, 123, 129, 138: barrier metal layer, 62, 67, 71, 77, 81, 90, 95, 115,
119,124,130,139: metal layer, 68,78,92,103,116,125,131,
140: insulating layer, 73, 97, 108, 120, 136: MTJ
Element, 72, 96, 121, 135: lower electrode, MTJ1, ... MTJ4: TMR element (MT
J element), BK11, ... BKjn: read block, WWL4 (n-1) +1, ... WWL4 (n-1) +
4: write word line, RWL1, ... RWLn: read word line, BL1, ... BLj: read / write bit line, QP1, ... QP19: P channel MOS
Transistors, QN1, ... QN20: N-channel MOS
AD1, ... AD10: AND circuit, ND1, ... ND12: NAND circuit, INV1, ... INV8: inverter circuit, OP: operational amplifier, Is1, Is2: constant current source, RSW: read selection switch, BSW: Block selection switch.

Claims (40)

[Claims] 1. A plurality of memory cells that store data by utilizing a magnetoresistive effect stacked in a plurality of stages, a read selection switch commonly connected to one end of the plurality of memory cells, and the plurality of memory cells. And a plurality of bit lines extending in a first direction, the other end of each of the plurality of memory cells being independently connected to one of the plurality of bit lines. A magnetic random access memory in which a plurality of bit lines are electrically insulated from each other during reading. 2. The magnetic random access memory according to claim 1, wherein the read selection switch is arranged immediately below the plurality of memory cells. 3. The method according to claim 1, further comprising a plurality of contact plugs that connect one end of the plurality of memory cells and the read selection switch, and the plurality of contact plugs overlap each other. The magnetic random access memory described. 4. The magnetic random access memory according to claim 1, further comprising a source line connected to the read selection switch and extending in the first direction. 5. The magnetic random access memory according to claim 4, further comprising a power supply terminal and a column selection switch connected between the source line and the power supply terminal. 6. The magnetic random access memory according to claim 4, further comprising a read word line connected to a control terminal of the read selection switch and extending in a second direction intersecting the first direction. . 7. The magnetic random access memory according to claim 6, wherein the read selection switch is controlled by a row address signal. 8. The magnetic random access memory according to claim 1, further comprising a read word line connected to the read selection switch and extending in a second direction intersecting the first direction. 9. The magnetic random access memory according to claim 8, further comprising a decode line connected to a control terminal of the read selection switch and extending in the first direction. 10. The magnetic random access memory according to claim 9, wherein the read selection switch is controlled by a column address signal. 11. The magnetic random access memory according to claim 1, further comprising a read circuit and a column selection switch connected between the plurality of bit lines and the read circuit. 12. The magnetic random access memory according to claim 11, wherein the read selection switch and the column selection switch perform the same operation. 13. The read circuit includes a plurality of sense amplifiers provided corresponding to the plurality of bit lines, and a plurality of output buffers provided corresponding to the plurality of sense amplifiers. The magnetic random access memory according to claim 11. 14. The read circuit includes a plurality of sense amplifiers provided corresponding to the plurality of bit lines, an output buffer for outputting data of one of the plurality of sense amplifiers, and a plurality of the plurality of sense amplifiers. The magnetic random access memory according to claim 11, comprising a selector connected between a sense amplifier and the output buffer. 15. A write bit line driver / sinker, which is connected to both ends of each of the plurality of bit lines, for supplying a write current in a direction according to write data to the plurality of bit lines. The magnetic random access memory according to claim 1. 16. The magnetic random access memory according to claim 1, wherein the plurality of bit lines function as a read bit line and a write bit line. 17. The magnetic device according to claim 1, further comprising a plurality of write word lines provided corresponding to the plurality of memory cells and extending in a second direction intersecting the first direction. Random access memory. 18. The magnetic random access memory according to claim 17, wherein each of the plurality of write word lines is arranged at one end side of the plurality of memory cells. 19. The magnetic random access memory according to claim 1, further comprising a plurality of block selection switches connected between the other ends of the plurality of memory cells and the plurality of bit lines. . 20. The block selection switch is controlled by a row address signal.
9. The magnetic random access memory according to 9. 21. The magnetic random access memory according to claim 19, wherein the read selection switch and the block selection switch operate in the same manner. 22. The magnetic random access memory according to claim 1, wherein the plurality of memory cells form one read block, and the data of the plurality of memory cells are read simultaneously. 23. Each of the plurality of memory cells is arranged between a pinned layer whose magnetization direction is fixed, a storage layer whose magnetization direction changes according to write data, and between the pinned layer and the storage layer. The magnetic random access memory according to claim 1, wherein the magnetic random access memory comprises a magnetic storage element including a tunnel barrier layer. 24. The magnetic random access memory according to claim 23, wherein an easy axis of magnetization of the magnetic memory element is oriented in a second direction intersecting the first direction. 25. The read selection switch is a MIS.
The magnetic random access memory according to claim 1, wherein the magnetic random access memory is one of a transistor, a MES transistor, a junction transistor, a bipolar transistor, and a diode. 26. The magnetic random access memory according to claim 1, wherein the value of the data to be written in the plurality of memory cells is determined by the direction of the write current flowing in the plurality of bit lines. 27. Stacked first and second memory cells for storing data using a magnetoresistive effect, a read selection switch connected to one end of the first and second memory cells, and the first A first bit line connected to the other end of the memory cell; and a second bit line connected to the other end of the second memory cell, wherein the data of the first and second memory cells are A magnetic random access memory which outputs to the first and second bit lines. 28. Reading of a magnetic random access memory having a read block composed of a plurality of memory cells for storing data by utilizing a magnetoresistive effect, and a plurality of sense amplifiers provided corresponding to the plurality of memory cells. In the method, a read current is applied to the plurality of memory cells simultaneously and independently, a step of detecting data of the plurality of memory cells by the plurality of sense amplifiers based on the read current, and a plurality of sense operations. And a step of simultaneously outputting the data of the amplifier, the reading method of the magnetic random access memory. 29. Reading of a magnetic random access memory having a read block composed of a plurality of memory cells for storing data by utilizing a magnetoresistive effect, and a plurality of sense amplifiers provided corresponding to the plurality of memory cells. In the method, a read current is applied to the plurality of memory cells simultaneously and independently, a step of detecting data of the plurality of memory cells by the plurality of sense amplifiers based on the read current, And a step of selectively outputting data of one of the amplifiers, the reading method of the magnetic random access memory. 30. The magnetic random access memory reading method according to claim 28, wherein the data of the plurality of memory cells are independently detected by the plurality of sense amplifiers. 31. The other end of each of the plurality of memory cells is short-circuited, and the read current flows from one end of the plurality of memory cells to the other end thereof. A method for reading the magnetic random access memory described. 32. The plurality of sense amplifiers detect data in the plurality of memory cells by comparing a read potential generated from the read current with a reference potential. A method of reading the magnetic random access memory according to 1. 33. The method of reading a magnetic random access memory according to claim 32, wherein the reference potential is generated using a resistance element having the same structure as the memory cell. 34. The method of reading a magnetic random access memory according to claim 28, wherein when reading the data of the plurality of memory cells, a ground potential is applied to one end of the plurality of memory cells. 35. When the data of the plurality of memory cells is not read, one end of the plurality of memory cells is in a short-circuited state and the other end is in a floating state. A method of reading the magnetic random access memory according to 1. 36. A step of forming a read selection switch in a surface region of a semiconductor substrate, a step of forming a first write word line extending in a first direction on the read selection switch, and a step immediately above the first write word line. Forming a first MTJ element on the first MTJ element, and forming a first read / write bit line on the first MTJ element, the first read / write bit line being in contact with the first MTJ element and extending in a second direction intersecting the first direction. Forming a second write word line extending in the first direction directly above the first write word line; forming a second MTJ element immediately above the second write word line;
Directly above the MTJ element, forming a second read / write bit line in contact with the second MTJ element and extending in the second direction, the first and second write word lines and the first and second write word lines. A method of manufacturing a magnetic random access memory, wherein at least one of the second read / write bit lines is formed by a damascene process. 37. At least one of the first and second write word lines and the first and second read / write bit lines forms a wiring groove in an insulating layer, and completely fills the wiring groove. 37. The method of manufacturing a magnetic random access memory according to claim 36, wherein the method is formed by forming a metal layer and removing the metal layer other than inside the wiring groove. 38. The method of manufacturing a magnetic random access memory according to claim 37, further comprising the step of forming a barrier metal layer before forming the metal layer. 39. Before forming the barrier metal layer,
Forming a sidewall insulating layer on the side wall of the wiring groove; and removing the metal layer except in the wiring groove, and then forming a cap insulating layer on the metal layer from the same material as the sidewall insulating layer. 39. The method of manufacturing a magnetic random access memory according to claim 38, further comprising: 40. The method of manufacturing a magnetic random access memory according to claim 39, wherein the sidewall insulating layer and the cap insulating layer are made of silicon nitride.