TWI594340B - 用於具有晶粒對封裝的基板第一接合的半導體裝置封裝的方法和系統 - Google Patents

用於具有晶粒對封裝的基板第一接合的半導體裝置封裝的方法和系統 Download PDF

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TWI594340B
TWI594340B TW102141436A TW102141436A TWI594340B TW I594340 B TWI594340 B TW I594340B TW 102141436 A TW102141436 A TW 102141436A TW 102141436 A TW102141436 A TW 102141436A TW I594340 B TWI594340 B TW I594340B
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die
package substrate
interposer
bonding
semiconductor
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TW102141436A
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TW201430968A (zh
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麥可Ｇ 凱利
羅納 派翠克 休莫勒
杜旺朱
大衛 強 海納
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艾馬克科技公司
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Description

用於具有晶粒對封裝的基板第一接合的半導體裝置封裝的方法和系統 【相關申請案之交互參照/納入參考】
此申請案係參考到2012年11月15日申請的美國申請案序號13/678,058(代理人文件編號25031US01)、以及2012年11月15日申請的美國申請案序號13/678,012(代理人文件編號25963US01)。
以上所引用的申請案的每一個茲在此以其整體納入作為參考。
本發明的某些實施例係有關於半導體晶片封裝。更明確地說，本發明的某些實施例係有關於一種用於一具有一晶粒至封裝基板第一接合的半導體裝置封裝之方法及系統。
半導體封裝係保護積體電路或晶片免於物理性損壞以及外部的應力。此外，其可以提供一導熱路徑以有效率地移除在一晶片中所產生的熱，並且例如亦提供電連接至其它例如是印刷電路板的構件。用於半導體封裝的材料通常包括陶瓷或塑膠，並且外觀形狀尺寸已經從陶瓷扁平封裝及雙排型封裝進步到尤其是針柵陣列及無引線的晶片載體封裝。
透過此種系統與如同在本申請案的其餘部分中參考圖式所 闡述的本發明比較，習知及傳統的方法的進一步限制及缺點對於具有此項技術的技能者而言將會變成是明顯的。
本發明的一態樣為一種用於半導體封裝之方法，該方法係包 括：接合一第一半導體晶粒至一封裝基板；在該第一半導體晶粒以及該封裝基板之間施加一底膠填充材料；以及接合一或多個額外的晶粒至該第一半導體晶粒，其中該一或多個額外的晶粒包括電子裝置。
本發明的另一態樣為一種用於半導體封裝之方法，該方法係 包括：在一晶粒至封裝基板第一接合中產生一半導體封裝，該產生包括：利用一熱壓縮製程來接合一中介層晶粒至一封裝基板；在接合的該中介層晶粒以及該封裝基板之間施加一底膠填充材料；利用一熱壓縮製程來接合一或多個額外的晶粒至接合的該中介層晶粒，其中該一或多個額外的晶粒包括電子裝置；以及在接合的該一或多個額外的晶粒以及接合的該中介層晶粒之間施加一底膠填充材料。
本發明的另一態樣為一種用於半導體封裝之方法，該方法 係包括：在一晶粒至封裝基板第一接合中產生一半導體封裝，該製程包括：接合一第一半導體晶粒至一封裝基板；利用一質量回焊製程來接合一或多個額外的晶粒至該第一半導體晶粒，其中該一或多個額外的晶粒包括電子裝置；在該第一半導體晶粒以及該封裝基板之間並且在該一或多個額外的晶粒以及該第一半導體晶粒之間施加一底膠填充材料；以及在接合的該第一晶粒以及接合的該一或多個額外的晶粒的周圍設置一模製材料。
100‧‧‧封裝
101‧‧‧晶粒
103‧‧‧封裝基板
105‧‧‧被動元件
107‧‧‧中介層
109‧‧‧微凸塊
111‧‧‧焊料球
113‧‧‧蓋子
115‧‧‧直通矽晶穿孔(TSV)
117‧‧‧背面凸塊
118‧‧‧熱介面材料
119‧‧‧墊
121‧‧‧動態隨機存取記憶體(DRAM)(晶粒)
123‧‧‧金屬互連
125‧‧‧底膠填充材料
127‧‧‧晶粒
129‧‧‧黏著層
131‧‧‧金屬墊
150‧‧‧封裝
200‧‧‧晶粒至封裝製程
201、203、205、207、209、211、213、215、217、219、221、223‧‧‧步驟
301A、301B、303A、303B、305A、305B、307A、307B、309‧‧‧步驟
401A、401B‧‧‧底膠填充
501、503、505、507、509、511‧‧‧步驟
601‧‧‧前側墊
603‧‧‧支承結構
605‧‧‧金屬互連層
607‧‧‧背面凸塊
610‧‧‧中介層
701、703、705、707、711、713、715、717、719、721‧‧‧步驟
801A‧‧‧晶粒
801B‧‧‧晶粒
803A‧‧‧底膠填充材料
811‧‧‧熱介面材料
813‧‧‧焊料球
821‧‧‧包覆成型
823‧‧‧散熱片
825‧‧‧基板
901‧‧‧晶舟
903‧‧‧夾子
905‧‧‧晶粒
907‧‧‧中介層
909‧‧‧基板
1001‧‧‧晶舟
1005‧‧‧晶粒
1007‧‧‧中介層
1008‧‧‧基板
1009‧‧‧真空密封環
1011‧‧‧真空通道
1013‧‧‧閥
1015‧‧‧真空源
1101‧‧‧載體晶圓
1103‧‧‧裝置晶圓
1105‧‧‧背面凸塊
1107‧‧‧聚合物層
1109A‧‧‧頂端夾頭
1109B‧‧‧底部夾頭
1111‧‧‧膜框架
1201‧‧‧頂端晶粒
1203‧‧‧微凸塊
1205‧‧‧底部晶粒
1207‧‧‧接觸墊
1209‧‧‧底膠填充層
圖1A是描繪根據本發明的一範例實施例的一種被配置有一中介層至封裝基板第一接合的積體電路封裝之概要圖。
圖1B是描繪根據本發明的一範例實施例的一種被配置有一中介層至封裝基板第一接合以及堆疊的晶粒的積體電路封裝之概要圖。
圖1C-1E係描繪根據本發明的一範例實施例的用於利用一黏著膜來接合多個晶粒的步驟。
圖2是描繪根據本發明的一範例實施例的一種晶粒至封裝基板製程流程之概要圖。
圖3是描繪根據本發明的一範例實施例的用在一封裝中的晶粒之接合選項的概要圖。
圖4A-4C係描繪根據本發明的一範例實施例的一種用於一中介層至封裝基板第一接合的製程。
圖5是描繪根據本發明的一範例實施例的一種中介層製程之流程圖。
圖6A-6B係描繪在根據本發明的一範例實施例的一種中介層製程中之最初的步驟。
圖6C-6D係描繪在根據本發明的一範例實施例的一種中介層製程中之最後的步驟。
圖7是描繪根據本發明的一範例實施例的一堆疊的晶粒至封裝基板製程之流程圖。
圖8A-8B係描繪在根據本發明的一範例實施例的一有功能的晶粒至封 裝基板組裝製程中之最初的步驟。
圖8C-8D係描繪在根據本發明的一範例實施例的一有功能的晶粒至封裝基板組裝製程中之最後的步驟。
圖8E係描繪在根據本發明的一範例實施例的晶粒至封裝基板製程中所產生的組件。
圖9是描繪根據本發明的一範例實施例的一機械式平坦化裝置之圖。
圖10是描繪根據本發明的一範例實施例的一真空平坦化裝置之圖。
圖11A-11E係描繪根據本發明的一範例實施例的用於脫黏具有大的背面凸塊的晶圓之步驟。
圖12是描繪根據本發明的一範例實施例的利用一圖案化的底膠填充層的晶粒至晶粒的接合之圖。
本發明的某些特點可見於一種用於一具有一晶粒至封裝基 板第一接合的半導體裝置封裝之方法及系統。本發明的範例特點可包括接合一第一半導體晶粒至一封裝基板，在該第一半導體晶粒以及該封裝基板之間施加一種底膠填充(underfill)材料，以及接合一或多個額外的晶粒至該第一半導體晶粒。該一或多個額外的晶粒可包括電子裝置。該第一半導體晶粒可包括一中介層晶粒、或是該第一半導體晶粒可包括電子裝置。該第一半導體晶粒可利用一質量回焊製程或是一熱壓縮製程而被接合至該封裝基板。該一或多個額外的晶粒可利用一質量回焊製程或是一熱壓縮製程而被接合至該第一晶粒。該接合的第一晶粒以及該接合的一或多個額外的晶粒可被囊封在一種模製材料中。該模製材料可包括一種聚合物。該一或多個 額外的晶粒可包括用於耦接至該第一半導體晶粒的微凸塊。
圖1A是描繪根據本發明的一範例實施例的一種被配置有一 中介層至封裝基板第一接合的積體電路封裝之概要圖。參照圖1A，其係展示有一種封裝100，其包括晶粒101、一封裝基板103、被動元件105、一中介層107、焊料球111、一蓋子113、以及熱介面材料118。
該晶粒101可包括已經從一或多個半導體晶圓分開的積體 電路晶粒。例如，該晶粒101可包括像是數位信號處理器(DSP)、網路處理器、電源管理單元、音訊處理器、RF電路、無線基頻系統單晶片(SoC)處理器、感測器、以及特殊應用積體電路之電路。此外，該晶粒101可包括微凸塊109，以用於提供在該晶粒101中的電路以及在該中介層107的表面上的接觸墊之間的電性接觸。
該中介層107可包括一例如是矽晶粒的半導體晶粒，其係具 有提供從該中介層107的一表面至相對的表面之導電的路徑之直通矽晶穿孔(TSV)115。該中介層107亦可包括用於達成電性及機械的接觸至該封裝基板103之背面凸塊117。在另一範例情節中，該中介層107可包括玻璃或是一種有機積層材料，其任一種都可以能夠有例如是500x500mm的數量級之大的面板格式。
該封裝基板103可包括一用於該中介層107、晶粒101、被 動元件105以及蓋子113之機械式的支承結構。該封裝基板103例如可包括在底表面上的焊料球111，以用於提供電性接觸至外部的裝置及電路。該封裝基板103亦可包括在一種非導電材料中之導電的線路，以用於經由墊來提供從該焊料球至該晶粒101的導電的路徑，該墊被配置以接收該中介層 107上的背面凸塊117。此外，該封裝基板103可包括用於接收該焊料球111的墊119。該墊119例如可包括一或多種凸塊下的金屬，以用於在該封裝基板103以及該焊料球111之間提供一適當的電性及機械的接觸。
例如，該被動元件105可包括像是電阻器、電容器及電感器 的電性元件，其可以提供功能給在該晶粒101中的元件及電路。該被動元件105可包括可能是難以整合在該晶粒101中的積體電路內之元件，例如是高值的電容器或電感器。在另一範例情節中，該被動元件105可包括一或多個晶體振盪器，以用於提供一或多個時脈信號至該晶粒101。
該蓋子113可提供氣密密封給在藉由該蓋子113以及該封裝 基板103所界定的凹處內的元件。一熱介面可被產生，以用於經由該熱介面材料118將熱從該晶粒101傳出至該蓋子113，該熱介面材料118亦可作用為一黏著劑。
在一範例情節中，該封裝100可藉由利用一質量回焊或是熱 壓縮製程來第一接合該中介層107至該封裝基板103而加以製造。該晶粒101接著可利用質量回焊或是熱壓縮的任一種而被接合至該中介層107。一毛細管底膠填充製程可為了機械及絕緣之目的而接在該接合製程之後。電性測試可以在該接合製程後加以執行，以驗證是否達成適當的電連接並且沒有短路或開路存在。
圖1B是描繪根據本發明的一範例實施例的一種被配置有一 中介層至封裝基板第一接合以及堆疊的晶粒的積體電路封裝之概要圖。參照圖1B，其係展示有一種封裝150，其包括該晶粒101、封裝基板103、被動元件105、中介層107、以及動態隨機存取記憶體(DRAM)121的一堆疊。 例如，該晶粒101、封裝基板103、被動元件105、以及中介層107可以是實質如同相關圖1A所述者，但是對於不同的晶粒101以及DRAM 121的堆疊係具有不同的電連接。
該DRAM 121可包括晶粒的一堆疊，以用於提供一高密度的 記憶體給在該晶粒101中的電路或是在該封裝100外部的電路。該DRAM 121可以是前後地加以堆疊，並且因此包括用於在該個別的晶粒之間提供電連接的TSV。
在一範例情節中，該封裝150可藉由利用一質量回焊或是熱 壓縮製程來第一接合該中介層107至該封裝基板103而被製造。該晶粒101接著可利用質量回焊或是熱壓縮中的任一種而被接合至該中介層107。此外，DRAM 121的堆疊接著可被接合至該中介層107。一毛細管底膠填充製程可以為了機械及絕緣之目的而接在該接合製程之後。電性測試可以在該接合製程後加以執行，以驗證是否達成適當的電連接並且沒有短路或開路存在。
圖1C-1E係描繪根據本發明的一範例實施例的用於利用一 黏著膜來接合多個晶粒的步驟。參照圖1C，其係展示有複數個晶粒121以及一黏著層129。該複數個晶粒121的每一個可包括一金屬互連123，以用於後續的接合至其它晶粒。在另一範例情節中，該金屬互連123例如可包括微凸塊或是銅柱。
例如，該黏著膜129可包括一黏著帶或是柔性層，該複數個 晶粒121可被接合至該黏著帶，即如同在圖1C中所繪者。該黏著膜129可以是一暫時性黏著劑，以用於附接多個晶粒至另一晶粒。在一範例情節中， 該複數個晶粒121可以暫時被置放在該黏著膜129上。儘管圖1C係描繪該複數個晶粒121為由三個晶粒所構成，但是更多或較少的晶粒(包含單一晶粒)也是可能的而且被思及。
如同在圖1D中所示，一旦該複數個晶粒121已經附接至該 黏著膜129之後，一種選配的底膠填充材料125亦可被置放在一晶粒127上。該底膠填充材料125例如可用於後續的熱壓縮接合製程，並且可容許有在一後續的熱壓縮接合製程期間透過一快速固化之瞬間的底膠填充。此可以改善接合良率，因為相較於用在該複數個晶粒121的每一個之一個別的置放及底膠填充製程，單一底膠填充製程可被利用於該複數個晶粒121。 該複數個晶粒121可以面朝上地加以置放，因而該金屬互連123可耦接至一接收的晶粒。
如同在圖1D及1E中所示，在該黏著膜129上的複數個晶 粒121接著例如可被置放在該晶粒127(或是其它例如是封裝基板的基板)上，其中在該黏著膜129上的複數個晶粒121之最初的設置可以致能細微的控制該複數個晶粒121與該晶粒127的間隔及對準。在一範例情節中，該晶粒127可被多端子接合(gang bond)至該個別的晶粒121。該晶粒127可包括用於接收該金屬互連123的金屬墊131。一旦該複數個晶粒121被設置在該晶粒127上，一熱壓縮接合製程可以為了在該金屬互連123以及金屬墊131之間適當的電性及機械的接合來加以執行。一旦接合後，該黏著膜129可被移除，此係產生在圖1E中所示的結構。
圖2是描繪根據本發明的一範例實施例的一種晶粒至封裝 基板製程流程之概要圖。參照圖2，其係展示有晶粒至封裝製程200，其包 括一膏印刷步驟201、一助焊劑(flux)噴射步驟203、一被動元件安裝步驟205、以及熱壓縮接合中介層步驟207。該封裝製程200亦可包括一助焊劑清洗步驟209、一底膠填充及固化步驟211、一助焊劑浸漬步驟213、以及一熱壓縮頂端晶粒接合步驟215。接在這些步驟後面的可以是一底膠填充及固化步驟217、一蓋子附接步驟219、一雷射標記步驟221、以及一球格陣列(BGA)附接步驟223。
該膏印刷步驟201可包括非導電膏的施加以協助晶粒至該 封裝基板之後續的熱壓縮接合。待被接合的晶粒可包括一中介層晶粒或是一有功能的晶粒，其例如可包括數位信號處理器(DSP)、網路處理器、電源管理單元、音訊處理器、RF電路、無線基頻系統單晶片(SoC)處理器、感測器、以及特殊應用積體電路。
該助焊劑噴射步驟203可包括導電表面在該封裝基板上的 製備，以用於後續的導電的接合。該助焊劑製程可包括一表面清洗步驟，並且可移除在待被接合的表面上之過多的氧化層。例如，在該封裝基板上的墊可被加助焊劑，以用於和該中介層晶粒上的背面凸塊之後續的接合、或是用於在一有功能的晶粒上的微凸塊。此外，在該封裝基板上的接合墊可加以製備，以用於被動元件之後續的安裝。
在該被動元件安裝步驟205中，例如是相關圖1A及1B所 敘述的被動元件105之被動元件可被安裝到該封裝基板。在該熱壓縮接合中介層步驟207中，一中介層晶粒可以利用一熱壓縮接合製程而被接合至該封裝基板。該先前施加的非導電膏實際上可以藉由導電表面的壓縮來加以位移。儘管一熱壓縮接合製程被展示在圖2中，但是一質量回焊製程亦 可被使用於接合該中介層或是有功能的晶粒至該封裝基板。此製程的例子被展示在圖3及7中。
在該助焊劑清洗步驟209中，殘留的助焊劑例如可在一溶劑 及/或去離子(DI)水清洗中加以移除，接著是在一升高的溫度下之一乾燥製程。此可以在該底膠填充/固化步驟211中製備用於一毛細管潛流(underflow)製程之接合的結構。在此製程中，一種潛流材料可被注入在該接合的晶粒的邊緣處，並且在一升高的溫度下之毛細管作用可以將該材料均勻地散佈在該接合的晶粒之下，此係在該電性接合的周圍提供一保護介電層。一旦該毛細管作用已經散佈該底膠填充材料後，其可以在一段延長的時間於一升高的溫度下被固化。
在該毛細管底膠填充及固化製程之後，該助焊劑浸漬步驟 213可加以執行，其可以在該接合的中介層或是有功能的晶粒上的該接合區域加助焊劑，以用於後續的接合至其它晶粒上的微凸塊。該助焊劑材料可提供一用於該接合表面的清洗機構，並且可以從該金屬移除過多的氧化層。
一頂端晶粒接著可在一熱壓縮頂端晶粒步驟215中被接合 至該結構。該頂端晶粒可被接合至該先前接合的中介層晶粒或是一先前接合的有功能的晶粒。該頂端晶粒可以在一升高的溫度下被壓抵該中介層晶粒/封裝基板，以提供一藉由該接合的接點所形成的電性及機械的支撐。如同該熱壓縮接合中介層步驟207，該熱壓縮接合頂端晶粒步驟215例如可以替代地包括一如同在圖3中所繪的質量回焊接合製程。
另一底膠填充及固化製程可在該底膠填充/固化步驟217中加以執行，但是為用於該頂端晶粒，該步驟可包括一種底膠填充材料的注 入，該底膠填充材料可以經由在一升高的溫度下的毛細管作用而再次散佈在該頂端晶粒之下。類似地，該底膠填充材料接著可以在一段例如長達幾個小時之延長的時間，在一升高的溫度下被固化。
該製程可以繼續以該蓋子附接步驟219，類似於例如在圖1A 中所示的蓋子113，若為所要的話，其可以在該接合的晶粒、中介層及封裝基板之上設置一保護及氣密密封。此接著可以是一雷射標記步驟221，其中可以在該蓋子及/或封裝基板中做成識別的標記。最後，一球格陣列(BGA)附接步驟223可加以執行以安裝例如是焊料球111的焊料球至該封裝基板，以用於後續的接合至一電路板或是其它支承結構。該BGA可受到一回焊製程，以確保良好的電性及機械的接觸至該封裝基板上的墊。
圖3是描繪根據本發明的一實施例的用在一封裝中的晶粒 之接合選項之概要圖。參照圖3，其係展示有四種包括質量回焊及熱壓縮接合步驟的製程變化。每一種製程係描繪一可包括一中介層晶粒至一封裝基板的第一晶粒接合製程、以及一包括一晶粒至該先前接合的中介層晶粒之第二接合。
該第一製程係包括一質量回焊/質量回焊製程，其中第一步 驟是一中介層晶粒至基板附接步驟301A，接著是一回焊步驟303A、以及底膠填充步驟305A、一晶粒至中介層附接步驟307A、一第二回焊步驟303B、一第二底膠填充步驟305B、以及一最後的步驟309。
在此範例情節中，該中介層晶粒至基板附接步驟301A以及 該晶粒至中介層附接步驟307A可包括質量回焊接合製程(例如，分別在步驟303A及303B)。
第二製程流程係包括一熱壓縮第一接合以及一質量回焊第 二接合。該製程因此包括一熱壓縮/非導電膏/毛細管底膠填充中介層晶粒至基板接合步驟301B、一晶粒至中介層附接步驟307A、接著是該回焊步驟303B、底膠填充步驟305B以及最終的測試309。
第三製程流程係包括兩個熱壓縮接合製程，因而該製程係包 括該熱壓縮/非導電膏/毛細管底膠填充中介層晶粒至基板接合步驟301B、一熱壓縮/非導電膏/毛細管底膠填充晶粒至中介層接合步驟307B、以及最終的測試步驟309。
最後，第四製程流程係包括一質量回焊第一接合以及一熱壓 縮第二接合，因而該製程係包括該中介層晶粒至基板附接步驟301A、回焊步驟303A、底膠填充步驟305A、熱壓縮/非導電膏/毛細管底膠填充晶粒至中介層接合步驟307B、以及最終的測試步驟309。
在圖3中所示的製程流程係描繪質量回焊以及熱壓縮的任 意組合可被利用來在該封裝中接合各種的晶粒。熱壓縮接合技術在40微米的間距或更小下可能是有利的，並且白凸塊，亦即高介電係數的介電層脫層可利用熱壓縮接合而被消除。此外，平坦度可以在熱壓縮接合下加以改善，此係產生較少的因為過大的間隙所造成之開路連接。
圖4A-4C係描繪根據本發明的一範例實施例的一種用於一 中介層至封裝基板第一接合的製程。參照圖4A，其係展示有該封裝基板103以及中介層107。例如，該封裝基板103以及該中介層107可以是如先前所述者，其中該封裝基板103可包括該墊119，並且該中介層107可包括該TSV 115以及背面凸塊117。
該中介層晶粒107可以利用一質量回焊製程或是一具有非 導電膏的熱壓縮製程而被接合至該封裝基板103。該質量回焊製程可包括一助焊劑浸漬以製備用於適當的接合之金屬表面。該熱壓縮接合製程可包括非導電膏或膜之選擇性的施加，以協助該接合製程。此外，一毛細管底膠填充製程可以填入在該中介層107以及封裝基板103之間的區域中的背面凸塊117之間的空隙，例如由該底膠填充401A所描繪者。
在圖4B中，該晶粒101可以利用一質量回焊製程或是一具 有非導電膏的熱壓縮製程而被接合至該中介層晶粒107。如同該中介層晶粒107，一毛細管底膠填充製程可以填入在該晶粒101以及該中介層晶粒107之間的區域中的微凸塊109之間的空隙，例如由在圖4C中所示的底膠填充401B所描繪者。
儘管兩個晶粒101至該中介層晶粒107的耦接被描繪在圖 4A-4C中，但是本發明並不一定如此限制的。於是，任意數目的晶粒都可被接合至該中介層107，此例如是由可利用的空間及功率與熱的需求來決定的。再者，晶粒可以堆疊在該中介層晶粒107上，即例如在圖1B中所繪者。
最後，該焊料球111可被設置在該封裝基板103上的該墊 119上。一助焊劑製程可被利用以製備該焊料球111及墊119。該焊料球111在設置後可受到一回焊製程，以完成至該墊119的低電阻及機械式可靠的接點。
圖5是描繪根據本發明的一範例實施例的一種中介層製程 之流程圖。參照圖5，一進入的中介層晶圓可以前進至前側墊步驟501，其中接觸墊可被沉積在該中介層晶圓的正面側上。在一範例情節中，該前側 墊可包括鎳/鈀/金。
該中介層晶圓接著可以前進至該晶圓支承步驟503，其中該 晶圓可以利用例如是一黏著層而被接合到一支承基板。在一範例情節中，該支承結構例如可包括一具有一用於黏貼該中介層晶圓的黏著層之像是矽基板的剛性基板。具有接觸墊的前表面可被黏貼到該晶圓支承件，以容許處理該背表面。此支承件可容許例如是該中介層的薄化之後續的處理步驟，而不造成災難性的物理損壞。
在該薄化的步驟505中，該中介層晶圓可被薄化而下降到一 露出在該基板中的TSV之厚度。該薄化可包括一化學機械的拋光(CMP)製程，以用於移除在該中介層的背表面之材料。
該薄化步驟505之後可以是背面凸塊步驟507，其中金屬凸 塊可附接在該露出的TSV以致能至該背表面的電性接觸。該背面凸塊例如可被利用來將該中介層接合至一封裝基板。該背面凸塊可受到一回焊製程，以確保適當的電性及機械的接合至該中介層。
在該背面凸塊已經施加之後，該中介層可以在脫黏步驟509 中從該晶圓支承件加以移除。此可包括一用於移除該黏著層的熱升溫(thermal ramp)且/或可包括一用於移除該黏著劑的溶劑步驟。最後，該中介層可前進至組裝步驟511，其中該中介層可被單一化並且整合到一例如在圖1A-4C中所示的封裝內。
圖6A及6B係描繪在根據本發明的一範例實施例的一種中 介層製程中之最初的步驟。參照圖6A，其係展示有一中介層610(例如，一中介層晶圓)以及一支承結構603。該支承結構603可包括一種多層的結構。 在一範例情節中，該支承結構603例如可包括一像是矽基板的剛性基板，其具有一用於黏貼該中介層610至該支承結構603的黏著層。
該中介層610在薄化之前可包括一具有前側墊601之厚的基 板，該前側墊601可被利用作為用於在處理後將會耦接至該中介層610的半導體晶粒的接觸墊。為了便於例如是該前側墊601的沉積之操作及處理，在此階段的中介層610可以是比如同在圖1A-4C中整合的中介層107的厚度更厚。該中介層610可包括部分延伸穿過該厚的基板之TSV 115，其中該TSV 115將會在該中介層晶圓610之後續的薄化後被露出。該中介層610亦可包括一用於耦接該TSV 115至適當的前側墊601之金屬互連層605。
圖6B係描繪被黏貼到該中介層晶圓610的支承結構603以 及後續的薄化方向。該中介層610例如可利用一CMP製程而被薄化，並且可被薄化以露出該TSV 115。
圖6C-6D係描繪在根據本發明的一範例實施例的一種中介 層製程中之最後的步驟。參照圖6C，其係展示有帶有該被黏貼的支承結構603之薄化後的中介層610。在該TSV 115被露出下，金屬凸塊可附接在該露出的TSV 115的表面，此係產生可被利用以耦接該中介層610至一封裝基板的背面凸塊607。
在該背面凸塊607被附接之後，該支承結構603例如可透過 一加熱製程或是一溶劑製程而被移除。該所產生的結構可包括一接著可被切割成為個別的包括晶粒之中介層的中介層610，例如該中介層107。
圖7是描繪根據本發明的一範例實施例的一堆疊的晶粒至封裝基板製程之流程圖。參照圖7，在助焊劑浸漬步驟701中，一封裝基板 可被置放在一助焊劑浸漬中，以在一半導體晶粒(例如，一電子裝置或是有功能的晶粒、一中介層晶粒等等)上製備用於和例如是C4微凸塊的金屬凸塊接合的金屬接觸表面。
在質量回焊底部晶粒步驟703中，一第一晶粒可利用一質量 回焊製程而被接合至該封裝基板。儘管一質量回焊製程被展示用於附接該底部晶粒，但是本發明並不一定如此限制的。於是，其它的接合技術亦可被利用，例如一熱壓縮製程。
在助焊劑清洗步驟705中，一清洗製程可被執行在該接合的 晶粒及封裝基板上，以移除任何剩餘的助焊劑，接著是一底膠填充/固化步驟707，其中一種底膠填充材料可被設置在該接合的晶粒以及該封裝基板之間的空間內。該底膠填充材料例如可在一毛細管作用下填入該容積內。一旦該材料被注入到該容積之中，其可以為了硬化而在一升高的溫度下被固化。
一旦該底膠填充材料被固化後，一或多個頂端晶粒可在該熱 壓縮頂端晶粒及非導電膏步驟711中被接合至該底部晶粒。在此步驟中，一種非導電膏可被設置在該底部晶粒的頂表面上，以用於後續接合一或多個頂端晶粒。一種範例結構可包括一邏輯晶粒作為該底部晶粒以及一或多個記憶體晶粒作為該頂端晶粒。
在該固化步驟713中，該非導電膏可在一升高的溫度下被固 化，此係確保該頂端晶粒至該底部晶粒之可靠的機械式接合。此接著可以是包覆成型步驟715，其中一種模製材料可被設置在該接合的結構之上，以產生一模製封裝。該模製材料可以提供例如該晶粒及基板封裝的囊封，並 且可保護該電路免於外部的應激源(stressor)。
在該熱介面材料步驟717中，一種具有良好導熱度的材料可 被設置在該頂端晶粒之露出的頂表面上。此可以利用一導熱層來將熱從該接合的晶粒傳導離開至一後續附接的散熱器，以致能用於該接合的晶粒之散熱。在其中該模製材料在包覆成型步驟715後剩餘在該頂端晶粒的頂表面上的實例中，該模製材料可以在一研磨步驟中加以移除。
此接著可以是一雷射標記步驟719，其中識別標記可被置放 在該模製封裝上，接著是球格陣列(BGA)附接步驟721，其中導電球可以附接至該封裝基板的底表面。例如，該BGA接著可被利用來將該整個封裝附接至一電路板。
圖8A及8B係描繪在根據本發明的一範例實施例的一有功 能的晶粒至封裝基板組裝製程中之最初的步驟。參照圖8A，其係展示有一晶粒801A以及該封裝基板103。該封裝基板103例如可以是如先前所述者，並且可包括用於焊料球的後續接合之背面墊119。
例如，該晶粒801A可包括像是數位信號處理器(DSP)、網路 處理器、電源管理單元、音訊處理器、RF電路、無線基頻系統單晶片(SoC)處理器、感測器、以及特殊應用積體電路之電路。再者，該晶粒801A可包括用於做成電性接觸至該封裝基板103的微凸塊109。該晶粒801A可利用一質量回焊製程或是一熱壓縮及非導電膏接合製程而被接合至該封裝基板。
在該接合製程之後，一毛細管底膠填充製程可加以執行，以利用一後續的固化製程來填入在該晶粒801A以及該封裝基板103之間的容 積內。當加以沉積或是設置時，該底膠填充材料803A例如可包括一膜、膏、b階段膜、或是一液體。該所產生的結構被描繪在圖8B中。
圖8C及8D係描繪在根據本發明的一範例實施例的一有功 能的晶粒至封裝基板組裝製程中之最後的步驟。參照圖8C，該晶粒801B可被接合至先前被接合到該封裝基板103的晶粒801A。該晶粒801B可經由一熱壓縮及非導電膏製程而耦接至該晶粒801A。在該晶粒801B上的微凸塊109可耦接至在該晶粒801A上的墊。在另一範例情節中，該晶粒801B可利用一質量回焊製程而耦接至該晶粒801A。
一包覆成型製程可被利用以囊封該接合的結構，此係產生包 覆成型821。包覆成型821可包括一種聚合物，其係經由一壓縮模製製程而被設置在該晶粒801A及801B以及封裝基板103之上及周圍。在一範例情節中，包覆成型可被設置在該晶粒801A及801B的周圍，但是不在頂端上，因而該熱介面材料811可加以沉積在該晶粒801B的頂端上。在另一範例情節中，該包覆成型製程可以產生剩餘在該晶粒801B的頂表面上的包覆成型，但是接著例如透過一研磨或是CMP製程而被移除。
儘管該底膠填充材料803A被展示在圖8C至8E中，該包覆 成型材料本身可被利用作為用於例如是在該中介層103與晶粒801A之間以及在該晶粒801A與801B之間的每個耦接介面的底膠填充材料。在另一範例實施例中，底膠填充材料可被插入為一種液體或膏、設置為一膜或是一b階段膜，並且可以隨著每個晶粒至基板或是晶粒至晶粒的接合完成時依序地被置放、或是可以在所有的電性接合完成之後全部一次來加以完成。
該熱介面材料811可被利用以提供一導熱路徑來讓熱離開 該晶粒801A及801B。如同在圖8E中所繪，一散熱片可被置放在該熱介面材料811之上，以使得熱能夠轉移離開該晶粒801A及801B中的電路。
再者，該焊料球111可被接合至該封裝基板103上的背面墊 119。例如，該焊料球111可以是可運作以提供電互連至外部的裝置及電路，例如至一印刷電路板。應注意的是儘管焊料球被展示在圖8D中，但例如像是微凸塊或銅柱之任何的金屬互連都可被利用。
圖8E係描繪在根據本發明的一範例實施例的晶粒至封裝基 板製程中所產生的組件。如同在圖8E中所示，一基板825可利用該焊料球813而被接合至該中介層103，並且該散熱片823可被置放在該晶粒801B之上而與該熱介面材料811以及包覆成型821接觸。此外，一種熱介面材料可被置放在該散熱片823以及該基板825之間的接觸表面處。
圖9是描繪根據本發明的一範例實施例的一機械式平坦化 裝置之圖。參照圖9，其係展示有一晶舟901、夾子903、複數個晶粒905、一中介層907、以及一基板909。該晶舟901可包括一剛性支承結構，其中一晶粒/中介層組件可藉由該夾子903而被置放且保持在適當的地方。該晶舟901可以是能夠承受例如是超過200℃的高溫。
例如，該中介層907可利用一熱壓縮技術而被接合至該基板 909。類似地，在該複數個晶粒905被置放在該晶舟901中之前，例如可經由一熱壓縮接合技術而被接合至該中介層907。隨著該晶舟901、複數個晶粒905以及中介層907的溫度增高，在該夾子903於該組件的外部邊緣提供一向下的力之下，包括該複數個晶粒905以及中介層907的一組件的曲率可能會變平。隨著該曲率接近零，在橫向的方向上增大的長度可藉由滑動在 該夾子901之下而被容納。此外，該晶舟901可以結合該夾子903之向下的力來提供機械式的支撐，藉此平坦化該組件。
該晶舟901以及夾子903可允許該部分組裝的封裝以正常的 方式加熱，但是當該系統已經變成平坦時，其係抵抗翹曲的正常發展，此係保持該部分組裝的封裝在加熱期間變平，並且接著隨著溫度上升而維持該矽中介層的該平坦度。
圖10是描繪根據本發明的一範例實施例的一真空平坦化裝 置之圖。參照圖10，其係展示有一晶舟1001、複數個晶粒1005、一中介層1007、一基板1008、真空密封環1009、真空通道1011、一閥1013以及一真空源1015。
在一範例情節中，該晶舟1001係包括一真空系統，以將包 括該複數個晶粒1005、中介層1007以及基板1008之部分組裝的封裝變平，該基板1008例如可包括一封裝基板。該真空機械式的系統係允許該部分組裝的封裝以正常的方式加熱，但是當該部分組裝的封裝已經變成平坦時，其係抵抗翹曲的正常發展，在加熱期間保持該部分組裝的封裝處於一變平的形態，並且接著隨著溫度增高而維持該矽中介層1007以及基板1008的該平坦度。
該真空可以在室溫或是稍微升高的溫度下，利用該真空源 1015經由該閥1013以及真空通道1011而被施加，並且可利用該高溫的密封環1009來加以保持，因而該真空機械式的晶舟1001可以行進通過一標準的回焊爐並且仍然維持充分的真空，以維持中介層矽的頂表面之平面性。
圖11A-11E係描繪根據本發明的一範例實施例的用於脫黏 具有大的背面凸塊的晶圓之步驟。參照圖11A，其係展示有一載體晶圓1101、一具有背面凸塊1105的裝置晶圓1103、以及一聚合物層1107。
例如，該裝置晶圓1103可包括一電子裝置(亦即有功能的) 晶圓或是一中介層晶圓，其可包括在脫黏製程中可能易受損壞的大的背面凸塊1105。於是，該聚合物層1107可被施加以在脫黏製程期間保護該背面凸塊1105。例如，該聚合物層1107可包括一種抗蝕材料或是一黏著膜或帶，其可被施加在該裝置晶圓1103的背面凸塊1105之上。
例如利用一真空技術之後續的夾頭附著至該載體晶圓1101 以及該聚合物層1107的頂表面被展示在圖11B中。該頂端夾頭1109A可被移動在一橫向的方向上，同時該底部夾頭1109B可被移動在相反的方向上，以分開的該載體晶圓1101與該裝置晶圓1103。該聚合物層1107可以致能一適當的真空密封至該表面，其中當真空直接施加至該背面凸塊1105時，其可能是一劣質的密封。
圖11C係展示從該載體晶圓1101脫黏後之產生的結構。當 該載體晶圓1101仍然附接至該頂端夾頭1109A時，從該載體晶圓1101剩下的任何黏著劑殘留物都可在一清洗製程中加以移除。
例如在圖11D中所示，在該背面凸塊1105面朝上的情形下， 該被清洗後的結構接著可被黏貼至一膜框架1111。該聚合物層1107接著可以用化學或是熱的方式來加以移除，而接著是一表面清洗，此係產生例如在圖11E中所示之接合的晶圓1103。
圖12是描繪根據本發明的一實施例的利用一圖案化的底膠填充層的晶粒至晶粒的接合之圖。參照圖12，其係展示有一具有微凸塊1203 的頂端晶粒1201以及一包括接觸墊1207及一底膠填充層1209的底部晶粒1205。
在一範例情節中，該微凸塊1203例如可包括銅柱，並且可 對應於在該底部晶粒1205中的接觸墊1207。該底膠填充層1209可包括一種施加至該底部晶粒1205的頂表面之聚合物，而下一層級的晶粒，亦即該頂端晶粒1201將會接合到該頂表面。該聚合物可包括一再保護或是預先施加的底膠填充，其將會流動且接合至兩個晶粒表面，此係除去對於後續的底膠填充製程之需求。
再者，該底膠填充層1209可利用微影技術或是雷射剝蝕而 被圖案化，以在該底部晶粒1205中露出適當的接觸墊1207(例如，藉由在該層1209中形成井)。該層1209可包括一膜，其中該開口例如可包括利用雷射剝蝕或是微影技術所產生的完全深度的凹穴或是部分深度的凹穴。在該部分深度的凹穴中剩餘的材料例如可以有助於該頂端晶粒1201至該底部晶粒1205的接合製程。
該露出的墊可被利用來將該頂端晶粒1201對準到該底部晶 粒1205。該晶粒例如可利用一熱壓縮或是質量回焊技術而被接合。一助焊劑浸漬可被利用以助於焊料從一表面至另一表面的潤濕，並且該底膠填充可“快速固化”並且密封至頂端及底部晶粒表面兩者。再者，該底膠填充可以在該接合製程期間在該微凸塊1203以及接觸墊1207之下到處流動。
在本發明的一範例實施例中，一種用於一具有一晶粒至封裝基板第一接合的半導體裝置封裝之方法及系統被揭示。為了此例子之目的，圖1A-1B的中介層107被稱為一第一晶粒107。就此點而言，本發明的 特點可包括接合一第一晶粒107、801A(例如，一半導體晶粒)至一封裝基板103，在該第一晶粒107、801A以及該封裝基板103之間施加一種底膠填充材料401A、401B、803A，以及接合一或多個額外的晶粒101、801B至該第一晶粒107、801A。
該一或多個額外的晶粒101、801B可包括電子裝置。該第一 晶粒107、801A可以是一中介層(如上所論述)或是可包括電子裝置。該第一晶粒107、801A可利用一質量回焊製程303A或是一熱壓縮製程301B而被接合至該封裝基板103。該一或多個額外的晶粒101、801B可利用一質量回焊製程303B或是一熱壓縮製程301B、307B而被接合至該第一晶粒107、801A。該接合的第一晶粒以及該接合的一或多個額外的晶粒可被囊封在一種模製材料821中。該模製材料821可包括一種聚合物。該一或多個額外的晶粒101、801B可包括用於耦接至該第一晶粒107、801A的微凸塊109。
該第一晶粒107、801A可以是一利用一熱壓縮製程而被接合 至該封裝基板103的中介層(如上所論述)。該一或多個額外的晶粒101、801B的接合可包括：附著該一或多個額外的晶粒101、801B至一黏著層；以及接合該黏著的一或多個額外的晶粒101、801B至該第一晶粒107、801A。
該一或多個額外的晶粒101、801B的接合可包括：設置該第 一晶粒107、801A以及該封裝基板在一固定裝置中，該固定裝置係容許該第一晶粒107、801A以及該封裝基板彎曲在一方向上，而不是彎曲在一相反的方向上；以及透過一回焊製程來處理該第一晶粒107、801A、封裝基板以及一或多個額外的晶粒101、801B。
在該晶粒107、801A至該封裝基板的接合之前：薄化一第一 基板610以露出在該第一晶粒107、801A中的直通矽晶穿孔115，該第一基板610係包括該第一晶粒107、801A並且被接合到一支承結構603；以及從該支承結構603移除該第一中介層610。該第一基板從該支承結構603的移除可包括：在該第一裝置晶圓1103上的背面凸塊1105之上形成一保護的聚合物層1107；附接一第一夾頭1109A至該聚合物層1107；附接一第二夾頭1109B至該載體晶圓1101；以及在該附接的第一夾頭1109A以及該附接的第二夾頭1109B之間造成相對的運動。
該接合的第一晶粒107、801以及該接合的一或多個額外的 晶粒101、801B可被囊封在一種模製材料821中。該一或多個額外的晶粒101、801B、1201可包括用於耦接至該第一晶粒107、801、1205的微凸塊109、1203，其中該接合係包括：定位該微凸塊1203在一設置於該第一晶粒107、801A、1205上的層1209中之個別的井內；以及接合該微凸塊1203至該第一晶粒107、801A。
儘管本發明已經參考某些實施例來加以敘述，但是將會被熟 習此項技術者所理解的是可以完成各種的改變並且可以用等同物來加以取代，而不脫離本發明的範疇。此外，可以對於本發明的教示完成許多修改以適配一特定的情況或材料，而不脫離其範疇。因此，所欲的是本發明並不受限於該揭露的特定實施例，而是本發明將會包含所有落在所附的申請專利範圍的範疇內之實施例。
103‧‧‧封裝基板
107‧‧‧中介層
115‧‧‧直通矽晶穿孔(TSV)
117‧‧‧背面凸塊
119‧‧‧墊

Claims (23)

  1. 一種用於半導體封裝之方法，該方法係包括：接合一第一半導體晶粒至一封裝基板，其中該第一半導體晶粒未包含電子裝置；在該第一半導體晶粒以及該封裝基板之間施加一底膠填充材料；以及接合一或多個額外的晶粒至該第一半導體晶粒，其中該一或多個額外的晶粒包括電子裝置。
  2. 根據申請專利範圍第1項之方法，其中：該第一半導體晶粒是一中介層晶粒；以及接合該第一半導體晶粒至該封裝基板包括利用一熱壓縮製程來接合該中介層晶粒至該封裝基板。
  3. 根據申請專利範圍第1項之方法，其係包括利用一熱壓縮製程來接合該一或多個額外的晶粒至該第一晶粒。
  4. 根據申請專利範圍第1項之方法，其中該一或多個額外的晶粒的接合包括：將該一或多個額外的晶粒黏著至一黏著層；以及接合黏著的該一或多個額外的晶粒至該第一半導體晶粒。
  5. 根據申請專利範圍第4項之方法，其中該一或多個額外的晶粒的接合包括：將複數個額外的晶粒黏著至一黏著層；以及接合黏著的該複數個額外的晶粒至該第一半導體晶粒。
  6. 根據申請專利範圍第1項之方法，其中該一或多個額外的晶粒的接 合包括：設置至少該第一半導體晶粒以及該封裝基板在一固定裝置中，該固定裝置容許該第一半導體晶粒以及該封裝基板彎曲在一方向上，而不是彎曲在一相反的方向上；以及透過一回焊製程來處理該第一半導體晶粒、該封裝基板以及該一或多個額外的晶粒，其中該固定裝置允許該封裝基板在加熱製程的第一部分期間不翹曲且在該加熱製程的第二部分期間保持平坦。
  7. 根據申請專利範圍第6項之方法，其中該固定裝置容許該封裝基板移動在一第一方向上，但是抵抗該封裝基板在垂直於該第一方向的一第二方向上的移動。
  8. 根據申請專利範圍第7項之方法，其中該固定裝置包括機械式的夾子，其覆蓋該封裝基板的頂側且容許該封裝基板移動在該第一方向上，但是抵抗該封裝基板在該第二方向上的移動。
  9. 根據申請專利範圍第7項之方法，其中該固定裝置包括真空的特點，其容許該封裝基板移動在該第一方向上，但是抵抗該封裝基板在該第二方向上的移動。
  10. 根據申請專利範圍第1項之方法，其係在該第一半導體晶粒至該封裝基板的接合之前包括：薄化包括該第一半導體晶粒並且被接合到一支承基板的一第一半導體晶圓，以露出在該第一半導體晶粒中的直通矽晶穿孔；以及從該支承基板移除該第一半導體晶圓。
  11. 根據申請專利範圍第10項之方法，其中從該支承基板移除該第一半導體晶圓包括：在該第一半導體晶圓的背面凸塊之上形成一保護層；附接一第一夾頭至該保護層；附接一第二夾頭至該支承基板；以及在附接的該第一夾頭以及附接的該第二夾頭之間造成相對的運動。
  12. 根據申請專利範圍第11項之方法，其係包括從該保護層脫離該第一夾頭並且移除該保護層。
  13. 根據申請專利範圍第1項之方法，其中該第一半導體晶粒包括電子裝置。
  14. 根據申請專利範圍第1項之方法，其係包括囊封接合的該第一半導體晶粒以及接合的該一或多個額外的晶粒在一模製材料中。
  15. 根據申請專利範圍第1項之方法，其中該一或多個額外的晶粒包括用於耦接至該第一半導體晶粒的微凸塊，並且其中接合該一或多個額外的晶粒至接合的該第一半導體晶粒包括：定位該微凸塊在設置於該第一半導體晶粒上的一層中之個別的井內；以及接合該微凸塊至該第一半導體晶粒。
  16. 根據申請專利範圍第15項之方法，其係包括利用微影及/或雷射剝蝕中的一或多個來在該層中形成該個別的井。
  17. 根據申請專利範圍第16項之方法，其中該井是該層的一完全深度。
  18. 根據申請專利範圍第16項之方法，其中該井是在該層中之部分深 度的井。
  19. 根據申請專利範圍第1項之方法，其中該底膠填充材料被施加為下列的一或多個：一液體、一膏、一積層以及一模製材料。
  20. 一種用於半導體封裝之方法，該方法係包括：在一晶粒至封裝基板第一接合中產生一半導體封裝，該產生包括：利用一熱壓縮製程來接合一中介層晶粒至一封裝基板，其中該中介層晶粒未包含電子裝置；在接合的該中介層晶粒以及該封裝基板之間施加一底膠填充材料；利用一熱壓縮製程來接合一或多個額外的晶粒至接合的該中介層晶粒，其中該一或多個額外的晶粒包括電子裝置；以及在接合的該一或多個額外的晶粒以及接合的該中介層晶粒之間施加一底膠填充材料。
  21. 根據申請專利範圍第20項之方法，其中該一或多個額外的晶粒的接合包括：將該一或多個額外的晶粒黏著至一黏著層；以及將黏著的該一或多個額外的晶粒接合至該中介層晶粒。
  22. 根據申請專利範圍第20項之方法，其中該一或多個額外的晶粒包括用於耦接至該中介層晶粒的微凸塊，並且其中接合該一或多個額外的晶粒至接合的該中介層晶粒包括：定位該微凸塊在設置於該中介層晶粒上的一層中之個別的井內；以及接合該微凸塊至該中介層晶粒。
  23. 一種用於半導體封裝之方法，該方法係包括： 在一晶粒至封裝基板第一接合中產生一半導體封裝，該製程包括：接合一第一半導體晶粒至一封裝基板，其中該第一半導體晶粒未包含電子裝置；利用一質量回焊製程來接合一或多個額外的晶粒至該第一半導體晶粒，其中該一或多個額外的晶粒包括電子裝置；在該第一半導體晶粒以及該封裝基板之間並且在該一或多個額外的晶粒以及該第一半導體晶粒之間施加一底膠填充材料；以及在接合的該第一晶粒以及接合的該一或多個額外的晶粒的周圍設置一模製材料。
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