TWI562322B - Semiconductor device packages - Google Patents

Semiconductor device packages

Info

Publication number
TWI562322B
TWI562322B TW104134721A TW104134721A TWI562322B TW I562322 B TWI562322 B TW I562322B TW 104134721 A TW104134721 A TW 104134721A TW 104134721 A TW104134721 A TW 104134721A TW I562322 B TWI562322 B TW I562322B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
device packages
packages
semiconductor
Prior art date
Application number
TW104134721A
Other languages
English (en)
Other versions
TW201616632A (zh
Inventor
Kuo Hsien Liao
I Chia Lin
Chieh Chen Fu
Cheng Nan Lin
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Publication of TW201616632A publication Critical patent/TW201616632A/zh
Application granted granted Critical
Publication of TWI562322B publication Critical patent/TWI562322B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15158Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
TW104134721A 2014-10-22 2015-10-22 Semiconductor device packages TWI562322B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/521,342 US9269673B1 (en) 2014-10-22 2014-10-22 Semiconductor device packages

Publications (2)

Publication Number Publication Date
TW201616632A TW201616632A (zh) 2016-05-01
TWI562322B true TWI562322B (en) 2016-12-11

Family

ID=55314744

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104134721A TWI562322B (en) 2014-10-22 2015-10-22 Semiconductor device packages

Country Status (3)

Country Link
US (1) US9269673B1 (zh)
CN (2) CN108807304B (zh)
TW (1) TWI562322B (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107535078B (zh) * 2015-05-20 2020-03-31 株式会社村田制作所 高频模块
US9461001B1 (en) 2015-07-22 2016-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same
JP6418605B2 (ja) * 2015-07-31 2018-11-07 東芝メモリ株式会社 半導体装置および半導体装置の製造方法
US10535611B2 (en) 2015-11-20 2020-01-14 Apple Inc. Substrate-less integrated components
US10147685B2 (en) * 2016-03-10 2018-12-04 Apple Inc. System-in-package devices with magnetic shielding
JP6407186B2 (ja) * 2016-03-23 2018-10-17 Tdk株式会社 電子回路パッケージ
US10225964B2 (en) * 2016-03-31 2019-03-05 Apple Inc. Component shielding structures with magnetic shielding
US10242954B2 (en) * 2016-12-01 2019-03-26 Tdk Corporation Electronic circuit package having high composite shielding effect
US20190035744A1 (en) * 2016-03-31 2019-01-31 Tdk Corporation Electronic circuit package using composite magnetic sealing material
US10373916B2 (en) * 2016-07-28 2019-08-06 Universal Scientific Industrial (Shanghai) Co., Ltd. Semiconductor device packages
US9711442B1 (en) 2016-08-24 2017-07-18 Nanya Technology Corporation Semiconductor structure
US10854556B2 (en) * 2016-10-12 2020-12-01 Advanced Semiconductor Engineering Korea, Inc. Semiconductor package device and method of manufacturing the same
TWI668821B (zh) * 2016-10-25 2019-08-11 日商Tdk股份有限公司 電子零件模組及其製造方法
KR101896435B1 (ko) 2016-11-09 2018-09-07 엔트리움 주식회사 전자파차폐용 전자부품 패키지 및 그의 제조방법
JP2018088629A (ja) 2016-11-29 2018-06-07 ソニーセミコンダクタソリューションズ株式会社 高周波モジュール、および通信装置
US10553542B2 (en) * 2017-01-12 2020-02-04 Amkor Technology, Inc. Semiconductor package with EMI shield and fabricating method thereof
US10622318B2 (en) * 2017-04-26 2020-04-14 Advanced Semiconductor Engineering Korea, Inc. Semiconductor package device and method of manufacturing the same
CN107172549A (zh) * 2017-06-06 2017-09-15 广东欧珀移动通信有限公司 电声组件及电子设备
TWI647796B (zh) * 2018-04-09 2019-01-11 矽品精密工業股份有限公司 電子封裝件及其製法
US10438901B1 (en) * 2018-08-21 2019-10-08 Qualcomm Incorporated Integrated circuit package comprising an enhanced electromagnetic shield
US11557489B2 (en) * 2018-08-27 2023-01-17 Intel Corporation Cavity structures in integrated circuit package supports
US10937741B2 (en) 2018-11-16 2021-03-02 STATS ChipPAC Pte. Ltd. Molded laser package with electromagnetic interference shield and method of making
TWI766164B (zh) * 2019-05-28 2022-06-01 力成科技股份有限公司 封裝結構
CN110534502B (zh) * 2019-07-26 2021-12-10 南通通富微电子有限公司 封装结构
US20220270982A1 (en) * 2019-07-26 2022-08-25 Tongfu Microelectronics Co., Ltd. Packaging structure and fabrication method thereof
JP2021125525A (ja) * 2020-02-04 2021-08-30 キオクシア株式会社 半導体パッケージおよびその製造方法
CN114078823A (zh) * 2020-08-17 2022-02-22 江苏长电科技股份有限公司 扇出型封装结构及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350951B1 (en) * 1997-12-29 2002-02-26 Intel Corporation Electric shielding of on-board devices
US8686543B2 (en) * 2011-10-28 2014-04-01 Maxim Integrated Products, Inc. 3D chip package with shielded structures

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2092371C (en) * 1993-03-24 1999-06-29 Boris L. Livshits Integrated circuit packaging
US5294826A (en) * 1993-04-16 1994-03-15 Northern Telecom Limited Integrated circuit package and assembly thereof for thermal and EMI management
US5639989A (en) * 1994-04-19 1997-06-17 Motorola Inc. Shielded electronic component assembly and method for making the same
KR100654114B1 (ko) * 1998-10-30 2006-12-05 스미또모 가가꾸 가부시끼가이샤 전자파 차단판
US6872993B1 (en) * 1999-05-25 2005-03-29 Micron Technology, Inc. Thin film memory device having local and external magnetic shielding
US20050184304A1 (en) * 2004-02-25 2005-08-25 Gupta Pavan O. Large cavity wafer-level package for MEMS
US7148531B2 (en) * 2004-04-29 2006-12-12 Nve Corporation Magnetoresistive memory SOI cell
US7183617B2 (en) * 2005-02-17 2007-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Magnetic shielding for magnetically sensitive semiconductor devices
US7315248B2 (en) * 2005-05-13 2008-01-01 3M Innovative Properties Company Radio frequency identification tags for use on metal or other conductive objects
US7451539B2 (en) 2005-08-08 2008-11-18 Rf Micro Devices, Inc. Method of making a conformal electromagnetic interference shield
US8062930B1 (en) 2005-08-08 2011-11-22 Rf Micro Devices, Inc. Sub-module conformal electromagnetic interference shield
TWI328408B (en) * 2006-01-12 2010-08-01 Au Optronics Corp Dual emission display
US8124425B2 (en) * 2007-02-27 2012-02-28 Renesas Electronics Corporation Method for manufacturing magnetic memory chip device
US8133529B2 (en) * 2007-09-10 2012-03-13 Enpirion, Inc. Method of forming a micromagnetic device
US7943510B2 (en) * 2007-09-10 2011-05-17 Enpirion, Inc. Methods of processing a substrate and forming a micromagnetic device
TWI358116B (en) * 2008-02-05 2012-02-11 Advanced Semiconductor Eng Packaging structure and packaging method thereof
US8247888B2 (en) * 2009-04-28 2012-08-21 Dai Nippon Printing Co., Ltd. Semiconductor device and method for manufacturing metallic shielding plate
CN101930969B (zh) * 2009-06-22 2012-06-13 日月光半导体制造股份有限公司 具有电磁干扰防护罩的半导体封装件
KR101855294B1 (ko) 2010-06-10 2018-05-08 삼성전자주식회사 반도체 패키지
KR101678055B1 (ko) * 2010-06-15 2016-11-22 삼성전자 주식회사 전자파 간섭 제거 장치 및 이를 포함하는 반도체 패키지
US8836449B2 (en) * 2010-08-27 2014-09-16 Wei Pang Vertically integrated module in a wafer level package
CN102110674B (zh) * 2010-12-31 2012-07-04 日月光半导体制造股份有限公司 半导体封装件
JP2012151326A (ja) 2011-01-20 2012-08-09 Toshiba Corp 半導体装置の製造方法、半導体装置及び電子部品のシールド方法
US8268677B1 (en) 2011-03-08 2012-09-18 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer over semiconductor die mounted to TSV interposer
TWI460843B (zh) 2011-03-23 2014-11-11 Universal Scient Ind Shanghai 電磁屏蔽結構及其製作方法
CN103022011B (zh) * 2011-09-23 2015-10-07 讯芯电子科技(中山)有限公司 半导体封装结构及其制造方法
JP5829562B2 (ja) * 2012-03-28 2015-12-09 ルネサスエレクトロニクス株式会社 半導体装置
KR102161173B1 (ko) * 2013-08-29 2020-09-29 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
TW201519400A (zh) * 2013-11-06 2015-05-16 矽品精密工業股份有限公司 半導體封裝件

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350951B1 (en) * 1997-12-29 2002-02-26 Intel Corporation Electric shielding of on-board devices
US8686543B2 (en) * 2011-10-28 2014-04-01 Maxim Integrated Products, Inc. 3D chip package with shielded structures

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Publication number Publication date
CN108807304B (zh) 2021-02-12
CN108807304A (zh) 2018-11-13
TW201616632A (zh) 2016-05-01
CN105552061A (zh) 2016-05-04
US9269673B1 (en) 2016-02-23
CN105552061B (zh) 2018-07-20

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