TW201519400A - 半導體封裝件 - Google Patents

半導體封裝件 Download PDF

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TW201519400A
TW201519400A TW102140245A TW102140245A TW201519400A TW 201519400 A TW201519400 A TW 201519400A TW 102140245 A TW102140245 A TW 102140245A TW 102140245 A TW102140245 A TW 102140245A TW 201519400 A TW201519400 A TW 201519400A
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shielding
layers
semiconductor package
layer
package
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TW102140245A
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邱志賢
陳嘉揚
蔡宗賢
朱恆正
江政育
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矽品精密工業股份有限公司
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Priority to TW102140245A priority Critical patent/TW201519400A/zh
Priority to CN201310571477.0A priority patent/CN104637923A/zh
Priority to US14/133,842 priority patent/US20150123251A1/en
Publication of TW201519400A publication Critical patent/TW201519400A/zh

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    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract

一種半導體封裝件，係包括：具有至少一半導體元件之封裝結構、相互堆疊設於該封裝結構上之至少三屏蔽層，且於連續排設之任三該屏蔽層中，位於中間之該屏蔽層之導電率係小於位於兩側之該屏蔽層之導電率，以藉複數屏蔽層衰減電磁干擾，而增加屏蔽效能。

Description

半導體封裝件
本發明係關於一種半導體封裝件，更詳言之，本發明係關於一種具屏蔽結構之半導體封裝件。
由於電子產業的蓬勃發展，大部份的電子產品均朝向小型化及高速化的目標發展，尤其是通訊產業的發展已普遍運用整合於各類電子產品，例如行動電話(Cell phone)、膝上型電腦(laptop)等。然而，上述之電子產品需使用高頻的射頻晶片，且射頻晶片可能相鄰設置數位積體電路、數位訊號處理器(DSP,Digital Signal Processor)或基頻晶片(BB,Base Band)，造成電磁干擾的現象，故需進行電磁屏蔽(Electromagnetic Shielding)處理。
如第1圖所示，習知半導體封裝件1係包括一基板10、設於該基板10上之複數晶片11、包覆該些晶片11之封裝膠體12、及遮蓋該封裝膠體12之金屬層13。由於該些晶片11具有高頻的特性，故利用金屬層13以達到電磁屏蔽的效果。
再者，如第1’圖所示，入射波W經由該金屬層13後會形成電磁衰減之穿射波T，而屏蔽效能(Shielding effectiveness,SE)係為一外殼如何衰減電磁場之測量值，且理論上之均質材料之屏蔽效能可由下列公式計算：SE=R+A+B≒R+A
其中，R為反射損失(Reflective loss)，A為吸收損失(absorption loss)，B為二次反射損失(極小，可忽略)，且吸收損失之公式係為：
其中，t是屏蔽層(如該金屬層13)之厚度，f是波頻率(frequency)，μ是相對導磁率，σ r 是相對於銅之導電率(conductivity)。
因此，依上公式，若屏蔽物之材料與波頻率均固定，則吸收損失(absorption loss)可藉由增厚該屏蔽層(如金屬層13)而增加。
然而，因習知半導體封裝件1僅形成單一金屬層13作為屏蔽結構，若藉由增加該金屬層13之厚度，會造成該半導體封裝件1之整體厚度增厚，致使不符合微小化的需求。
另一方面，依上公式，若固定波頻率與該金屬層13之厚度，即不增加該金屬層13之厚度，而改為使用較高的導磁率與導電率的材料，如高滲透性材(higher Permeability material)，以增加屏蔽效能，則會使成本增加。
因此，如何解決習知技術之種種缺失，實為目前各界亟欲解決之技術問題。
為解決上述習知技術之種種問題，本發明遂揭露一種半導體封裝件，係包括：封裝結構，係具有至少一半導體元件；以及屏蔽結構，係包含至少三屏蔽層，其相互堆疊設於該封裝結構上並覆蓋該半導體元件，且於連續排設之任三該屏蔽層中，位於中間之該屏蔽層之導電率係小於位於兩側之該屏蔽層之導電率。
前述之半導體封裝件中，該些屏蔽層之至少二層之材質係為相同。
前述之半導體封裝件中，該些屏蔽層之材質互不相同。
前述之半導體封裝件中，該些屏蔽層之中係至少一層為導體層。
前述之半導體封裝件中，該些屏蔽層係為導體層或非導體層，且該些屏蔽層之中係至少一層為導體層。
前述之半導體封裝件中，該封裝結構復具有包覆該半導體元件之封裝膠體，令該屏蔽結構設於該封裝膠體上。
另外，前述之半導體封裝件中，該屏蔽結構係具有三層、四層、五層、六層或七層屏蔽層等。
由上可知，本發明之半導體封裝件，係藉由複數屏蔽層之設計，以衰減電磁，而增加屏蔽效能。
1,2‧‧‧半導體封裝件
10‧‧‧基板
11‧‧‧晶片
12,22‧‧‧封裝膠體
13‧‧‧金屬層
2a‧‧‧封裝結構
20‧‧‧承載件
21‧‧‧半導體元件
23,23’,23”,53,63‧‧‧屏蔽結構
231‧‧‧第一屏蔽層
232‧‧‧第二屏蔽層
233‧‧‧第三屏蔽層
234‧‧‧第四屏蔽層
235‧‧‧第五屏蔽層
W‧‧‧入射波
T‧‧‧穿射波
第1圖係顯示習知半導體封裝件之剖面示意圖；第1’圖係為第1圖之局部放大圖；第2圖係本發明之半導體封裝件之剖面示意圖； 第2’圖係為第2圖之局部放大圖；以及第3至6圖係為本發明之半導體封裝件之其它實施例之局部放大圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
如第2圖所示，本發明之半導體封裝件2係包括：一封裝結構2a、以及設於該封裝結構2a外表面之一屏蔽結構23。
所述之封裝結構2a係具有一承載件20、設於該承載件20上之一半導體元件21、及包覆該半導體元件21之封裝膠體22。
所述之承載件20係為封裝用之線路板或導線架，其種類繁多，並無特別限制。
所述之半導體元件21係為如主動元件或被動元件之晶片，且該半導體元件21可以覆晶、打線或其它方式電性連接該承載件20，並無特別限制。
所述之屏蔽結構23係包含依序堆疊於該封裝膠體22上之第一屏蔽層231、第二屏蔽層232與一第三屏蔽層233，且於連續排設之該第一、第二與第三屏蔽層231,232,233中，位於中間之第二屏蔽層232之導電率係均小於位於兩側之第一與第三屏蔽層231,233之導電率。
於本實施例中，該第一、第二與第三屏蔽層231,232,233中之至少兩者之材質不相同，例如，三者材質均不相同。
再者，該第一屏蔽層231係為導體層或非導體層，且該第二屏蔽層232係為導體層或非導體層，而該第三屏蔽層233係為導體層或非導體層。有關導體或非導體之材質種類繁多，故不詳加贅述。雖然該第一、第二與第三屏蔽層231,232,233之組合態樣繁多，但該第一、第二與第三屏蔽層231,232,233之中係至少一層為導體層。
又，依屏蔽效能之公式，反射損失(Reflective loss)之公式係為：
其中，Zw是波阻抗，ZS是屏蔽阻抗。
因此，依公式，若Zw遠大於ZS，將得到較大的反射損失R，故如第2’圖所示，本發明之半導體封裝件2藉由多層材質構成之屏蔽結構23係能增加波阻抗，以產生較大的反射損失R，致使入射波W經由該屏蔽結構23後會大幅衰減電磁，亦即幾乎不會形成穿射波，故能有效增加屏蔽效能。
再者，由複數屏蔽層構成之屏蔽結構23因其各層之導磁率與導電率並未對屏蔽效能產生較大之影響，故對於導磁率與導電率的材料之選擇性較多，例如，使用較低的導磁率與導電率的材料，藉以降低成本。
又，本發明之半導體封裝件2中，因該屏蔽結構23之厚度並未對屏蔽效能產生較大之影響，故可依需求調整該屏蔽結構23之厚度，例如，與習知技術相比，於同樣屏蔽效果之情況下，該屏蔽結構23係遠小於習知金屬層之厚度。因此，本發明之半導體封裝件2之整體厚度不僅可有效控制以符合微小化的需求，且能達到所需之屏蔽效果。
於另一實施例中，如第3圖所示，所述之屏蔽結構23’復具有第四屏蔽層234，該第四屏蔽層234係為導體層或非導體層，且該第一至第四屏蔽層231,232,233,234之中係至少一層為導體層。
再者，於連續排設之該第一、第二與第三屏蔽層231,232,233中，位於中間之該第二屏蔽層232之導電率係均小於位於兩側之該第一屏蔽層231之導電率與第三屏蔽層233之導電率；或者，於連續排設之該第二、第三與第 四屏蔽層232,233,234中，位於中間之第三屏蔽層233之導電率係均小於位於兩側之該第二屏蔽層232之導電率與第四屏蔽層234之導電率。
於另一實施例中，如第4圖所示，所述之屏蔽結構23”復具有第五屏蔽層235，該第五屏蔽層235係為導體層或非導體層，且該第一至第五屏蔽層231,232,233,234,235之中係至少一層為導體層。
於本實施例中，於連續排設之該第一、第二與第三屏蔽層231,232,233中，位於中間之該第二屏蔽層232之導電率係均小於位於兩側之該第一屏蔽層231之導電率與第三屏蔽層233之導電率。
或者，於連續排設之該第二、第三與第四屏蔽層232,233,234中，位於中間之第三屏蔽層233之導電率係均小於位於兩側之該第二屏蔽層232之導電率與第四屏蔽層234之導電率。
再者，於連續排設之該第三、第四與第五屏蔽層231,232,233中，位於中間之第四屏蔽層234之導電率係均小於位於兩側之第三屏蔽層233之導電率與第五屏蔽層235之導電率。
又，於連續排設之該第一、第二與第三屏蔽層231,232,233中，位於中間之該第二屏蔽層232之導電率係均小於位於兩側之該第一屏蔽層231之導電率與第三屏蔽層233之導電率，且同時於連續排設之該第三、第四與第五屏蔽層231,232,233中，位於中間之第四屏蔽層234之導 電率係均小於位於兩側之第三屏蔽層233之導電率與第五屏蔽層235之導電率。
於其它實施例中，如第5或6圖所示，該屏蔽結構53,63係具有六層或七層屏蔽層。
綜上所述，本發明之半導體封裝件，主要利用於該封裝結構外表面上形成複數屏蔽層，以增加反射損失，使該屏蔽結構類似電容，且當電磁干擾為直流(DC)或低頻(low frequency)時，該電容的阻抗(impedance)係為無限大，故該半導體封裝件不僅能大幅衰減電磁波之干擾，且能降低成本、及有效控制半導體封裝件之整體厚度。
上述該些實施樣態僅例示性說明本發明之功效，而非用於限制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述該些實施態樣進行修飾與改變。此外，在上述該些實施態樣中之元件的數量僅為例示性說明，亦非用於限制本發明。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
2a‧‧‧封裝結構
20‧‧‧承載件
21‧‧‧半導體元件
22‧‧‧封裝膠體
23‧‧‧屏蔽結構
231‧‧‧第一屏蔽層
232‧‧‧第二屏蔽層
233‧‧‧第三屏蔽層

Claims (11)

  1. 一種半導體封裝件，係包括：封裝結構，係具有至少一半導體元件；以及屏蔽結構，係包含至少三屏蔽層，其相互堆疊設於該封裝結構上並覆蓋該半導體元件，且於連續排設之任三該屏蔽層中，位於中間之該屏蔽層之導電率係小於位於兩側之該屏蔽層之導電率。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該些屏蔽層之至少二層之材質係為相同。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該些屏蔽層之材質互不相同。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該屏蔽層之中係至少一層為導體層。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該些屏蔽層係為導體層或非導體層，且該些屏蔽層之中係至少一層為導體層。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該封裝結構復具有包覆該半導體元件之封裝膠體，令該屏蔽結構設於該封裝膠體上。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該屏蔽結構係具有三層屏蔽層。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中，該屏蔽結構係具有四層屏蔽層。
  9. 如申請專利範圍第1項所述之半導體封裝件，其中， 該屏蔽結構係具有五層屏蔽層。
  10. 如申請專利範圍第1項所述之半導體封裝件，其中，該屏蔽結構係具有六層屏蔽層。
  11. 如申請專利範圍第1項所述之半導體封裝件，其中，該屏蔽結構係具有七層屏蔽層。
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