CN104637923A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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CN104637923A
CN104637923A CN201310571477.0A CN201310571477A CN104637923A CN 104637923 A CN104637923 A CN 104637923A CN 201310571477 A CN201310571477 A CN 201310571477A CN 104637923 A CN104637923 A CN 104637923A
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semiconductor package
package part
conductance
shielding construction
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邱志贤
陈嘉扬
蔡宗贤
朱恒正
江政育
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Siliconware Precision Industries Co Ltd
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Abstract

一种半导体封装件，包括：具有至少一半导体组件的封装结构、相互堆栈设于该封装结构上的至少三屏蔽层，且于连续排设的任三该屏蔽层中，位于中间的该屏蔽层的导电率小于位于两侧的该屏蔽层的导电率，以藉多个屏蔽层衰减电磁干扰，而增加屏蔽效能。

Description

半导体封装件
技术领域
本发明涉及一种半导体封装件，尤指一种具屏蔽结构的半导体封装件。
背景技术
由于电子产业的蓬勃发展，大部份的电子产品均朝向小型化及高速化的目标发展，尤其是通讯产业的发展已普遍运用整合于各类电子产品，例如移动电话(Cell phone)、膝上型电脑(laptop)等。然而，上述的电子产品需使用高频的射频芯片，且射频芯片可能相邻设置数字集成电路、数字讯号处理器(DSP,Digital Signal Processor)或基频芯片(BB,Base Band)，造成电磁干扰的现象，故需进行电磁屏蔽(Electromagnetic Shielding)处理。
如图1所示，现有半导体封装件1包括一基板10、设于该基板10上的多个芯片11、包覆该些芯片11的封装胶体12、及遮盖该封装胶体12的金属层13。由于该些芯片11具有高频的特性，故利用金属层13以达到电磁屏蔽的效果。
此外，如图1’所示，入射波W经由该金属层13后会形成电磁衰减的穿射波T，而屏蔽效能（Shielding effectiveness,SE）为一外壳如何衰减电磁场的测量值，且理论上的均质材料的屏蔽效能可由下列公式计算：
SE=R+A+B≒R+A
其中，R为反射损失(Reflective loss)，A为吸收损失(absorptionloss)，B为二次反射损失（极小，可忽略），且吸收损失的公式为：
A = 8.69 ( t / δ ) = 131.7 t fμ r σ r dB
其中，t是屏蔽层（如该金属层13）的厚度，f是波频率（frequency），μr是相对导磁率，σr是相对于铜的导电率（conductivity）。
因此，依上公式，若屏蔽物的材料与波频率均固定，则吸收损失(absorption loss)可藉由增厚该屏蔽层（如金属层13）而增加。
然而，因现有半导体封装件1仅形成单一金属层13作为屏蔽结构，若藉由增加该金属层13的厚度，会造成该半导体封装件1的整体厚度增厚，致使不符合微小化的需求。
另一方面，依上公式，若固定波频率与该金属层13的厚度，即不增加该金属层13的厚度，而改为使用较高的导磁率与导电率的材料，如高渗透性材（higher Permeability material），以增加屏蔽效能，则会使成本增加。
因此，如何解决现有技术的种种缺失，实为目前各界亟欲解决的技术问题。
发明内容
为解决上述现有技术的种种问题，本发明的目的为揭露一种半导体封装件，能增加屏蔽效能。
本发明的半导体封装件，包括：封装结构，具有至少一半导体组件；以及屏蔽结构，包含至少三屏蔽层，其相互堆栈设于该封装结构上并覆盖该半导体组件，且于连续排设的任三该屏蔽层中，位于中间的该屏蔽层的导电率小于位于两侧的该屏蔽层的导电率。
前述的半导体封装件中，该些屏蔽层的至少二层的材质为相同。
前述的半导体封装件中，该些屏蔽层的材质互不相同。
前述的半导体封装件中，该些屏蔽层的中至少一层为导体层。
前述的半导体封装件中，该些屏蔽层为导体层或非导体层，且该些屏蔽层的中至少一层为导体层。
前述的半导体封装件中，该封装结构还具有包覆该半导体组件的封装胶体，令该屏蔽结构设于该封装胶体上。
另外，前述的半导体封装件中，该屏蔽结构具有三层、四层、五层、六层或七层屏蔽层等。
由上可知，本发明的半导体封装件，藉由多个屏蔽层的设计，以衰减电磁，而增加屏蔽效能。
附图说明
图1为显示现有半导体封装件的剖面示意图；
图1’为图1的局部放大图；
图2为本发明的半导体封装件的剖面示意图；
图2’为图2的局部放大图；以及
图3至图6为本发明的半导体封装件的其它实施例的局部放大图。
符号说明
1,2                 半导体封装件
10                  基板
11                  芯片
12,22               封装胶体
13                  金属层
2a                  封装结构
20                  承载件
21                  半导体组件
23,23’,23”,53,63  屏蔽结构
231                 第一屏蔽层
232                 第二屏蔽层
233                 第三屏蔽层
234                 第四屏蔽层
235                 第五屏蔽层
W                   入射波
T                   穿射波。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如「上」、及「一」等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
如图2所示，本发明的半导体封装件2包括：一封装结构2a、以及设于该封装结构2a外表面的一屏蔽结构23。
所述的封装结构2a具有一承载件20、设于该承载件20上的一半导体组件21、及包覆该半导体组件21的封装胶体22。
所述的承载件20为封装用的线路板或导线架，其种类繁多，并无特别限制。
所述的半导体组件21为如主动组件或被动组件的芯片，且该半导体组件21可以覆晶、打线或其它方式电性连接该承载件20，并无特别限制。
所述的屏蔽结构23包含依序堆栈于该封装胶体22上的第一屏蔽层231、第二屏蔽层232与一第三屏蔽层233，且于连续排设的该第一、第二与第三屏蔽层231,232,233中，位于中间的第二屏蔽层232的导电率均小于位于两侧的第一与第三屏蔽层231,233的导电率。
于本实施例中，该第一、第二与第三屏蔽层231,232,233中的至少两者的材质不相同，例如，三者材质均不相同。
此外，该第一屏蔽层231为导体层或非导体层，且该第二屏蔽层232为导体层或非导体层，而该第三屏蔽层233为导体层或非导体层。有关导体或非导体的材质种类繁多，故不详加赘述。虽然该第一、第二与第三屏蔽层231,232,233的组合态样繁多，但该第一、第二与第三屏蔽层231,232,233的中至少一层为导体层。
又，依屏蔽效能的公式，反射损失(Reflective loss)的公式为：
R = 20 log | Z w | 4 | Z s | dB
其中，Zw是波阻抗，ZS是屏蔽阻抗。
因此，依公式，若Zw远大于ZS，将得到较大的反射损失R，故如图2’所示，本发明的半导体封装件2藉由多层材质构成的屏蔽结构23能增加波阻抗，以产生较大的反射损失R，致使入射波W经由该屏蔽结构23后会大幅衰减电磁，亦即几乎不会形成穿射波，故能有效增加屏蔽效能。
此外，由多个屏蔽层构成的屏蔽结构23因其各层的导磁率与导电率并未对屏蔽效能产生较大的影响，故对于导磁率与导电率的材料的选择性较多，例如，使用较低的导磁率与导电率的材料，藉以降低成本。
又，本发明的半导体封装件2中，因该屏蔽结构23的厚度并未对屏蔽效能产生较大的影响，故可依需求调整该屏蔽结构23的厚度，例如，与现有技术相比，于同样屏蔽效果的情况下，该屏蔽结构23远小于现有金属层的厚度。因此，本发明的半导体封装件2的整体厚度不仅可有效控制以符合微小化的需求，且能达到所需的屏蔽效果。
于另一实施例中，如图3所示，所述的屏蔽结构23’还具有第四屏蔽层234，该第四屏蔽层234为导体层或非导体层，且该第一至第四屏蔽层231,232,233,234之中至少一层为导体层。
此外，于连续排设的该第一、第二与第三屏蔽层231,232,233中，位于中间的该第二屏蔽层232的导电率均小于位于两侧的该第一屏蔽层231的导电率与第三屏蔽层233的导电率；或者，于连续排设的该第二、第三与第四屏蔽层232,233,234中，位于中间的第三屏蔽层233的导电率均小于位于两侧的该第二屏蔽层232的导电率与第四屏蔽层234的导电率。
于另一实施例中，如图4所示，所述的屏蔽结构23”还具有第五屏蔽层235，该第五屏蔽层235为导体层或非导体层，且该第一至第五屏蔽层231,232,233,234,235之中至少一层为导体层。
于本实施例中，于连续排设的该第一、第二与第三屏蔽层231,232,233中，位于中间的该第二屏蔽层232的导电率均小于位于两侧的该第一屏蔽层231的导电率与第三屏蔽层233的导电率。
或者，于连续排设的该第二、第三与第四屏蔽层232,233,234中，位于中间的第三屏蔽层233的导电率均小于位于两侧的该第二屏蔽层232的导电率与第四屏蔽层234的导电率。
此外，于连续排设的该第三、第四与第五屏蔽层231,232,233中，位于中间的第四屏蔽层234的导电率均小于位于两侧的第三屏蔽层233的导电率与第五屏蔽层235的导电率。
又，于连续排设的该第一、第二与第三屏蔽层231,232,233中，位于中间的该第二屏蔽层232的导电率均小于位于两侧的该第一屏蔽层231的导电率与第三屏蔽层233的导电率，且同时于连续排设的该第三、第四与第五屏蔽层231,232,233中，位于中间的第四屏蔽层234的导电率均小于位于两侧的第三屏蔽层233的导电率与第五屏蔽层235的导电率。
于其它实施例中，如图5或图6所示，该屏蔽结构53,63具有六层或七层屏蔽层。综上所述，本发明的半导体封装件，主要利用于该封装结构外表面上形成多个屏蔽层，以增加反射损失，使该屏蔽结构类似电容，且当电磁干扰为直流（DC）或低频（low frequency）时，该电容的阻抗（impedance）为无限大，故该半导体封装件不仅能大幅衰减电磁波的干扰，且能降低成本、及有效控制半导体封装件的整体厚度。
上述该些实施例仅例示性说明本发明的功效，而非用于限制本发明，任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述该些实施例进行修饰与改变。此外，在上述该些实施例中的组件的数量仅为例示性说明，也非用于限制本发明。因此本发明的权利保护范围，应如权利要求书所列。

Claims (11)

1.一种半导体封装件，包括：
封装结构，其具有至少一半导体组件；以及
屏蔽结构，其包含至少三屏蔽层，其相互堆栈设于该封装结构上并覆盖该半导体组件，且于连续排设的任三该屏蔽层中，位于中间的该屏蔽层的导电率小于位于两侧的该屏蔽层的导电率。
2.根据权利要求1所述的半导体封装件，其特征在于，该些屏蔽层的至少二层的材质为相同。
3.根据权利要求1所述的半导体封装件，其特征在于，该些屏蔽层的材质互不相同。
4.根据权利要求1所述的半导体封装件，其特征在于，该屏蔽层之中至少一层为导体层。
5.根据权利要求1所述的半导体封装件，其特征在于，该些屏蔽层为导体层或非导体层，且该些屏蔽层之中为至少一层为导体层。
6.根据权利要求1所述的半导体封装件，其特征在于，该封装结构还具有包覆该半导体组件的封装胶体，令该屏蔽结构设于该封装胶体上。
7.根据权利要求1所述的半导体封装件，其特征在于，该屏蔽结构具有三层屏蔽层。
8.根据权利要求1所述的半导体封装件，其特征在于，该屏蔽结构具有四层屏蔽层。
9.根据权利要求1所述的半导体封装件，其特征在于，该屏蔽结构具有五层屏蔽层。
10.根据权利要求1所述的半导体封装件，其特征在于，该屏蔽结构具有六层屏蔽层。
11.根据权利要求1所述的半导体封装件，其特征在于，该屏蔽结构具有七层屏蔽层。
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