CN201259891Y - 具电磁屏蔽结构的多芯片封装模块 - Google Patents

具电磁屏蔽结构的多芯片封装模块 Download PDF

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CN201259891Y
CN201259891Y CNU2008201124340U CN200820112434U CN201259891Y CN 201259891 Y CN201259891 Y CN 201259891Y CN U2008201124340 U CNU2008201124340 U CN U2008201124340U CN 200820112434 U CN200820112434 U CN 200820112434U CN 201259891 Y CN201259891 Y CN 201259891Y
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encapsulation module
substrate
core encapsulation
armouring structure
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卓恩民
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本实用新型涉及一种具电磁屏蔽结构的多芯片封装模块，包含基板、至少一导电接点、多个芯片、封胶体及电磁屏蔽层，其中基板上设置导电接点及芯片；封胶体密封芯片于基板上，而一电磁屏蔽层利用印刷步骤覆盖于封胶体表面及导电接点上，以隔绝高频的电磁波，再者，电磁屏蔽层取代现有金属盖板，从而减少多芯片模块的尺寸。

Description

具电磁屏蔽结构的多芯片封装模块
技术领域
本实用新型涉及一种多芯片封装模块，特别是一种具电磁屏蔽结构的多芯片封装模块。
背景技术
由于电子产业的蓬勃发展，大部份的电子产品均朝向小型化及高速化的目标发展，尤其是通讯产业的发展已普遍运用整合于各类电子产品，例如移动电话(Cell phone)、膝上型计算机(laptop)等等；然而上述的电子产品需使用高频的射频芯片，且射频芯片可能相邻设置数字集成电路、数字讯号处理器(DSP，Digital Signal Processor)或基频芯片(BB，Base Band)，造成电磁干扰的现象，因此必需进行电磁屏蔽(Electromagnetic Shielding)处理。
举例而言，图1所示为现有具电磁屏蔽结构的多芯片封装模块的示意图。如图所示，多芯片模块10包含基板12、第一芯片14A、第二芯片14B、第三芯片14C及金属壳16，其中第一芯片14A、第二芯片14B、第三芯片14C分别具有封胶体18设置于基板12上；由于第一芯片14A、第二芯片14B、第三芯片14C具有高频的特性，因此可利用金属壳16设置于第一芯片14A、第二芯片14B、第三芯片14C，以达到电磁屏蔽的效果，但金属壳16会造成整体多芯片模块10的厚度过高不符合小型化的需求。
再者，如图2所示为另一具电磁屏蔽结构的多芯片封装模块示意图，其包括一金属层(metal layer)20及一具有多个穿孔(via hole)22及介电层(dielectric layer)24，介电层24设置于金属层20的上表面，而一芯片26设置于介电层24上，致使芯片26电性连接于金属层20，通过此金属层20的弯折的方式可使芯片26达到高散热及金属屏蔽效果，然而，上述的封装结构需要弯折金属层20并且需要利用黏着剂28连接介电层24与芯片26；再者，上述封装结构的电磁屏蔽结构必须使用弯折及黏着等步骤，才能完成封装结构，不仅会浪费许多生产时间及制作成本，且整体封装结构的高度仍无法降低。
发明内容
为了解决上述问题，本实用新型的目的在于克服现有技术的不足与缺陷，提出一种具电磁屏蔽结构的多芯片封装模块，利用印刷形成电磁屏蔽层，以隔绝高频的电磁波。
为了解决上述问题，本实用新型的另一目的在于，提出一种具电磁屏蔽结构的多芯片封装模块，利用印刷形成电磁屏蔽层取代现有金属盖板，以减少整体多芯片模块的尺寸。
为达上述目的，本实用新型提供一种具电磁屏蔽结构的多芯片封装模块，包含：一基板，其设置至少一导电接点；多个芯片，其设置于该基板上，并与该基板电性连接；一封胶体，其密封该些芯片及该基板上；及一电磁屏蔽层，其覆盖于该封胶体表面及该导电接点上。
本实用新型具有以下有益技术效果：本实用新型提供的具电磁屏蔽结构的多芯片封装模块，利用印刷形成电磁屏蔽层，以隔绝高频的电磁波；再者，电磁屏蔽层利用印刷形成可取代现有金属盖板，以减少整体多芯片模块的尺寸。
附图说明
图1所示为现有具电磁屏蔽结构的多芯片封装模块的示意图；
图2所示为另一现有具电磁屏蔽结构的多芯片封装模块的示意图；
图3所示为根据本实用新型具电磁屏蔽结构的多芯片封装模块示意图；
图4、图5及图6所示为本实用新型一实施例具电磁屏蔽结构的多芯片封装模块的制作顺序图。
图中符号说明
10                   多芯片模块
12、100              基板
14A                  第一芯片
14B                  第二芯片
14C第                三芯片
16                   金属壳
18、130封            胶体
20金                 属层
22                   穿孔
24                   介电层
26、120A、120B、120C 芯片
28                   黏着剂
110                  导电接点
140                  电磁屏蔽层
具体实施方式
请参阅图3所示为根据本实用新型具电磁屏蔽结构的多芯片封装模块，包含基板100、导电接点110、芯片120A、120B及120C、封胶体130及电磁屏蔽层140，其中基板100设置导电接点110；芯片120A、120B及120C设置于基板100上；一封胶体130密封芯片120A、120B及120C于基板100上；及电磁屏蔽层140覆盖于封胶体130表面及导电接点110上，以将电磁波/射频释放至多芯片封装模块的外界，因此，多芯片模块可以通过电磁屏蔽层140以及导电接点110所构成的屏蔽线路，以隔绝及释放高频的电磁波。
接续上述，芯片可为一射频芯片、一数字集成电路、基频芯片或数字讯号处理器(DSP)；另一方面，多芯片模块可为无线信号收发装置，例如，无线网络卡、光电收发模块等。
于一较佳的实例中，电磁屏蔽层通过喷墨印刷的方式连续地或同时地喷涂在多芯片模块上；再着，基板的尺寸大于封胶体塑封的尺寸致使基板有足够的空间容纳导电接点，且导电接点可设置于基板周缘，以容置芯片；另外，电磁屏蔽层可通过印刷机将多芯片模块所需电磁屏蔽部位的数据输入印刷机中，以印刷至多芯片模块上；换言之，使用者可以规划最佳的电磁屏蔽部位，将多芯片模块中产生高频电磁波的芯片或可能被电磁波干扰的芯片进行印刷步骤。
于另一较佳的实例中，电磁屏蔽层可为粒子状的金属材质或为一抗高频电磁的材质：此外，更包含一导线用以连接电磁屏蔽层及导电接点上，以释放高频的电磁波，而芯片设置引线用以电性连接基板及芯片；或基板设置球门阵列，以电性连接芯片。
图4、图5及图6所示为本实用新型一实施例具电磁屏蔽结构的多芯片封装模块的制作顺序图。首先，如图4所示，提供基板100形成至少一导电接点110；接着，如图5所示，提供芯片120A、120B及120C设置于基板100上，并与基板100电性连接；之后，如图6所示，提供一封胶体130密封芯片120A、120B及120C于基板100上，而导电接点110则暴露于封胶体130外；最后，如图3所示，一电磁屏蔽层140通过印刷方式形成于封胶体130及导电接点110上；以及电磁屏蔽层140与导电接点110之间为电性连接，可作为接地之用。
以上所述的实施例仅为说明本实用新型的技术思想及特点，其目的在使本领域技术人员能够了解本实用新型的内容并据以实施，当不能以之限定本实用新型的专利范围，即大凡依本实用新型所揭示的精神所作的均等变化或修饰，仍应涵盖在本实用新型权利要求书的范围内。

Claims (9)

1.一种具电磁屏蔽结构的多芯片封装模块，其特征在于，包含：
一基板，其设置至少一导电接点；
多个芯片，其设置于该基板上，并与该基板电性连接；
一封胶体，其密封该些芯片及该基板上；及
一电磁屏蔽层，其覆盖于该封胶体表面及该导电接点上。
2.如权利要求1所述具电磁屏蔽结构的多芯片封装模块，其特征在于，该些芯片为射频芯片、数字集成电路、基频芯片、数字讯号处理器或以上的组合。
3.如权利要求1所述具电磁屏蔽结构的多芯片封装模块，其特征在于，该多芯片封装模块为一无线网络卡或一光电收发模块。
4.如权利要求1所述具电磁屏蔽结构的多芯片封装模块，其特征在于，该些芯片设置多个引线用以电性连接该基板。
5.如权利要求1所述具电磁屏蔽结构的多芯片封装模块，其特征在于，该基板设置多个球门阵列用以电性连接该些芯片。
6.如权利要求1所述具电磁屏蔽结构的多芯片封装模块，其特征在于，该电磁屏蔽层为一粒子状的金属材质或为一抗高频电磁的材质。
7.如权利要求1所述具电磁屏蔽结构的多芯片封装模块，其特征在于，该基板的尺寸大于该封胶体的尺寸。
8.如权利要求1所述具电磁屏蔽结构的多芯片封装模块，其特征在于，该导电接点暴露于该封胶体外。
9.如权利要求1所述具电磁屏蔽结构的多芯片封装模块，其特征在于，该导电接点设置于该基板周缘。
CNU2008201124340U 2008-04-22 2008-04-22 具电磁屏蔽结构的多芯片封装模块 Expired - Fee Related CN201259891Y (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102340066A (zh) * 2010-07-28 2012-02-01 国碁电子(中山)有限公司 具有天线接口的模组及其制造方法
CN102045993B (zh) * 2009-10-22 2012-08-22 环旭电子股份有限公司 防电磁波干扰的电路模块及其制造方法
CN103354228A (zh) * 2013-07-10 2013-10-16 三星半导体(中国)研究开发有限公司 半导体封装件及其制造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102045993B (zh) * 2009-10-22 2012-08-22 环旭电子股份有限公司 防电磁波干扰的电路模块及其制造方法
CN102340066A (zh) * 2010-07-28 2012-02-01 国碁电子(中山)有限公司 具有天线接口的模组及其制造方法
CN102340066B (zh) * 2010-07-28 2013-12-25 国碁电子(中山)有限公司 具有天线接口的模组及其制造方法
CN103354228A (zh) * 2013-07-10 2013-10-16 三星半导体(中国)研究开发有限公司 半导体封装件及其制造方法

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