TWI525863B - The wafer package structure is packaged using a wafer package structure A module, and a method of manufacturing the wafer package structure - Google Patents
The wafer package structure is packaged using a wafer package structure A module, and a method of manufacturing the wafer package structure Download PDFInfo
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- TWI525863B TWI525863B TW102132667A TW102132667A TWI525863B TW I525863 B TWI525863 B TW I525863B TW 102132667 A TW102132667 A TW 102132667A TW 102132667 A TW102132667 A TW 102132667A TW I525863 B TWI525863 B TW I525863B
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- Prior art keywords
- layer
- insulating layer
- chip package
- wafer
- core plate
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- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000010410 layer Substances 0.000 claims description 187
- 229910000679 solder Inorganic materials 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000011889 copper foil Substances 0.000 claims description 5
- 239000012790 adhesive layer Substances 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims description 2
- 230000004907 flux Effects 0.000 claims description 2
- 239000012943 hotmelt Substances 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 239000000565 sealant Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 239000003292 glue Substances 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 claims 1
- 238000007747 plating Methods 0.000 claims 1
- 239000003566 sealing material Substances 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- 238000007789 sealing Methods 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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Description
本發明與晶片封裝技術有關,尤指一種晶片封裝結構、使用該晶片封裝結構之晶片封裝模組,以及該晶片封裝結構之製造方法。
傳統發光二極體的封裝製程是將發光二極體晶片固定在基板上之後,接著利用打線接合方式將多數條導線(如金線)連接在發光二極體晶片與基板之間,最後再利用一封膠體(如環氧樹脂)將發光二極體晶片進行封裝,但是此一封裝結構會因為晶片的電路導通需求及導線的連接關係而無法有效減少整體厚度,導致在應用於產品時會缺乏競爭力。
為了解決上述問題,中華民國公開第201013858號專利案是將晶粒配置在兩個以上下堆疊方式設置之基板內,再搭配單面或雙面的重新分配層(Redistribution Layer,RDL)來減少整體封裝結構的厚度。然而,此習用專利案的製程相當複雜,實際上所能減少厚度的效果也是有限,並無法真正達到降低製造成本及減少封裝厚度的目的。
本發明之主要目的在於提供一種晶片封裝結
構,其能降低製造成本及減少封裝厚度。
為了達成上述目的,本發明之晶片封裝結構包含有一複合基板、一晶片、一封膠層、一第一線路層、一第二線路層。該複合基板具有一核心板、一導熱絕緣層,以及一貫穿該核心板與該導熱絕緣層之貫孔,該核心板具有一上表面、一背對該上表面之下表面,以及一設於該下表面之下開口,該導熱絕緣層設於該核心板之上表面且具有一頂面,該導熱絕緣層之頂面設有一上開口,該上開口相對於該核心板之下開口;該晶片埋設於該複合基板之導熱絕緣層內且具有一上電極及一下電極,該晶片之上電極對應該導熱絕緣層之上開口,該晶片之下電極固定於該核心板之上表面且對應於該核心板之下開口;該封膠層局部包覆該晶片而曝露出該晶片之上電極;該第一線路層佈設於該導熱絕緣層之頂面、該貫孔內,以及該核心板之下表面,並經由該導熱絕緣層之上開口與該晶片之上電極形成電性連接;該第二線路層佈設於該核心板之下表面,並經由該核心板之下開口與該晶片之下電極形成電性連接。
本發明之次一目的在於提供一種晶片封裝模組,其具有至少兩個前述晶片封裝結構,該兩晶片封裝結構之間相互連接在一起,而且,該兩晶片封裝結構之間設有一切割道,用以供一切割刀進行切割而分離出單一該晶片封裝結構。
本發明之再一目的在於提供一種前述晶片封裝結構之製造方法,包含有下列步驟:將一晶片之一下電極固
定於一核心板之一上導電層;設置一封膠層將該晶片包覆住;壓合一導熱絕緣層於該核心板之一上表面,使該晶片埋設於該導熱絕緣層內;對該導熱絕緣層及該核心板加工出一貫孔,並且對該導熱絕緣層之一頂面及該封膠層之一頂面加工出一上開口,使該晶片之上電極經由該上開口而顯露在外,另外再對該核心板之一下表面加工出一下開口,使該核心板之上導電層經由該下開口而顯露在外;電鍍一導電材料於該導熱絕緣層之頂面、該貫孔內,以及該核心板之下表面,並對該導電材料圖案化,以分別形成一第一線路層及一第二線路層,使該第一、第二線路層分別電性連接該晶片之上電極及該核心板之上導電層。
藉此,本發明之晶片封裝結構使用單一基板即能完成該晶片的封裝製程,相較於傳統打線接合製程或習用專利案之製造方法,本發明之晶片封裝結構更能有效達到簡化製程、降低製造成本及減少封裝體積的目的。
10‧‧‧晶片封裝模組
12‧‧‧晶片封裝結構
14‧‧‧切割道
20‧‧‧複合基板
21‧‧‧核心板
22‧‧‧導熱絕緣層
23‧‧‧貫孔
24‧‧‧絕緣層
25‧‧‧上導電層
26‧‧‧下導電層
27‧‧‧下開口
28‧‧‧上開口
30‧‧‧晶片
32‧‧‧上電極
34‧‧‧下電極
40‧‧‧封膠層
50‧‧‧第一線路層
52‧‧‧第一接點
60‧‧‧第二線路層
62‧‧‧第二接點
80‧‧‧第一防焊層
82‧‧‧第二防焊層
90‧‧‧電漿
第1圖為使用本發明之晶片封裝模組的結構示意圖。
第2圖為本發明之結構示意圖。
第3圖A至B為本發明之製造方法的流程圖。
請參閱第1圖,圖中所示之晶片封裝模組10是由多數個晶片封裝結構12連接而成,相鄰兩個晶片封裝結構12之間具有一切割道14,用以供一切割刀(圖中未示)進行
切割而分離出單一個晶片封裝結構12。請再參閱第2圖,本發明之晶片封裝結構12包含有一複合基板20、一晶片30、一封膠層40、一第一線路層50,以及一第二線路層60。
複合基板20具有一核心板21、一導熱絕緣層22,以及一貫穿核心板21與導熱絕緣層22之貫孔23。核心板21具有一絕緣層24、一上導電層25,以及一下導電層26,上、下導電層25、26分別設於絕緣層24之上、下表面,此外,核心板21具有一下開口27,下開口27貫穿下導電層26及絕緣層24而曝露出上導電層25;導熱絕緣層22設於核心板21之上表面,而且,導熱絕緣層22之頂面設有一上開口28,上開口28相對於核心板21之下開口27,此外,導熱絕緣層22可以是背膠銅箔或軟陶瓷導熱膠膜,其中以背膠銅箔為最佳選擇。
晶片30(在此以發光二極體晶片為例)埋設於複合基板20之導熱絕緣層22內且具有一上電極32(在此為正極)及一下電極34(在此為負極),晶片30之上電極32對應導熱絕緣層22之上開口28,晶片30之下電極34固定於核心板21之上導電層25且對應於核心板21之下開口27。
封膠層40局部包覆晶片30而曝露出晶片30之上電極32,用以避免晶片30在製程中受到腐蝕或產生剝離現象。
第一線路層50佈設於導熱絕緣層22之頂面、貫孔23內,以及核心板21之下表面,並且經由導熱絕緣層22之上開口28與晶片30之上電極32形成電性連接。
第二線路層60佈設於核心板21之下表面,並且經
由核心板21之下開口27電性連接於核心板21之上導電層25,使得第二線路層60與晶片30之下電極34之間經由核心板21之上導電層25形成電性連接。
除了上述結構之外,本發明之晶片封裝結構更提供一第一防焊層80及一第二防焊層82,第一防焊層80佈設於導熱絕緣層22之頂面且包覆第一線路層50,用以對第一線路層50提供絕緣保護效果,第二防焊層82佈設於核心板21之下表面且包覆第一、第二線路層50、60,用以對第一、第二線路層50、60提供絕緣保護效果。
藉此,當在第一線路層50之一第一接點52及第二線路層60之一第二接點62加上正向電壓時,電流會從第一線路層50流至晶片30之上電極32,接著通過晶片30之後再由晶片30之下電極34流向第二線路層60,使晶片30發出光線。
以上為本發明之晶片封裝模組10的詳細結構,以下再就本發明之晶片封裝模組10的製造方法進行說明,如第3圖A至B所示。
A):將晶片30之下電極34固定於核心板21之上導電層25。在此步驟中有兩種固定方式:第一種方式先將晶片30沾附助焊劑之後置於核心板21之上導電層25,再以熱壓熔錫焊接技術將晶片30之下電極34固定於核心板21之上導電層25;第二種方式是先塗佈一焊料於核心板21之上導電層25,再將晶片30置於核心板21之上導電層25後進行回焊,使晶片30之下電極34固定於核心板21之上導電層25。
B):設置封膠層40將晶片30包覆住,接著再將晶片30連同封膠層40進行黑色氧化處理,此時的封膠層40可以避免晶片30在進行黑色氧化處理的過程中受到腐蝕而損壞。
C):壓合導熱絕緣層22於核心板21之上表面,使晶片30埋設於導熱絕緣層22內,此時的封膠層40亦可避免晶片30在壓合導熱絕緣層22的過程中產生剝離現象。
D):使用二氧化碳雷射對導熱絕緣層22及核心板21加工出一貫孔23,並且對導熱絕緣層22之頂面及封膠層40之頂面加工出一上開口28,使晶片30之上電極32經由上開口28而顯露在外,另外再對核心板21之下表面加工出一下開口27,使核心板21之上導電層25經由下開口27而顯露在外。
E):使用電漿90進行雷射鑽孔後的去膠渣處理,接著電鍍一導電材料(以銅為最佳選擇)於導熱絕緣層22之頂面、貫孔23內,以及核心板21之下表面,並對導電材料圖案化,以分別形成一第一線路層50及一第二線路層60,使第一線路層50經由上開口28電性連接晶片30之上電極32,第二線路層60經由下開口27電性連接核心板21之上導電層25。在第一、第二線路層50、60佈設完成之後,再佈設第一防焊層80於導熱絕緣層22之頂面而將第一線路層50包覆住,同時佈設第二防焊層82於核心板21之下表面而將第一、第二線路層50、60包覆住,最後分別對第一、第二線路層50、60形成一化學金層,以作為第一接點52及第二接點62,如此
即完成本發明之晶片封裝結構12的製造。
綜上所陳,本發明之晶片封裝結構12使用單一核心板21與導熱絕緣層22所構成之複合基板20就能完成晶片30的封裝製程,相較於傳統打線接合製程或習用專利案所使用之兩個上下堆疊之基板及重新分配層的佈線設計,本發明之晶片封裝結構12不但具有相對簡單的製程而能有效降低製造成本,同時更能有效減少封裝體積而達到本發明之目的。
12‧‧‧晶片封裝結構
20‧‧‧複合基板
21‧‧‧核心板
22‧‧‧導熱絕緣層
23‧‧‧貫孔
24‧‧‧絕緣層
25‧‧‧上導電層
26‧‧‧下導電層
27‧‧‧下開口
28‧‧‧上開口
30‧‧‧晶片
32‧‧‧上電極
34‧‧‧下電極
40‧‧‧封膠層
50‧‧‧第一線路層
52‧‧‧第一接點
60‧‧‧第二線路層
62‧‧‧第二接點
80‧‧‧第一防焊層
82‧‧‧第二防焊層
Claims (22)
- 一種晶片封裝結構,包含有:一複合基板,具有一核心板、一導熱絕緣層,以及一貫穿該核心板與該導熱絕緣層之貫孔,該核心板具有一上表面、一背對該上表面之下表面,以及一設於該下表面之下開口,該導熱絕緣層設於該核心板之上表面且具有一頂面,該導熱絕緣層之頂面設有一上開口,該上開口相對於該核心板之下開口;一晶片,埋設於該複合基板之導熱絕緣層內且具有一上電極及一下電極,該晶片之上電極對應該導熱絕緣層之上開口,該晶片之下電極固定於該核心板之上表面且對應於該核心板之下開口;一封膠層,局部包覆該晶片而曝露出該晶片之上電極;一第一線路層,佈設於該導熱絕緣層之頂面、該貫孔內,以及該核心板之下表面,並且經由該導熱絕緣層之上開口與該晶片之上電極形成電性連接;以及一第二線路層,佈設於該核心板之下表面且經由該核心板之下開口與該晶片之下電極形成電性連接。
- 如請求項1所述之晶片封裝結構,其中該核心板具有一絕緣層、一上導電層,以及一下導電層,該上、下導電層分別設於該絕緣層之上、下表面,該下開口貫穿該下導電層及該絕緣層而曝露出該上導電層,該上導電層供該晶片之下電極固定且電性連接該第二線路層。
- 如請求項1所述之晶片封裝結構,其中該導熱絕緣層之頂面設有一第一防焊層,該第一防焊層包覆該第一線路層,該核心板之下表面設有一第二防焊層,該第二防焊層包覆該第一、第二線路層。
- 如請求項1所述之晶片封裝結構,其中該第一線路層在該核心板之下表面形成一第一接點,該第二線路層在該核心板之下表面形成一第二接點。
- 如請求項1所述之晶片封裝結構,其中該導熱絕緣層為一背膠銅箔。
- 如請求項1所述之晶片封裝結構,其中該導熱絕緣層為一軟陶瓷導熱膠膜。
- 一種晶片封裝模組,包含有:至少二如請求項1所述之晶片封裝結構,該二晶片封裝結構相互連接在一起,且該二晶片封裝結構之間設有一切割道。
- 如請求項7所述之晶片封裝模組,其中該核心板具有一絕緣層、一上導電層,以及一下導電層,該上、下導電層分別設於該絕緣層之上、下表面,該下開口貫穿該下導電層及該絕緣層而曝露出該上導電層,該上導電層供該晶片之下電極固定且電性連接該第二線路層。
- 如請求項7所述之晶片封裝模組,其中該導熱絕緣層之頂面設有一第一防焊層,該第一防焊層包覆該第一線路層,該核心板之下表面設有一第二防焊層,該第二防焊層包覆該第一、第二線路層。
- 如請求項7所述之晶片封裝模組,其中該第一線路層在該核心板之下表面形成一第一接點,該第二線路層在該核心板之下表面形成一第二接點。
- 如請求項7所述之晶片封裝模組,其中該導熱絕緣層為一背膠銅箔。
- 如請求項7所述之晶片封裝模組,其中該導熱絕緣層為一軟陶瓷導熱膠膜。
- 一種晶片封裝結構之製造方法,包含有下列步驟:A)將一晶片之一下電極固定於一核心板之一上導電層;B)設置一封膠層將該晶片包覆住;C)壓合一導熱絕緣層於該核心板,使該晶片埋設於該導熱絕緣層內;D)對該導熱絕緣層及該核心板加工出一貫孔,並且對該導熱絕緣層之一頂面及該封膠層之一頂面加工一上開口,使該晶片之上電極經由該導熱絕緣層之上開口而顯露在外,另外再對該核心板之一下表面加工出一下開口,使該核心板之上導電層經由該核心板之下開口而顯露在外;以及E)電鍍一導電材料於該導熱絕緣層之頂面、該貫孔內,以及核心板之下表面,並對該導電材料圖案化,以分別形成一第一線路層及一第二線路層,使該第一線路層電性連接該晶片之上電極,該第二線路層電性連接該核心板之上導電層。
- 如請求項13之晶片封裝結構之製造方法,在步驟A)中,先將該晶片沾附助焊劑之後置於該核心板之上導電層,再以熱壓熔錫焊接技術將該晶片之下電極固定於該核心板之上導電層。
- 如請求項13之晶片封裝結構之製造方法,在步驟A)中,先塗佈一焊料於該核心板之上導電層,再將該晶片置於該核心板之上導電層後進行回焊,使該晶片之下電極固定於該核心板之上導電層。
- 如請求項13之晶片封裝結構之製造方法,在步驟B)中,在設置封膠層之後再進行黑色氧化處理。
- 如請求項13之晶片封裝結構之製造方法,在步驟D)中,該貫孔、該上開口,以及該下開口是以雷射加工方式所形成。
- 如請求項17之晶片封裝結構之製造方法,在步驟E)中,在電鍍該導電材料之前,先使用電漿進行雷射鑽孔後的去膠渣處理。
- 如請求項13之晶片封裝結構之製造方法,在步驟E)中,在對該導電材料圖案化之後,佈設一第一防焊層於該導熱絕緣層之頂面且將該第一線路層包覆住,同時佈設一第二防焊層於該核心板之下表面而將該第一、第二線路層包覆住。
- 如請求項19之晶片封裝結構之製造方法,在步驟E)中,在佈設該第一、第二防焊層之後,再分別於該第一、第二線路層形成一化學金層,以作為一第一接點及一第二接點。
- 如請求項13之晶片封裝結構之製造方法,其中該導熱絕緣層為一背膠銅箔。
- 如請求項13之晶片封裝結構之製造方法,其中該導熱絕緣層為一軟陶瓷導熱膠膜。
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