TWI521794B - 包括天線基板之半導體封裝件及其製造方法 - Google Patents

包括天線基板之半導體封裝件及其製造方法 Download PDF

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TWI521794B
TWI521794B TW102140113A TW102140113A TWI521794B TW I521794 B TWI521794 B TW I521794B TW 102140113 A TW102140113 A TW 102140113A TW 102140113 A TW102140113 A TW 102140113A TW I521794 B TWI521794 B TW I521794B
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substrate
layer
antenna
package
ground
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TW102140113A
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TW201436361A (zh
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顏瀚琦
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日月光半導體製造股份有限公司
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Description

包括天線基板之半導體封裝件及其製造方法
本發明是有關於一種半導體封裝件及其製造方法，且特別是有關於一種具有天線基板之半導體封裝件及其製造方法。
無線通訊裝置例如是手機(cell phone)，傳統上包括用以傳送或接收無線射頻(RF)訊號的天線。傳統上，無線通訊裝置包括天線層及通訊模組，其中天線層及通訊模組整合成一晶片。然而，當晶片之一部分，例如是天線部或通訊模組判斷出有缺陷，即使晶片之其它部分可工作，整個晶片也必須報廢。
根據本發明之一實施例，提出一種半導體封裝件。半導體封裝件包括一封裝基板、一半導體裝置、一天線基板及一封裝體。半導體裝置鄰設於封裝基板之上表面。天線基板設置於半導體裝置上，天線基板包括一核心層、一接地層及一天線層。核心層包括一上表面、一下表面及一導電孔(conductive via)。接 地層形成於核心層之下表面。天線層形成於核心層之上表面，且透過導電孔電性連接於接地層。封裝體包覆半導體裝置與天線基板。
根據本發明之另一實施例，提出一種半導體封裝 件。半導體封裝件包括一封裝基板、一晶片、一隔離基板及一封裝體。晶片設置於封裝基板之上表面，且透過一線路電性連接於封裝基板。隔離基板設置於晶片上。天線基板設置於隔離基板上且包括一核心層、一接地層及一天線層。核心層包括一上表面、一下表面及一導電孔。接地層形成於核心層之下表面。天線層形成於核心層之上表面，且透過導電孔電性連接於接地層。封裝體包覆晶片、隔離基板與天線基板。
根據本發明之另一實施例，提出一種半導體封裝件 之製造方法。製造方法包括以下步驟。提供一封裝基板，其中封裝基板包括一上表面，設置一晶片於封裝基板之上表面；提供一天線基板，其中天線基板係一通過測試(verifid)的一工作天線基板，包括一上表面、一下表面及一導電孔，接地層形成於核心層之下表面，而天線層形成於核心層之上表面且透過導電孔電性連接於接地層；設置天線基板於晶片上；以及，形成一封裝體包覆晶片、基板之上表面之一部分與天線基板。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
100、200、300、400‧‧‧半導體封裝件
110‧‧‧封裝基板
110u、120u、141u、371u、470u‧‧‧上表面
110b、141b、371b‧‧‧下表面
110s、130s、140s‧‧‧側表面
111‧‧‧走線
112‧‧‧導電孔
113‧‧‧接墊
115‧‧‧被動元件
120‧‧‧晶片
120b‧‧‧主動面
121f、3711f‧‧‧饋入導電孔
120f‧‧‧饋入層
120g‧‧‧接地層
121g、3711g‧‧‧接地導電孔
130‧‧‧封裝體
140‧‧‧天線基板
141‧‧‧核心層
142‧‧‧天線層
142a‧‧‧天線部
142g‧‧‧接地部
143‧‧‧接地層
143f‧‧‧饋入部
143g‧‧‧接地部
1411‧‧‧導電孔
1411f‧‧‧饋入導電孔
1411g‧‧‧接地導電孔
250g‧‧‧接地線
250f‧‧‧饋入線
360‧‧‧導電焊線
370、470‧‧‧隔離基板
371‧‧‧基材
370f‧‧‧饋入層
370g‧‧‧接地層
T1‧‧‧切割道
第1A圖繪示依照本發明一實施例之半導體封裝件的剖視圖。
第1B圖繪示第1A圖之天線基板之底視圖
第2A圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。
第2B圖繪示第2A圖之天線基板的底視圖。
第3圖繪示依照本發明另一實施例之半導體封裝件之剖視圖。
第4圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。
第5A至5E圖繪示第1A圖之半導體封裝件之製造過程圖。
第6A至6E圖繪示第3圖之半導體封裝件的製造過程圖。
本發明實施例之一整合式半導體封裝件包括一天線部及一 無線通訊裝置之通訊模組部，不會因為其整合而減少良率。以下係揭露這樣的一整合式半導體封裝件。
請參照第1A圖，其繪示依照本發明一實施例之半導體封裝 件的剖視圖。半導體封裝件100包括封裝基板110、被動元件115、晶片120、封裝體130及天線基板140。
封裝基板具有相對之上表面110u與下表面110b、走線 111、導電孔112與數個接墊113。走線111形成於上表面110u，導電孔112從上表面110u延伸到下表面110b，接墊113形成於下表面110b。被動元件115及晶片120可透過導電孔112電性連接於接墊113。此外，封裝基板110例如是多層有機基板或陶瓷基板。
被動元件115設置於封裝基板110之上表面110u，且透過 走線111電性連接於晶片120。被動元件115例如是電阻、電感或電容。
晶片120設置於封裝基板110之上表面110u。晶片120以 朝下方位耦接於封裝基板110之上表面110u，且透過數個焊球電性連接於封裝基板110。這樣的結構稱為覆晶(flip chip)。晶片120可以是主動晶片或SOC(System on Chip)。例如，晶片120可以是一收發器(transceiver)，其傳送無線射頻(radio frequency,RF)訊號給天線基板140且從天線基板140接收RF訊號。
晶片120包括上表面120u及饋入導電孔121f。晶片120係半導體裝置的一部分，其中半導體裝置包括形成於晶片120之上表面120u之饋入層120f。饋入層120f透過饋入導電孔121f電性連接於封裝基板110。半導體裝置更包括形成於晶片120之上表面120u的接地層120g。晶片120包括電性連接接地層120g與封裝基板110之接地導電孔121g。也就是說，形成於晶片120之上表面120u的接地層120g可透過接地導電孔121g電性連接於一接地電位。接地導電孔121g及饋入導電孔121f例如是矽穿孔(through-silicon via,TSV)實現。
封裝體130包覆封裝基板110之上表面110u的一部分、晶片120與天線基板140。封裝體130可包括酚醛基樹脂(Novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其他適當之包覆劑。封裝體130亦可包括適當之填充劑，例如是粉狀之二氧化矽。可利用數種封裝技術形成封裝體130，例如是壓縮成型(compression molding)、注射成型(injection molding)或轉注成型(transfer molding)。
天線基板140設置於半導體裝置上。在實施例中，天線基 板140直接設置於半導體裝置上而無中間層，以縮短一訊號傳輸路徑以及控制電磁干擾(electromagnetic interference,EMI)。藉由控制天線基板140與半導體裝置之間的空間亦可獲得類似的效果，例如是約500微米內、約400微米內、約300微米內、約200微米內、約100微米內或約50微米的空間。
天線基板140包括核心層141、天線層142及接地層143。核心層141包括相對之上表面141u與下表面141b及至少一導電孔1411。於第1A圖之實施例中，至少一導電孔1411包括至少一饋入導電孔1411f及一接地導電孔1411g。核心層141例如是矽基板、有機基板及陶瓷基板。天線層142及接地層143係分別形成於核心層141之上表面141u與下表面141b。
接地層143包括饋入部143f及接地部143g，其中接地部143g與饋入部143f電性隔離。饋入部143f直接接觸饋入層120f，且饋入部143f電性連接於饋入導電孔121f。接地部143g直接接觸接地層120g，且接地部143g透過接地導電孔121g電性連接於接地電位。
由於接地層143之接地部143g電性連接於一接地電位，故接地層143可作為一屏蔽層，以保護接地層143下方的被動元件，避免其天線層142所導致的電磁干擾(EMI)。例如，第1A圖之實施例中，天線基板140之接地層143延伸覆蓋晶片120且覆蓋被動元件115以保護晶片120及被動元件115，避免其受到電磁干擾。另一實施例中，天線基板140可以延伸至封裝體130之一側表面，例如是側表面130s，以與封裝基板110 的整個上表面110u重疊。
天線層142係一圖案化金屬層，其形成於核心層141之上 表面141u。天線層142包括接地部142g及天線部142a，其中天線部142a電性隔離於接地部142g。天線部142a透過饋入導電孔1411f電性連接於接地層143之饋入部143f，且接地部142g透過接地導電孔1411g電性連接於接地層143之接地部143g。
天線基板140轉換電力成為無線電波(radio wave)，反之亦 然。在傳輸方面，晶片120作為一無線傳送器(radio transmitter)，其透過饋入導電孔121f、饋入層120f、饋入部143f與饋入導電孔1411f提供振盪無線射頻(radio frequency)電流給天線層142，且天線層142從電流輻射能量作為電磁波(electromagnetic wave)。此外，在接收方面，天線層142透過饋入導電孔1411f、饋入部143f、饋入層120f與饋入導電孔121f截取(intercept)電磁波的能量，以產生電壓提供給作為無線接收器(radio receiver)之晶片120。RF訊號路徑藉由直接地耦接天線基板140之饋入導電孔1411f至晶片120之饋入導電孔121f而縮短，進而減少RF訊號的衰退。
如第1A圖所示，天線層142被封裝體130包覆。然而， 另一實施例中，天線層142可從封裝體130露出。此外，天線基板140通過品質測試而為一已知合格(good)基板(例如，一工作天線基板)，其設置於晶片120上而形成半導體封裝件100。如此，具有缺陷之天線基板在設置於晶片120之前就可以被發現，如此可提升良率且降低成本。
請參照第1B圖，其繪示第1A圖之天線基板140之底視圖。 接地部143g與饋入部143f電性隔離，且環繞饋入部143f。此外，接地部 143g延伸至天線基板140之一側表面140s，以獲得最廣的屏蔽面積。
請繪示第2A圖，其繪示依照本發明另一實施例之半導體封 裝件200的剖視圖。半導體封裝件200包括封裝基板110、被動元件115、晶片120、封裝體130、天線基板140、接地線250g及饋入線250f。
晶片120設置於封裝基板110之上表面110u。晶片120包 括相對之上表面120u與主動面120b。面向天線基板140之上表面120u係一非主動面。主動面120b面向封裝基板110且透過數個焊球電性連接於封裝基板110。
封裝體130包覆晶片120、天線基板140及接地線250g 與饋入線250f。
天線基板140直接設置於晶片120上且包括核心層141、 天線層142及接地層143。核心層141包括相對之上表面141u與下表面141b及至少一接地導電孔1411g。天線層142形成於核心層141之上表面141u，且接地層143形成於核心層141之下表面141b且直接接觸晶片120之上表面120u。
天線基板140之天線層142包括接地部142g及天線部 142a，其中接地部142g透過接地線250g電性連接於封裝基板110，且天線部142a透過饋入線250f電性連接於封裝基板110。接地層143透過接地導電孔1411g電性連接於天線層142之天線接地部142g。因此，接地層143透過接地導電孔1411g、接地部142g與接地線250g電性連接於接地電位。透過封裝基板110之走線111及饋入線250f，RF訊號從天線基板140傳輸至晶片120。
請參照第2B圖，其繪示第2A圖之天線基板的底視圖。接 地層143覆蓋核心層141之整個下表面141b(第2A圖)，亦即，接地層143係一不具有中空圖案的連續金屬層。底視圖僅繪示本發明之一實施例，其非用以限制本發明。另一實施例中，接地層143可以是一圖案化接地層或可以覆蓋至少70%、至少80%、至少90%或至少95%之下表面141b。此外，接地層143可延伸至天線基板140之數個側表面140s的至少一者，以獲得最廣的屏蔽面積。
請參照第3圖，其繪示依照本發明另一實施例之半導體封 裝件300之剖視圖。半導體封裝件300包括封裝基板110、被動元件115、晶片120、封裝體130、天線基板140、至少一導電焊線360及隔離基板370。
晶片120以朝上方位(face-up)耦接於封裝基板110，且透過 數條導電焊線360電性連接於封裝基板110。晶片120包括面向封裝基板110之下表面120u與面向隔離基板370之主動面120b。
天線基板140包括核心層141、天線層142及接地層143。 本實施例中，接地層143之結構相似於第1A圖，容此不再贅述。
隔離基板370係一中介層基板，其設置於晶片120與天線 基板140之間，以提供一空間去容納導電焊線360，因而避免導電焊線360電性連接於天線基板140之接地層143。在實施例中，天線基板140直接設置於隔離基板370上，且隔離基板370直接設置於晶片120上，藉以縮短一訊號傳輸路徑以及控制電磁干擾。藉由控制天線基板140與隔離基板370之間的空間或隔離基板370與晶片120之間的空間亦可獲得類似的效 果，例如是約500微米內、400微米內、300微米內、200微米內、100微米內或約50微米的空間。
隔離基板370以朝下方位(face-down)直接耦接於晶片 120，且透過數個焊球電性連接於晶片120。隔離基板370包括基材371、饋入層370f及接地層370g。基材371包括上表面371u與下表面371b，其中饋入層370f及接地層370g形成於上表面371u。基材371更包括饋入導電孔3711f及接地導電孔3711g，其中饋入導電孔3711f電性連接於饋入層370f與晶片120，且接地導電孔3711g電性連接於接地層370g與晶片120。
請參照第4圖，其繪示依照本發明另一實施例之半導體封 裝件400的剖視圖。半導體封裝件400包括封裝基板110、被動元件115、晶片120、封裝體130、天線基板140、饋入線250f、接地線250g、至少一導電焊線360及隔離基板470。
天線基板140包括核心層141、天線層142及接地層143。 本實施例中，天線基板140的結構相似於第2A圖之結構，容此不再贅述。
饋入線250f電性連接於晶片及封裝基板110之走線 111，使RF訊號透過封裝基板110之走線111與饋入線250f從封裝基板110傳輸至晶片120。接地部142g可透過接地線250g與封裝基板110之走線111電性連接於接地電位。因為天線基板140可透過接地線250g與饋入線250f電性連接於封裝基板110，隔離基板470可省略數個導電元件，例如是導電孔(conductive via)或走線。
隔離基板470係一絕緣基板，其例如是由矽或玻璃形成。 隔離基板470直接設置於晶片120上且具有上表面470u。天線基板140直接設置於隔離基板470之上表面470u。
請參照第5A至5E圖，其繪示第1A圖之半導體封裝件之 製造過程圖。
如第5A圖所示，提供封裝基板110，其中封裝基板110包 括上表面110u、下表面110b、數條走線111、數個導電孔112及數個接墊113。走線111形成於上表面110u，導電孔112從上表面110u延伸至下表面110b，且接墊113形成於下表面110b。接墊113透過導電孔112電性連接於走線111。
如第5B圖所示，被動元件115及晶片120設置於封裝基板 110之上表面110u。晶片120以朝下方位耦接於封裝基板110之上表面110u，且透過數個焊球電性連接於封裝基板110。晶片120包括上表面120u，且係半導體裝置之一部分，其中半導體裝置包括饋入層120f及饋入導電孔121f，饋入導電孔121f形成於晶片120之上表面120u，而饋入導電孔121f電性連接饋入層120f與封裝基板110。
如第5C圖所示，可採用例如是表面黏貼技術(Surface mount technology,SMT)，設置天線基板140於晶片120上。天線基板140係通過品質測試且為一已知合格天線基板(例如是一工作基板)，其設置於晶片120上。如此，可提升良率以及降低成本。在實施例中，天線基板140水平地延伸至與被動元件115重疊。
天線基板140包括核心層141、天線層142及接地層143。 核心層141包括上表面141u、下表面141b、接地導電孔1411g及饋入導 電孔1411f。天線層142形成於核心層141之上表面141u，且接地層143形成於核心層141之下表面141b。天線層142包括天線部142a及接地部142g，其中接地部142g與天線部142a電性隔離。接地層143包括接地部143g及饋入部143f，其中饋入部143f與接地部143g電性隔離。天線部142a透過饋入導電孔1411f電性連接於饋入部143f，而接地部142g透過接地導電孔1411g電性連接於接地部143g。
如第5D圖所示，形成封裝體130於封裝基板110之上表 面110u上，其中封裝體130包覆被動元件115、晶片120與天線基板140。，如第5E圖所示，形成數個切割道T1經過封裝體130及封裝基板110，以形成半導體封裝件100。切割道T1使用雷射或刀具形成。 封裝體130之側表面130s與封裝基板110之側表面110s藉由切割而形成。側表面130s與側表面110s齊平。本實施例中，此種切割方法稱為”全穿切法(full-cut method)”，即，切割道T1切穿整個封裝基板110與封裝體130。另一實施例中，封裝體130與封裝基板110可使用半穿切法(half-cut method)切割，即，切割道T1可切穿封裝基板110之一部分或封裝體130之一部分。
半導體封裝件200的製造方法相似於半導體封裝件100， 容此不再說明。
請參照第6A至6E圖，其繪示第3圖之半導體封裝件的製 造過程圖。
如第6A圖所示，被動元件115及晶片120設置於封裝基板 110之上表面110u。晶片120以朝上方位耦接於封裝基板110之上表面 110u，且透過數個導電焊線360電性連接於封裝基板110。
如第6B圖所示，隔離基板370設置於晶片120上。隔離 基板370以朝下方位直接耦接於晶片120且透過數個焊球電性連接於晶片120。隔離基板370包括基材371、饋入層370f及接地層370g。基材371包括上表面371u與下表面371b，其中饋入層370f及接地層370g形成於上表面371u。基材371更包括饋入導電孔3711f及接地導電孔3711g，其中饋入導電孔3711f電性連接饋入層370f與晶片120，且接地導電孔3711g電性連接接地層370g與晶片120。
如第6C圖所示，可採用例如是表面黏貼技術(Surface mount technology,SMT)，設置天線基板140於隔離基板370上。天線基板140係通過品質測試且為一已知合格天線基板(例如是一工作天線基板)，其設置於隔離基板370上。在實施例中，天線基板140水平地延伸至與被動元件115重疊。
天線基板140包括核心層141、天線層142及接地層143， 其中核心層141包括上表面141u、下表面141b、接地導電孔1411g及饋入導電孔1411f。天線層142形成於核心層141之上表面141u，且接地層143形成於核心層141之下表面141b。天線層142包括天線部142a及接地部142g，其中接地部142g與天線部142a在空間上及電性上隔離。接地層143包括接地部143g及饋入部143f，其中饋入部143f與接地層143在空間上及電性上隔離。接地部143g透過接地導電孔1411g電性連接於接地部142g，而饋入部143f透過饋入導電孔1411f電性連接於天線部142a。
如第6D圖所示，形成封裝體130於封裝基板110之上表 面110u，其中封裝體130包覆被動元件115、晶片120、天線基板140與焊線360。
如第6E圖所示，形成數個切割道T1經過封裝體130及封 裝基板110，以形成半導體封裝件300。切割道T1使用雷射或刀具形成。 封裝體130之側表面130s與封裝基板110之側表面110s藉由切割形成，使側表面130s與側表面110s齊平。本實施例中，此種切割方法稱為”全穿切法”，即，切割道T1切穿整個封裝基板110與封裝體130。
半導體封裝件400的製造方法相似於第3圖之半導體封裝 件300，容此不再說明。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體封裝件
110‧‧‧封裝基板
110u、120u、141u‧‧‧上表面
110b、141b‧‧‧下表面
130s‧‧‧側表面
111‧‧‧走線
112‧‧‧導電孔
113‧‧‧接墊
115‧‧‧被動元件
120‧‧‧晶片
120b‧‧‧主動面
121f‧‧‧饋入導電孔
120f‧‧‧饋入層
120g‧‧‧接地層
121g‧‧‧接地導電孔
130‧‧‧封裝體
140‧‧‧天線基板
141‧‧‧核心層
142‧‧‧天線層
142a‧‧‧天線部
142g‧‧‧接地部
143‧‧‧接地層
143f‧‧‧饋入部
143g‧‧‧接地部
1411‧‧‧導電孔
1411f‧‧‧饋入導電孔
1411g‧‧‧接地導電孔

Claims (20)

  1. 一種半導體封裝件，包括：一封裝基板，包括一上表面；一半導體裝置，設置鄰接於該封裝基板之該上表面；一天線基板，設置於該半導體裝置之一上表面上，該天線基板包括：一核心層，包括一上表面、一下表面、在該核心層之該上表面與該下表面之間延伸的一側向表面及一導電孔(conductive via)；一接地層，形成於該核心層之該下表面上；以及一天線層，形成於該核心層之該上表面上，且透過該導電孔電性連接於該接地層；以及一封裝體，包覆該半導體裝置與該天線基板之該核心層之整個該側向表面。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中該接地層包括一饋入部及一接地部，該接地部環繞該饋入部且與該饋入部隔離。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中該接地層覆蓋該核心層之整個該下表面。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中該半導體裝置包括：一晶片，包括一上表面及一饋入導電孔(feeding conductive via)；以及一饋入層，形成於該晶片之該上表面上；其中，該天線基板透過該饋入層與該饋入導電孔電性連接 於該封裝基板。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中該半導體裝置包括一具有一上表面與一接地導電孔之晶片，且更包括一形成於該晶片之該上表面上之接地層，其中，該天線基板透過該接地層與該接地導電孔電性連接於該封裝基板。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中該天線基板之該天線層從該封裝體露出。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中該天線基板之該天線層包括一接地部及一天線部，且該半導體封裝件更包括：一饋入線，連接該天線部與該封裝基板；以及一接地線，連接該接地部與該封裝基板。
  8. 如申請專利範圍第1項所述之半導體封裝件，更包括：一被動元件，設置於該封裝基板上；其中，該天線基板至少部分地在該被動元件上方延伸。
  9. 一種半導體封裝件，包括：一封裝基板，包括一上表面；一晶片，設置鄰接於該封裝基板之該上表面；一線路，電性連接該晶片與該封裝基板；一隔離基板，設置於該晶片上；一天線基板，設置於該隔離基板上且包括：一核心層，包括一上表面、一下表面、在該核心層之該上表面與該下表面之間延伸的一側向表面及一導電孔；一接地層，形成於該核心層之該下表面上；及一天線層，形成於該核心層之該上表面上，且透過該導電孔電性連接於該接地層；以及 一封裝體，包覆該晶片、該隔離基板與該天線基板之該核心層之整個該側向表面。
  10. 如申請專利範圍第9項所述之半導體封裝件，其中該接地層包括一饋入部及一接地部，該接地部環繞該饋入部且與該饋入部隔離。
  11. 如申請專利範圍第9項所述之半導體封裝件，其中該接地層覆蓋該核心層之整個該下表面。
  12. 如申請專利範圍第9項所述之半導體封裝件，其中該隔離基板係一中介層基板(interposer substrate)，該中介層基板設置於該晶片與該天線基板之間，且包括一電性連接至該天線基板與該晶片之導電孔。
  13. 如申請專利範圍第12項所述之半導體封裝件，其中該中介層基板包括一上表面、一饋入層及一饋入導電孔，該饋入層形成於該中介層基板之該上表面處，而該天線基板透過該饋入層與該饋入導電孔電性連接於該晶片。
  14. 如申請專利範圍第12項所述之半導體封裝件，其中該中介層基板包括一上表面、一接地層及一接地導電孔，該接地層形成於該中介層基板之該上表面處，而該天線基板透過該中介層基板之該接地層與該接地導電孔電性連接於該晶片。
  15. 如申請專利範圍第9項所述之半導體封裝件，其中該晶片包括一面向該隔離基板之主動面。
  16. 如申請專利範圍第9項所述之半導體封裝件，其中該天線層從該封裝體露出。
  17. 如申請專利範圍第9項所述之半導體封裝件，其中該天線基板之該天線層包括一饋入部及一接地部，且該半導體封裝件包括： 一饋入線，連接該天線層之該饋入部與該封裝基板；以及一接地線，連接於該天線層之該接地部與該封裝基板。
  18. 如申請專利範圍第9項所述之半導體封裝件，更包括：一被動元件，設置於該封裝基板上；其中，該天線基板至少部分地在該被動元件上方延伸。
  19. 一種半導體封裝件之製造方法，包括：提供一封裝基板，其中該封裝基板包括一上表面；設置一晶片於該封裝基板之該上表面上；提供一天線基板，其中該天線基板係通過測試(verifid)的一工作天線基板，該天線基板包括：一核心層，包括一上表面、一下表面、在該核心層之該上表面與該下表面之間延伸的一側向表面及一導電孔；一接地層，形成於該核心層之該下表面上；及一天線層，形成於該核心層之該上表面上，且透過該導電孔電性連接於該接地層；設置該天線基板於該晶片之一上表面上；以及形成一封裝體包覆該晶片、該基板之該上表面之一部分與該天線基板之該核心層之整個該側向表面。
  20. 如申請專利範圍第19項所述之製造方法，其中於設置該天線基板於該晶片之步驟前，該製造方法更包括：設置一隔離基板於該晶片上。
TW102140113A 2013-03-04 2013-11-05 包括天線基板之半導體封裝件及其製造方法 TWI521794B (zh)

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TWI663781B (zh) * 2017-12-26 2019-06-21 國家中山科學研究院 多頻天線封裝結構

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CN107123623A (zh) 2017-09-01
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