CN104037137B - 包括天线基板的半导体封装件及其制造方法 - Google Patents

包括天线基板的半导体封装件及其制造方法 Download PDF

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CN104037137B
CN104037137B CN201410059783.0A CN201410059783A CN104037137B CN 104037137 B CN104037137 B CN 104037137B CN 201410059783 A CN201410059783 A CN 201410059783A CN 104037137 B CN104037137 B CN 104037137B
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substrate
antenna
chip
core layer
semiconductor package
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CN104037137A (zh
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颜瀚琦
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

半导体封装件包括封装基板、半导体装置、天线基板及封装体。半导体装置设置于封装基板的上表面。天线基板设置于半导体装置上且包括核心层、接地层及天线层。接地层形成于核心层的下表面。天线层形成于核心层的上表面，且通过核心层的导电孔电性连接于核心层的接地层。封装体包覆半导体装置与天线基板。

Description

包括天线基板的半导体封装件及其制造方法
技术领域
本发明是有关于一种半导体封装件及其制造方法，且特别是有关于一种具有天线基板的半导体封装件及其制造方法。
背景技术
无线通信装置例如是手机（cell phone），传统上包括用以传送或接收无线射频（RF）信号的天线。传统上，无线通信装置包括天线层及通信模块，其中天线层及通信模块整合成一芯片。然而，当芯片的一部分，例如是天线部或通信模块判断出有缺陷，即使芯片的其它部分可工作，整个芯片也必须报废。
发明内容
根据本发明的一实施例，提出一种半导体封装件。半导体封装件包括一封装基板、一半导体装置、一天线基板及一封装体。半导体装置邻设于封装基板的上表面。天线基板设置于半导体装置上，天线基板包括一核心层、一接地层及一天线层。核心层包括一上表面、一下表面及一导电孔(conductive via)。接地层形成于核心层的下表面。天线层形成于核心层的上表面，且通过导电孔电性连接于接地层。封装体包覆半导体装置与天线基板。
根据本发明的另一实施例，提出一种半导体封装件。半导体封装件包括一封装基板、一芯片、一隔离基板及一封装体。芯片设置于封装基板的上表面，且通过一线路电性连接于封装基板。隔离基板设置于芯片上。天线基板设置于隔离基板上且包括一核心层、一接地层及一天线层。核心层包括一上表面、一下表面及一导电孔。接地层形成于核心层的下表面。天线层形成于核心层的上表面，且通过导电孔电性连接于接地层。封装体包覆芯片、隔离基板与天线基板。
根据本发明的另一实施例，提出一种半导体封装件的制造方法。制造方法包括以下步骤。提供一封装基板，其中封装基板包括一上表面，设置一芯片于封装基板的上表面；提供一天线基板，其中天线基板是一通过测试(verifid)的一工作天线基板，包括一上表面、一下表面及一导电孔，接地层形成于核心层的下表面，而天线层形成于核心层的上表面且通过导电孔电性连接于接地层；设置天线基板于芯片上；以及，形成一封装体包覆芯片、基板的上表面的一部分与天线基板。
为了对本发明的上述及其他方面有更佳的了解，下文特举较佳实施例，并配合附图，作详细说明如下：
附图说明
图1A绘示依照本发明一实施例的半导体封装件的剖视图。
图1B绘示图1A的天线基板的底视图
图2A绘示依照本发明另一实施例的半导体封装件的剖视图。
图2B绘示图2A的天线基板的底视图。
图3绘示依照本发明另一实施例的半导体封装件的剖视图。
图4绘示依照本发明另一实施例的半导体封装件的剖视图。
图5A至5E绘示图1A的半导体封装件的制造过程图。
图6A至6E绘示图3的半导体封装件的制造过程图。
符号说明：
100、200、300、400：半导体封装件
110：封装基板
110u、120u、141u、371u、470u：上表面
110b、141b、371b：下表面
110s、130s、140s：侧表面
111：走线
112：导电孔
113：接垫
115：被动元件
120：芯片
120b：主动面
121f、3711f：馈入导电孔
120f：馈入层
120g：接地层
121g、3711g：接地导电孔
130：封装体
140：天线基板
141：核心层
142：天线层
142a：天线部
142g：接地部
143：接地层
143f：馈入部
143g：接地部
1411：导电孔
1411f：馈入导电孔
1411g：接地导电孔
250g：接地线
250f：馈入线
360：导电焊线
370、470：隔离基板
371：基材
370f：馈入层
370g：接地层
T1：切割道
具体实施方式
本发明实施例的一整合式半导体封装件包括一天线部及一无线通信装置的通信模块部，不会因为其整合而减少良率。以下是揭露这样的一整合式半导体封装件。
请参照图1A，其绘示依照本发明一实施例的半导体封装件的剖视图。半导体封装件100包括封装基板110、被动元件115、芯片120、封装体130及天线基板140。
封装基板具有相对的上表面110u与下表面110b、走线111、导电孔112与数个接垫113。走线111形成于上表面110u，导电孔112从上表面110u延伸到下表面110b，接垫113形成于下表面110b。被动元件115及芯片120可通过导电孔112电性连接于接垫113。此外，封装基板110例如是多层有机基板或陶瓷基板。
被动元件115设置于封装基板110的上表面110u，且通过走线111电性连接于芯片120。被动元件115例如是电阻、电感或电容。
芯片120设置于封装基板110的上表面110u。芯片120以朝下方位耦接于封装基板110的上表面110u，且通过数个焊球电性连接于封装基板110。这样的结构称为覆晶(flipchip)。芯片120可以是主动芯片或SOC(System on Chip)。例如，芯片120可以是一收发器(transceiver)，其传送无线射频(radio frequency,RF)信号给天线基板140且从天线基板140接收RF信号。
芯片120包括上表面120u及馈入导电孔121f。芯片120是半导体装置的一部分，其中半导体装置包括形成于芯片120的上表面120u的馈入层120f。馈入层120f通过馈入导电孔121f电性连接于封装基板110。半导体装置更包括形成于芯片120的上表面120u的接地层120g。芯片120包括电性连接接地层120g与封装基板110的接地导电孔121g。也就是说，形成于芯片120的上表面120u的接地层120g可通过接地导电孔121g电性连接于一接地电位。接地导电孔121g及馈入导电孔121f例如是硅穿孔(through-silicon via,TSV)实现。
封装体130包覆封装基板110的上表面110u的一部分、芯片120与天线基板140。封装体130可包括酚醛基树脂（Novolac-based resin）、环氧基树脂（epoxy-based resin）、硅基树脂（silicone-based resin）或其他适当的包覆剂。封装体130亦可包括适当的填充剂，例如是粉状的二氧化硅。可利用数种封装技术形成封装体130，例如是压缩成型（compression molding）、注射成型（injection molding）或转注成型（transfermolding）。
天线基板140设置于半导体装置上。在实施例中，天线基板140直接设置于半导体装置上而无中间层，以缩短一信号传输路径以及控制电磁干扰(electromagneticinterference,EMI)。经由控制天线基板140与半导体装置之间的空间亦可获得类似的效果，例如是约500微米内、约400微米内、约300微米内、约200微米内、约100微米内或约50微米的空间。
天线基板140包括核心层141、天线层142及接地层143。核心层141包括相对的上表面141u与下表面141b及至少一导电孔1411。于图1A的实施例中，至少一导电孔1411包括至少一馈入导电孔1411f及一接地导电孔1411g。核心层141例如是硅基板、有机基板及陶瓷基板。天线层142及接地层143是分别形成于核心层141的上表面141u与下表面141b。
接地层143包括馈入部143f及接地部143g，其中接地部143g与馈入部143f电性隔离。馈入部143f直接接触馈入层120f，且馈入部143f电性连接于馈入导电孔121f。接地部143g直接接触接地层120g，且接地部143g通过接地导电孔121g电性连接于接地电位。
由于接地层143的接地部143g电性连接于一接地电位，故接地层143可作为一屏蔽层，以保护接地层143下方的被动元件，避免其天线层142所导致的电磁干扰(EMI)。例如，图1A的实施例中，天线基板140的接地层143延伸覆盖芯片120且覆盖被动元件115以保护芯片120及被动元件115，避免其受到电磁干扰。另一实施例中，天线基板140可以延伸至封装体130的一侧表面，例如是侧表面130s，以与封装基板110的整个上表面110u重迭。
天线层142是一图案化金属层，其形成于核心层141的上表面141u。天线层142包括接地部142g及天线部142a，其中天线部142a电性隔离于接地部142g。天线部142a通过馈入导电孔1411f电性连接于接地层143的馈入部143f，且接地部142g通过接地导电孔1411g电性连接于接地层143的接地部143g。
天线基板140转换电力成为无线电波(radio wave)，反之亦然。在传输方面，芯片120作为一无线传送器(radio transmitter)，其通过馈入导电孔121f、馈入层120f、馈入部143f与馈入导电孔1411f提供振荡无线射频(radio frequency)电流给天线层142，且天线层142从电流辐射能量作为电磁波(electromagnetic wave)。此外，在接收方面，天线层142通过馈入导电孔1411f、馈入部143f、馈入层120f与馈入导电孔121f截取(intercept)电磁波的能量，以产生电压提供给作为无线接收器(radio receiver)的芯片120。RF信号路径经由直接地耦接天线基板140的馈入导电孔1411f至芯片120的馈入导电孔121f而缩短，进而减少RF信号的衰退。
如图1A所示，天线层142被封装体130包覆。然而，另一实施例中，天线层142可从封装体130露出。此外，天线基板140通过品质测试而为一已知合格(good)基板(例如，一工作天线基板)，其设置于芯片120上而形成半导体封装件100。如此，具有缺陷的天线基板在设置于芯片120之前就可以被发现，如此可提升良率且降低成本。
请参照图1B，其绘示图1A的天线基板140的底视图。接地部143g与馈入部143f电性隔离，且环绕馈入部143f。此外，接地部143g延伸至天线基板140的一侧表面140s，以获得最广的屏蔽面积。
请绘示图2A，其绘示依照本发明另一实施例的半导体封装件200的剖视图。半导体封装件200包括封装基板110、被动元件115、芯片120、封装体130、天线基板140、接地线250g及馈入线250f。
芯片120设置于封装基板110的上表面110u。芯片120包括相对的上表面120u与主动面120b。面向天线基板140的上表面120u是一非主动面。主动面120b面向封装基板110且通过数个焊球电性连接于封装基板110。
封装体130包覆芯片120、天线基板140及接地线250g与馈入线250f。
天线基板140直接设置于芯片120上且包括核心层141、天线层142及接地层143。核心层141包括相对的上表面141u与下表面141b及至少一接地导电孔1411g。天线层142形成于核心层141的上表面141u，且接地层143形成于核心层141的下表面141b且直接接触芯片120的上表面120u。
天线基板140的天线层142包括接地部142g及天线部142a，其中接地部142g通过接地线250g电性连接于封装基板110，且天线部142a通过馈入线250f电性连接于封装基板110。接地层143通过接地导电孔1411g电性连接于天线层142的天线接地部142g。因此，接地层143通过接地导电孔1411g、接地部142g与接地线250g电性连接于接地电位。通过封装基板110的走线111及馈入线250f，RF信号从天线基板140传输至芯片120。
请参照图2B，其绘示图2A的天线基板的底视图。接地层143覆盖核心层141的整个下表面141b(图2A)，亦即，接地层143是一不具有中空图案的连续金属层。底视图仅绘示本发明的一实施例，其非用以限制本发明。另一实施例中，接地层143可以是一图案化接地层或可以覆盖至少70%、至少80%、至少90%或至少95%的下表面141b。此外，接地层143可延伸至天线基板140的数个侧表面140s的至少一者，以获得最广的屏蔽面积。
请参照图3，其绘示依照本发明另一实施例的半导体封装件300的剖视图。半导体封装件300包括封装基板110、被动元件115、芯片120、封装体130、天线基板140、至少一导电焊线360及隔离基板370。
芯片120以朝上方位(face-up)耦接于封装基板110，且通过数条导电焊线360电性连接于封装基板110。芯片120包括面向封装基板110的下表面120u与面向隔离基板370的主动面120b。
天线基板140包括核心层141、天线层142及接地层143。本实施例中，接地层143的结构相似于图1A，容此不再赘述。
隔离基板370是一中介层基板，其设置于芯片120与天线基板140之间，以提供一空间去容纳导电焊线360，因而避免导电焊线360电性连接于天线基板140的接地层143。在实施例中，天线基板140直接设置于隔离基板370上，且隔离基板370直接设置于芯片120上，藉以缩短一信号传输路径以及控制电磁干扰。经由控制天线基板140与隔离基板370之间的空间或隔离基板370与芯片120之间的空间亦可获得类似的效果，例如是约500微米内、400微米内、300微米内、200微米内、100微米内或约50微米的空间。
隔离基板370以朝下方位(face-down)直接耦接于芯片120，且通过数个焊球电性连接于芯片120。隔离基板370包括基材371、馈入层370f及接地层370g。基材371包括上表面371u与下表面371b，其中馈入层370f及接地层370g形成于上表面371u。基材371更包括馈入导电孔3711f及接地导电孔3711g，其中馈入导电孔3711f电性连接于馈入层370f与芯片120，且接地导电孔3711g电性连接于接地层370g与芯片120。
请参照图4，其绘示依照本发明另一实施例的半导体封装件400的剖视图。半导体封装件400包括封装基板110、被动元件115、芯片120、封装体130、天线基板140、馈入线250f、接地线250g、至少一导电焊线360及隔离基板470。
天线基板140包括核心层141、天线层142及接地层143。本实施例中，天线基板140的结构相似于图2A的结构，容此不再赘述。
馈入线250f电性连接于芯片及封装基板110的走线111，使RF信号通过封装基板110的走线111与馈入线250f从封装基板110传输至芯片120。接地部142g可通过接地线250g与封装基板110的走线111电性连接于接地电位。因为天线基板140可通过接地线250g与馈入线250f电性连接于封装基板110，隔离基板470可省略数个导电元件，例如是导电孔(conductive via)或走线。
隔离基板470是一绝缘基板，其例如是由硅或玻璃形成。隔离基板470直接设置于芯片120上且具有上表面470u。天线基板140直接设置于隔离基板470的上表面470u。
请参照图5A至5E，其绘示图1A的半导体封装件的制造过程图。
如图5A所示，提供封装基板110，其中封装基板110包括上表面110u、下表面110b、数条走线111、数个导电孔112及数个接垫113。走线111形成于上表面110u，导电孔112从上表面110u延伸至下表面110b，且接垫113形成于下表面110b。接垫113通过导电孔112电性连接于走线111。
如图5B所示，被动元件115及芯片120设置于封装基板110的上表面110u。芯片120以朝下方位耦接于封装基板110的上表面110u，且通过数个焊球电性连接于封装基板110。芯片120包括上表面120u，且是半导体装置的一部分，其中半导体装置包括馈入层120f及馈入导电孔121f，馈入导电孔121f形成于芯片120的上表面120u，而馈入导电孔121f电性连接馈入层120f与封装基板110。
如图5C所示，可采用例如是表面黏贴技术(Surface mount technology,SMT)，设置天线基板140于芯片120上。天线基板140是通过品质测试且为一已知合格天线基板(例如是一工作基板)，其设置于芯片120上。如此，可提升良率以及降低成本。在实施例中，天线基板140水平地延伸至与被动元件115重迭。
天线基板140包括核心层141、天线层142及接地层143。核心层141包括上表面141u、下表面141b、接地导电孔1411g及馈入导电孔1411f。天线层142形成于核心层141的上表面141u，且接地层143形成于核心层141的下表面141b。天线层142包括天线部142a及接地部142g，其中接地部142g与天线部142a电性隔离。接地层143包括接地部143g及馈入部143f，其中馈入部143f与接地部143g电性隔离。天线部142a通过馈入导电孔1411f电性连接于馈入部143f，而接地部142g通过接地导电孔1411g电性连接于接地部143g。
如图5D所示，形成封装体130于封装基板110的上表面110u上，其中封装体130包覆被动元件115、芯片120与天线基板140。
如图5E所示，形成数个切割道T1经过封装体130及封装基板110，以形成半导体封装件100。切割道T1使用激光或刀具形成。封装体130的侧表面130s与封装基板110的侧表面110s经由切割而形成。侧表面130s与侧表面110s齐平。本实施例中，此种切割方法称为”全穿切法(full-cut method)”，即，切割道T1切穿整个封装基板110与封装体130。另一实施例中，封装体130与封装基板110可使用半穿切法(half-cut method)切割，即，切割道T1可切穿封装基板110的一部分或封装体130的一部分。
半导体封装件200的制造方法相似于半导体封装件100，容此不再说明。
请参照图6A至6E，其绘示图3的半导体封装件的制造过程图。
如图6A所示，被动元件115及芯片120设置于封装基板110的上表面110u。芯片120以朝上方位耦接于封装基板110的上表面110u，且通过数个导电焊线360电性连接于封装基板110。
如图6B所示，隔离基板370设置于芯片120上。隔离基板370以朝下方位直接耦接于芯片120且通过数个焊球电性连接于芯片120。隔离基板370包括基材371、馈入层370f及接地层370g。基材371包括上表面371u与下表面371b，其中馈入层370f及接地层370g形成于上表面371u。基材371更包括馈入导电孔3711f及接地导电孔3711g，其中馈入导电孔3711f电性连接馈入层370f与芯片120，且接地导电孔3711g电性连接接地层370g与芯片120。
如图6C所示，可采用例如是表面黏贴技术(Surface mount technology,SMT)，设置天线基板140于隔离基板370上。天线基板140是通过品质测试且为一已知合格天线基板(例如是一工作天线基板)，其设置于隔离基板370上。在实施例中，天线基板140水平地延伸至与被动元件115重迭。
天线基板140包括核心层141、天线层142及接地层143，其中核心层141包括上表面141u、下表面141b、接地导电孔1411g及馈入导电孔1411f。天线层142形成于核心层141的上表面141u，且接地层143形成于核心层141的下表面141b。天线层142包括天线部142a及接地部142g，其中接地部142g与天线部142a在空间上及电性上隔离。接地层143包括接地部143g及馈入部143f，其中馈入部143f与接地层143在空间上及电性上隔离。接地部143g通过接地导电孔1411g电性连接于接地部142g，而馈入部143f通过馈入导电孔1411f电性连接于天线部142a。
如图6D所示，形成封装体130于封装基板110的上表面110u，其中封装体130包覆被动元件115、芯片120、天线基板140与焊线360。
如图6E所示，形成数个切割道T1经过封装体130及封装基板110，以形成半导体封装件300。切割道T1使用激光或刀具形成。封装体130的侧表面130s与封装基板110的侧表面110s经由切割形成，使侧表面130s与侧表面110s齐平。本实施例中，此种切割方法称为”全穿切法”，即，切割道T1切穿整个封装基板110与封装体130。
半导体封装件400的制造方法相似于图3的半导体封装件300，容此不再说明。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视权利要求书所界定者为准。

Claims (20)

1.一种半导体封装件，其特征在于，包括：
一封装基板，包括一上表面；
一半导体装置，设置邻接于该封装基板的该上表面；
一天线基板，设置于该半导体装置上，该天线基板包括：
一核心层，包括一上表面、一下表面、在该核心层的该上表面与该下表面之间延伸的一侧向表面及一导电孔；
一接地层，形成于该核心层的该下表面上；以及
一天线层，形成于该核心层的该上表面上，且通过该导电孔电性连接于该接地层；以及
一封装体，包覆该半导体装置与该天线基板的该核心层的整个该侧向表面。
2.如权利要求1所述的半导体封装件，其特征在于，该接地层包括一馈入部及一接地部，该接地部环绕该馈入部且与该馈入部隔离。
3.如权利要求1所述的半导体封装件，其特征在于，该接地层覆盖该核心层的整个该下表面。
4.如权利要求1所述的半导体封装件，其特征在于，该半导体装置包括：
一芯片，包括一上表面及一馈入导电孔；以及
一馈入层，形成于该芯片的该上表面；
其中，该天线基板通过该馈入层与该馈入导电孔电性连接于该封装基板。
5.如权利要求1所述的半导体封装件，其特征在于，该半导体装置包括一具有一上表面与一接地导电孔的芯片，且更包括一形成于该芯片的该上表面上的接地层；
其中，该天线基板通过该芯片的该上表面上的该接地层与该接地导电孔电性连接于该封装基板。
6.如权利要求1所述的半导体封装件，其特征在于，该天线基板的该天线层从该封装体露出。
7.如权利要求1所述的半导体封装件，其特征在于，该天线基板的该天线层包括一接地部及一天线部，且该半导体封装件包括：
一馈入线，连接该天线部与该封装基板；以及
一接地线，连接该接地部与该封装基板。
8.如权利要求1所述的半导体封装件，其特征在于，更包括：
一被动元件，设置于该封装基板上；
其中，该天线基板延伸至覆盖该被动元件的至少一部分。
9.一种半导体封装件，其特征在于，包括：
一封装基板，包括一上表面；
一芯片，设置邻接于该封装基板的该上表面；
一线路，电性连接该芯片与该封装基板；
一隔离基板，设置于该芯片上；
一天线基板，设置于该隔离基板上且包括：
一核心层，包括一上表面、一下表面、在该核心层的该上表面与该下表面之间延伸的一侧向表面及一导电孔；
一接地层，形成于该核心层的该下表面上；及
一天线层，形成于该核心层的该上表面上，且通过该导电孔电性连接于该接地层；以及
一封装体，包覆该芯片、该隔离基板与该天线基板的该核心层的整个该侧向表面。
10.如权利要求9所述的半导体封装件，其特征在于，该接地层包括一馈入部及一接地部，该接地部环绕该馈入部且与该馈入部隔离。
11.如权利要求9所述的半导体封装件，其特征在于，该接地层覆盖该核心层的整个该下表面。
12.如权利要求9所述的半导体封装件，其特征在于，该隔离基板是一中介层基板，该中介层基板设置于该芯片与该天线基板之间，且包括一电性连接该天线基板与该芯片的导电孔。
13.如权利要求12所述的半导体封装件，其特征在于，该中介层基板包括一上表面、一馈入层及一馈入导电孔，该馈入层形成于该中介层基板的该上表面，而该天线基板通过该馈入层与该馈入导电孔电性连接于该芯片。
14.如权利要求12所述的半导体封装件，其特征在于，该中介层基板包括一上表面、一接地层及一接地导电孔，该中介层基板的该接地层形成于该中介层基板的该上表面，而该天线基板通过该中介层基板的该接地层与该接地导电孔电性连接于该芯片。
15.如权利要求9所述的半导体封装件，其特征在于，该芯片包括一面向该隔离基板的主动面。
16.如权利要求9所述的半导体封装件，其特征在于，该天线层从该封装体露出。
17.如权利要求9所述的半导体封装件，其特征在于，该天线基板的该天线层包括一馈入部及一接地部，且该半导体封装件包括：
一馈入线，连接该天线层的该馈入部与该封装基板；以及
一接地线，连接于该天线层的该接地部与该封装基板。
18.如权利要求9所述的半导体封装件，其特征在于，更包括：
一被动元件，设置于该封装基板上；
其中，该天线基板延伸至覆盖该被动元件的至少一部分。
19.一种半导体封装件的制造方法，其特征在于，包括：
提供一封装基板，其中该封装基板包括一上表面；
设置一芯片于该封装基板的该上表面；
提供一天线基板，其中该天线基板是通过测试的一工作天线基板，该天线基板包括：
一核心层，包括一上表面、一下表面、在该核心层的该上表面与该下表面之间延伸的一侧向表面及一导电孔；
一接地层，形成于该核心层的该下表面上；及
一天线层，形成于该核心层的该上表面上，且通过该导电孔电性连接于该接地层；
设置该天线基板于该芯片上；以及
形成一封装体包覆该芯片、该封装基板的该上表面的一部分与该天线基板的该核心层的整个该侧向表面。
20.如权利要求19所述的制造方法，其特征在于，于设置该天线基板于该芯片的步骤前，该制造方法更包括:
设置一隔离基板于该芯片上。
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US11664580B2 (en) 2023-05-30

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