TWI521583B - 半導體晶圓之載體接合及分離之製程 - Google Patents

半導體晶圓之載體接合及分離之製程 Download PDF

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TWI521583B
TWI521583B TW101143360A TW101143360A TWI521583B TW I521583 B TWI521583 B TW I521583B TW 101143360 A TW101143360 A TW 101143360A TW 101143360 A TW101143360 A TW 101143360A TW I521583 B TWI521583 B TW I521583B
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semiconductor wafer
carrier
adhesive
coating
barrier coating
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蕭偉民
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日月光半導體製造股份有限公司
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Description

半導體晶圓之載體接合及分離之製程
本發明係關於一種半導體元件之製程,特別的是,係關於製程中半導體晶圓之處理(Handling)及輸送(Transport)。
在製程中間狀態之半導體晶圓從一個工作站移到另一個工作站時必須非常小心的處理,以防止該晶圓受到損壞。通常,晶圓吸附器(Wafer Chuck)係安裝在晶圓或載體之表面。然而,此種方式會損壞晶圓,尤其是該吸附器從該晶圓拆卸下來時。由於減少該半導體晶圓厚度之努力一直在持續中,改良的半導體晶圓之處理及輸送技術將會變得越來越重要。
本揭露一方面係關於一種處理半導體晶圓之方法。在一實施例中,該處理半導體晶圓之方法包括:附著一載體至該半導體晶圓;將該半導體晶圓分成一內部及一外部,該載體從該內部移除所需之拉力實質上小於從該外部移除所需之拉力;及從該半導體晶圓之內部移除該載體。將該半導體晶圓分成該內部及該外部之步驟可以藉由利用一刀具或一雷射切割該半導體晶圓以形成該內部及該外部來實現。在一實施例中,該處理半導體晶圓之方法包括黏附該載體至該半導體晶圓之一主動面,其中一黏膠黏接該半導體晶圓之該主動面至一位於該載體表面之隔離塗層及不具有該隔離塗層之該載體表面之一部分。為了使該內部更容 易分離,該半導體晶圓之該主動面與該隔離塗層之間之黏著力係大致上小於該半導體晶圓與不具有該隔離塗層之該載體表面之部分之間之黏著力。
該方法特別適合於使用矽穿孔(Through Silicon Via,TSV)技術之半導體晶圓。在一實施例中,該處理半導體晶圓之方法更包括:在附著該載體至該半導體晶圓之主動面之後,移除該半導體晶圓之一非主動面之一部分以顯露位於該半導體晶圓內之至少一導電柱之一末端;以一保護層覆蓋該顯露之末端;及薄化該保護層以使得該末端突出於該保護層之外。為了更固定該晶圓,該方法更包括:附著該半導體晶圓之一非主動面至一切割膠帶之一第一表面。
本揭露另一方面係關於一種處理半導體晶圓之方法,其包括利用一第一黏膠以附著一載體至該半導體晶圓之一主動面,使得該第一黏膠係位於該半導體晶圓之主動面及一位於該載體之一表面之一隔離塗層,及一位於不具有該隔離塗層之該載體表面之一部分之第二黏膠之間;溶解該第二黏膠;及從該半導體晶圓移除該載體。
本揭露另一方面係關於一種處理半導體晶圓之方法,其包括利用一第一黏膠以附著一第一載體至該半導體晶圓之一主動面,使得該第一載體包含一位於該第一載體及該第一黏膠之間之第一隔離塗層,其中該第一隔離塗層之面積係小於該第一黏膠;形成一第二黏膠於該半導體晶圓之一非主動面;形成一第二載體於該第二黏膠上,其中該第二載體係為一高分子聚合物層;及從該半導體晶圓分離該第 一載體及該第一隔離塗層。
參考圖1,顯示本發明一實施例中準備被處理(Handling)及輸送(Transportation)之半導體晶圓20(以剖視圖呈現)。該半導體晶圓20具有一第一表面201、一第二表面202及複數個導電柱(Conductive Pillars)207。該半導體晶圓20可由矽(Silicon)、鍺(Germanium)、砷化鎵(Gallium Arsenide)等所製成,且該等導電柱207係由適當導電金屬,例如銅,所製成。在本實施例中,該半導體晶圓20包含一積體電路203位於該第一表面201及該等導電柱207(如圖所示),因此該第一表面201被定義為一主動面(Active Surface),且該第二表面202被定義為一非主動面(Inactive Surface)。然而,可以理解的是,該半導體晶圓20也可以是一中介基板(Interposer),其僅具有該等導電柱207。為了避免將導電金屬直接置於半導體材料中,一絕緣材料208,例如非導電高分子材料(包含聚亞醯胺(Polymide,PI)、環氧樹脂(Epoxy)或苯環丁烯(Benzocyclobutene,BCB))或無機材料(例如二氧化矽(SiO2)),係形成於該半導體材料及該等導電柱207之間。
在本實施例中,該積體電路203,例如CMOS電路,係係形成於該第一表面201且可包含一重佈層(Redistribution Layer,RDL),且複數個導電元件205係形成於該積體電路203上且電性連接至該等導電柱207。
一第一黏膠22係施加於該半導體晶圓20之第一表面 201。在本實施例中,該第一黏膠22係位於該積體電路203上,且包含一可溶劑溶解的黏膠(solvent-dissolving adhesive)。該可溶劑溶解的黏膠例如包含住友化學公司(SUMITOMO CHEMICAL)的X5000及X5300牌子的黏膠。
此外,提供一第一載體31,其可以是半導體材料或是絕緣材料例如玻璃。該第一載體31具有一第一隔離塗層(Isolation Coating)32,位於其一表面311。在本實施例中,該第一隔離塗層32係為一疏水性塗層。
參考圖2,該半導體晶圓20之第一表面201係附著該第一載體31,且係利用該第一黏膠22將該半導體晶圓20黏附至該第一載體31。該第一隔離塗層32之特性係為該第一隔離塗層32與該第一黏膠22間之黏著力較弱。在本實施例中,該等導電元件205係嵌在該第一黏膠22中,且該第一黏膠22之厚度係大於該等導電元件205之厚度。該第一隔離塗層32之面積係略小於該第一黏膠22之面積。在本實施例中,該第一黏膠22與該第一載體31間之黏著力係大於該第一黏膠22與該第一隔離塗層32之黏著力。
參考圖3,於該半導體晶圓20之第二表面202進行表面處理。以研磨及/或蝕刻方式薄化該半導體晶圓20之第二表面202,使得該等導電柱207突出於該半導體晶圓20之上表面,且形成複數個導電通孔(Conductive Via)204。因此,每一該等導電通孔204之末端2041(導電通孔204可包含該絕緣材料208及該導電柱207二個部分)係顯露。
參考圖4,例如以積層製程(Laminating Process)或旋轉 塗佈製程(Spin Coating Process)形成一保護層23於該第二表面202,以覆蓋該等導電通孔204之末端2041。該保護層23可以是非導電高分子材料(例如聚亞醯胺(Polymide,PI))、環氧樹脂(Epoxy)或苯環丁烯(Benzocyclobutene,BCB)。或者,也可使用無機保護層(例如二氧化矽(SiO2))。在本實施例中,該保護層23可能是感光性聚合物,例如苯環丁烯(Benzocyclobutene,BCB),且可以利用旋轉塗佈或噴射塗佈(Spray Coating)而形成。
參考圖5,以研磨及/或蝕刻方式薄化該保護層23以使得該等導電通孔204之末端2041突出於該保護層23之外。亦即,部分該保護層23仍留在該半導體晶圓20之第二表面202上,且填滿該等末端2041間之區域或在該等末端2041間之區域交錯。
參考圖6,以電鍍方式形成一表面處理層(surface finish layer)24於該等導電通孔204之末端2041。在本實施例中,該表面處理層24具有堆疊金屬層結構,例如鎳/金(Ni/Au)層或鎳/鈀/金(Ni/Pd/Au)層。
參考圖7,移除該半導體晶圓20及該第一黏膠22之一外緣部分以形成一圓形溝槽25以顯露部分該第一隔離塗層32。該半導體晶圓20被分割成一內部209及一外部210。該圓形溝槽25形成之後,該內部209係大致上全部利用該第一黏膠22附著至該第一隔離塗層32,如此,該內部209可容易地從該第一載體31分離。在本實施例中,為了移除大部分位於該圓形溝槽25內之第一黏膠22,該圓形溝槽25之 深度H係等於該半導體晶圓20之厚度t1、該第一黏膠22之厚度t2及10 μm之尺寸公差之總和。亦即,H=t1+t2±10 μm。在本實施例中,係利用一刀具51從該半導體晶圓20之第二表面202切割該半導體晶圓20及該第一黏膠22,且該內部209之表面積係略小於該第一隔離塗層32之表面積。
參考圖8,為了顯露一部份該第一隔離塗層32,該圓形溝槽25與該半導體晶圓20之一邊緣之距離d1係略大於該第一隔離塗層32與該半導體晶圓20之一邊緣之距離d2,使得該圓形溝槽25係形成於該第一隔離塗層32上。在本實施例中,d1和d2間之差距係介於400 μm至600 μm。
參考圖9,或者,一雷射42也可用以切割該半導體晶圓20及該第一黏膠22以形成該圓形溝槽25。
參考圖10,提供一第二載體。在本實施例中,該第二載體係為一切割膠帶41,其具有一第一表面411、一第二表面412及一位於該第一表面411之可紫外光解除之膠層(Ultraviolet-released Adhesive Layer)(圖中未示)。該切割膠帶41之第一表面411係利用該可紫外光解除之膠層而附著至該半導體晶圓20之第二表面202,且該等導電通孔204之末端2041係嵌在該可紫外光解除之膠層中。
參考圖11,形成一覆蓋層44於該切割膠帶41之第二表面412上。該覆蓋層44係為不透明層,且其尺寸及位置係對應該半導體晶圓20之內部209,且被當成一光罩使用。
參考圖12,利用一紫外光43照射該第二表面412位於該 覆蓋層44外之第一部份41a。因此,有效地降低在第一部份41a上之可紫外光解除之膠層之黏著力。此外,該切割膠帶41被該覆蓋層44覆蓋之一第二部份41b因未被該紫外光43照射而仍保持其黏著力。
參考圖13,該第一載體31係固定住,且對該切割膠帶41施加一拉力F。在本實施例中,該拉力F係大於該第一黏膠22與該第一隔離塗層32間之黏著力,因此,該第一載體31、該第一隔離塗層32及該半導體晶圓20之外部210同時從該切割膠帶41及該半導體晶圓20之內部209分離。
參考圖14,利用一溶劑(例如:加馬丁內酯(Gamma-Butyrolactone,GBL)或丙二醇甲醚醋酸酯(Propylene glycol methyl ether acetatePGMEA,PGMEA))將殘留之第一黏膠22從該半導體晶圓20移除,以顯露該等導電元件205。
本實施例之優點在於,該第一載體31分離後,使用該第二載體(該切割膠帶41)以支撐及保護該半導體晶圓20。此種強化之處理製程可使得該半導體晶圓20較不會受到損壞,因此增加該半導體製程之良率。再者,該第二載體(該切割膠帶41)所提供之支撐有利於清除該第一黏膠22之製程。此外,上述使用刀具51及雷射42之切割製程可大大地加速該第一載體31之分離速率。
參考圖15至圖18,顯示本發明另一實施例之暫時載體接合及分離之製程。本實施例係與上述之製程相似;然而,切割該半導體晶圓20及該第一黏膠22之步驟係不同。
參考圖15,移除該半導體晶圓20及該第一黏膠22之一外 緣部分以顯露部分該第一隔離塗層32。然而,在本實施例中,係利用該刀具51從該半導體晶圓20之第二表面202切割且移除該半導體晶圓20及該第一黏膠22之最外緣部分206,直到顯露該第一隔離塗層32為止。較佳地,也可同時切除該第一隔離塗層32之邊緣一小部分,以確保該第一載體31之表面311上沒有第一黏膠22。
參考圖16,或者,一雷射42也可用以切除該半導體晶圓20及該第一黏膠22之最外緣部分206。
參考圖17,該切割膠帶41之第一表面411係利用一黏膠層(圖中未示)而附著至該半導體晶圓20之第二表面202,且該等導電通孔204之末端2041係嵌在該黏膠層中。
參考圖18,該第一載體31及該第一隔離塗層32同時從該半導體晶圓20分離。然後,將該第一黏膠22浸於一溶劑(例如:加馬丁內酯(Gamma-Butyrolactone,GBL)或丙二醇甲醚醋酸酯(Propylene Glycol Methyl Ether Acetate,PGMEA))中。該溶劑溶解該第一黏膠22;因此,該半導體晶圓20之第一表面201係顯露。
該切割膠帶41保留在該半導體晶圓20上以使該半導體晶圓20可以被處理及/或從一個工作站輸送至另一個工作站。
參考圖19至圖24,顯示本發明另一實施例之暫時載體接合及分離之製程。本實施例係與上述之製程相似;然而,施加一第二載體之步驟係不同。
參考圖19,以電鍍方式形成一表面處理層24於該等導電 通孔204之末端2041後,一第二黏膠38形成於該半導體晶圓20之第二表面202該第二表面202,以覆蓋該等導電通孔204之末端2041。在本實施例中,該第二黏膠38係為一可溶劑溶解的黏膠,且其可與該第一黏膠22相同。
參考圖20,該第二黏膠38係利用旋轉塗佈(Spin Coating)或噴射塗佈(Spray Coating)所形成,且該第二黏膠38之面積係與該半導體晶圓20相同。
參考圖21,以旋轉塗佈或噴射塗佈形成一高分子聚合物層39於該第二黏膠38上。該高分子聚合物層39與該第二黏膠38係為實質不同之材料。在本實施例中,該高分子聚合物層39係為例如環氧樹脂(Epoxy)、封膠材料、雙馬來醯亞胺-三氮雜苯(Bismaleimide-Triazine,BT)樹脂、苯環丁烯(Benzocyclobutene,BCB)、PBO(polybezoxazole)或聚亞醯胺(Polymide,PI)。
參考圖22,經固化後,該高分子聚合物層39變成一第二載體40。在本實施例中,該第二載體40之面積係與該第二黏膠38相同,且為使該半導體晶圓20可以被處理及/或從一個工作站輸送至另一個工作站,該第二載體40係大致上比該第二黏膠38厚。
參考圖23,將該半導體晶圓20、該第一黏膠22及該第一載體31浸於一溶劑(例如:加馬丁內酯(Gamma-Butyrolactone,GBL)或丙二醇甲醚醋酸酯(Propylene glycol methyl ether acetatePGMEA,PGMEA)),接著,部分該第一黏膠22被溶解,且部分該第一隔離塗層32被顯露。接 著,由於該第一黏膠22及該第一隔離塗層32間之弱黏著力,該第一載體31及該第一隔離塗層32可以同時容易地從該半導體晶圓20分離。該第二載體40保留在該半導體晶圓20上以使該半導體晶圓20可以被處理及/或從一個工作站輸送至另一個工作站。
參考圖24,分離該第一載體31後,將殘留之第一黏膠22從該半導體晶圓20移除,以顯露該等導電元件205。
參考圖25至圖29,顯示本發明另一實施例之暫時載體接合及分離之製程。本實施例係與上述之製程相似;然而,該第一載體31之結構及該第一載體31之分離步驟係不同。
參考圖25,提供該第一載體31,該第一載體31具有一第一隔離塗層32,位於其一表面311。在本實施例中,該第一載體31係為半導體材料或是絕緣材料例如玻璃,且該第一隔離塗層32係為一疏水性塗層。一第一環邊黏膠34係形成於於該第一載體31之邊緣部分上,且係為環狀。在本實施例中,該第一環邊黏膠34係為感光性材質,例如正光阻或負光阻,且係利用乾膜疊層製程所製成。較佳地,該第一環邊黏膠34搭接該第一隔離塗層32。
參考圖26,提供該半導體晶圓20(以剖面圖表示)。該半導體晶圓20與圖1之該半導體晶圓20相同,因此不再贅述。接著,該第一黏膠22係施加於該半導體晶圓20之第一表面201。在本實施例中,該第一黏膠22係位於該積體電路203上,且包含一可溶劑溶解的黏膠。該可溶劑溶解的黏膠例如包含住友化學公司(SUMITOMO CHEMICAL)的 X5000及X5300牌子的黏膠。要注意的是,該第一黏膠22及該第一環邊黏膠34係實質上不同。
參考圖27,該半導體晶圓20之第一表面201係附著該第一載體31,且係利用該第一黏膠22將該半導體晶圓20黏附至該第一載體31。在本實施例中,該第一黏膠22接觸該第一環邊黏膠34,且該第一黏膠22與該第一環邊黏膠34間之黏著力係大於該第一黏膠22與該第一隔離塗層32間之黏著力。接著,於該半導體晶圓20之第二表面202進行表面處理,以形成複數個導電通道204。接著,形成一保護層23於該第二表面202,以覆蓋該等導電通道204之末端2041。接著,藉由電鍍以形成一表面處理層24於導電通道204之未端2041。
參考圖28,提供一第二載體。在本實施例中,該第二載體係為一切割膠帶41,其具有一第一表面411、一第二表面412及一位於該第一表面411之黏膠層(圖中未示)。該切割膠帶41之第一表面411係利用該黏膠層(圖中未示)而附著至該半導體晶圓20之第二表面202,且該等導電通道204之末端2041係嵌在該黏膠層中。
參考圖29,將該第一載體31、該第一環邊黏膠34及該半導體晶圓20浸於一鹼性溶劑,例如:氫氧化四甲基銨溶液(Tetramethylammonium Hydroxide,TMAH(aq))或氫氧化鈉溶液(NaOH(aq))中,且該第一環邊黏膠34被該鹼性溶劑溶解。接著,該第一載體31及該第一隔離塗層32係同時從該半導體晶圓20分離。該切割膠帶41保留在該半導體晶圓20 上以使該半導體晶圓20可以被處理及/或從一個工作站輸送至另一個工作站。分離該第一載體31後,將殘留之第一黏膠22從該半導體晶圓20移除,以顯露該等導電元件205。
參考圖30至圖32,顯示本發明另一實施例之暫時載體接合及分離之製程。本實施例係與上述之製程相似;然而,施加一第二載體之步驟係不同。
參考圖30,提供一第二載體35,其係為半導體材料或是絕緣材料例如玻璃。該第二載體35具有一表面351。接著,形成一第二隔離塗層36及一第二環邊黏膠37於該第二載體35之表面351,其中該第二環邊黏膠37係環繞且接觸該第二隔離塗層36。較佳地,該第二環邊黏膠37搭接該第二隔離塗層36。在本實施例中,該第二環邊黏膠37之形成方法係與該第一環邊黏膠34之形成方法相同,如圖25所示。在本實施例中,該第二環邊黏膠37之材質係與該第一環邊黏膠34之材質相同或不同。
參考圖31,利用一第二黏膠38將該第二載體35黏附至該半導體晶圓20之第二表面202。在本實施例中,該第二黏膠38與該第二環邊黏膠37間之黏著力係大於該第二黏膠38與該第二隔離塗層36間之黏著力。
參考圖32,將該第一環邊黏膠34、該第一黏膠22及該第一載體31浸於一鹼性溶劑,例如:氫氧化四甲基銨溶液(Tetramethylammonium Hydroxide,TMAH(aq))或氫氧化鈉溶液(NaOH(aq))中,且該第一環邊黏膠34被該鹼性溶劑溶 解。因此,該第一載體31及該第一隔離塗層32係同時從該半導體晶圓20分離。該第二載體35保留在該半導體晶圓20上以使該半導體晶圓20可以被處理及/或從一個工作站輸送至另一個工作站。分離該第一載體31後,將殘留之第一黏膠22從該半導體晶圓20移除,以顯露該等導電元件205。
惟上述實施例僅為說明本發明之原理及其功效,而非用以限制本發明。因此,習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
20‧‧‧半導體晶圓
22‧‧‧第一黏膠
23‧‧‧保護層
24‧‧‧表面處理層
25‧‧‧圓形溝槽
31‧‧‧第一載體
32‧‧‧第一隔離塗層
34‧‧‧第一環邊黏膠
35‧‧‧第二載體
36‧‧‧第二隔離塗層
37‧‧‧第二環邊黏膠
38‧‧‧第二黏膠
39‧‧‧高分子聚合物層
40‧‧‧第二載體
41‧‧‧切割膠帶
41a‧‧‧第一部份
41b‧‧‧第二部份
42‧‧‧雷射
43‧‧‧紫外光
44‧‧‧覆蓋層
51‧‧‧刀具
201‧‧‧第一表面
202‧‧‧第二表面
203‧‧‧積體電路
204‧‧‧導電通孔
205‧‧‧導電元件
206‧‧‧最外緣部分
207‧‧‧導電柱
208‧‧‧絕緣材料
209‧‧‧內部
210‧‧‧外部
311‧‧‧第一載體之表面
411‧‧‧第一表面
412‧‧‧第二表面
2041‧‧‧導電通孔之末端
F‧‧‧拉力
圖1至圖14顯示本發明一實施例之暫時載體接合及分離之製程;圖15至圖18顯示本發明另一實施例之暫時載體接合及分離之製程;圖19至圖24顯示本發明另一實施例之暫時載體接合及分離之製程;圖25至圖29顯示本發明另一實施例之暫時載體接合及分離之製程;及圖30至圖32顯示本發明另一實施例之暫時載體接合及分離之製程。
20‧‧‧半導體晶圓
22‧‧‧第一黏膠
23‧‧‧保護層
24‧‧‧表面處理層
25‧‧‧圓形溝槽
31‧‧‧第一載體
32‧‧‧第一隔離塗層
51‧‧‧刀具
201‧‧‧第一表面
202‧‧‧第二表面
203‧‧‧積體電路
204‧‧‧導電通孔
205‧‧‧導電元件
207‧‧‧導電柱
208‧‧‧絕緣材料
209‧‧‧內部
210‧‧‧外部
311‧‧‧第一載體之表面
2041‧‧‧導電通孔之末端

Claims (17)

  1. 一種處理半導體晶圓之方法,包括:附著一載體至該半導體晶圓,其中一黏膠黏接該半導體晶圓之一主動面至位於該載體表面之一隔離塗層及不具有該隔離塗層之該載體表面之一部分,且該半導體晶圓之該主動面與該隔離塗層之間之黏著力實質上係小於該半導體晶圓與不具有該隔離塗層之該載體表面之該部分之間之黏著力;將該半導體晶圓分成一內部及一外部,該載體從該內部移除所需之拉力實質上小於從該外部移除所需之拉力;及從該半導體晶圓之內部移除該載體。
  2. 如請求項1之方法,其中將該半導體晶圓分成該內部及該外部之步驟包含利用一刀具或一雷射切割該半導體晶圓以形成該內部及該外部。
  3. 如請求項1之方法,其中將該半導體晶圓分成該內部及該外部之步驟顯露出該隔離塗層。
  4. 如請求項1之方法,其中從該半導體晶圓之內部移除該載體之步驟包含施加一拉力至該載體。
  5. 如請求項1之方法,其中該隔離塗層係為一疏水性塗層。
  6. 如請求項1之方法,更包括:附著該半導體晶圓之一非主動面至一切割膠帶之一第一表面; 形成一覆蓋層於該切割膠帶之一第二表面上,其中該覆蓋層係對應該半導體晶圓之內部;及利用一紫外光照射該切割膠帶之第二表面,其中位於該覆蓋層之外之該切割膠帶之該第二表面之黏性變弱。
  7. 如請求項1之方法,更包括一從該半導體晶圓移除該黏膠之步驟。
  8. 如請求項1之方法,其中在附著該載體至該半導體晶圓之後更包括:移除該半導體晶圓之一非主動面之一部分以顯露位於該半導體晶圓內之至少一導電柱之一末端;以一保護層覆蓋該顯露之末端;及薄化該保護層以使得該末端突出於該保護層之外。
  9. 如請求項1之方法,其中將該半導體晶圓分成該內部及該外部之步驟包含形成一圓形溝槽以分割該內部及該外部,該圓形溝槽之深度係等於該半導體晶圓之厚度、一黏膠之厚度及一尺寸公差之總和。
  10. 如請求項9之方法,其中該圓形溝槽與該半導體晶圓之一邊緣之一距離係大於該隔離塗層與該半導體晶圓之一邊緣之一距離。
  11. 一種處理半導體晶圓之方法,包括:利用一第一黏膠以附著一載體至該半導體晶圓之一主動面,使得該第一黏膠係位於該半導體晶圓之主動面及一位於該載體之一表面之一隔離塗層,及一位於不具有該隔離塗層之該載體表面之一部分之第二黏膠之間; 溶解該第二黏膠;及從該半導體晶圓移除該載體。
  12. 如請求項11之方法,其中該第一黏膠與該第二黏膠係實質不同。
  13. 如請求項11之方法,其中該隔離塗層係為一疏水性塗層。
  14. 如請求項11之方法,更包括一利用一第三黏膠以附著一第二載體至該半導體晶圓之一非主動面之步驟。
  15. 如請求項14之方法,其中該第三黏膠係位於該半導體晶圓之非主動面及一位於該第二載體之一表面之第二隔離塗層,及一位於不具有該第二隔離塗層之該第二載體表面之一部分之第四黏膠。
  16. 一種處理半導體晶圓之方法,包括:利用一第一黏膠以附著一第一載體至該半導體晶圓之一主動面,使得該第一載體包含一位於該第一載體及該第一黏膠之間之第一隔離塗層,其中該第一隔離塗層之面積係小於該第一黏膠;形成一第二黏膠於該半導體晶圓之一非主動面;形成一第二載體於該第二黏膠上,其中該第二載體係為一高分子聚合物層;及從該半導體晶圓分離該第一載體及該第一隔離塗層。
  17. 如請求項16之方法,其中附著該載體至該半導體晶圓之後更包括:移除該半導體晶圓之一非主動面之一部分以顯露位於 該半導體晶圓內之至少一導電柱之一末端;以一保護層覆蓋該顯露之末端;及薄化該保護層以使得該末端突出於該保護層之外。
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US10543662B2 (en) 2012-02-08 2020-01-28 Corning Incorporated Device modified substrate article and methods for making
US9257368B2 (en) * 2012-05-14 2016-02-09 Intel Corporation Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
US10086584B2 (en) 2012-12-13 2018-10-02 Corning Incorporated Glass articles and methods for controlled bonding of glass sheets with carriers
TWI617437B (zh) 2012-12-13 2018-03-11 康寧公司 促進控制薄片與載體間接合之處理
US9340443B2 (en) 2012-12-13 2016-05-17 Corning Incorporated Bulk annealing of glass sheets
US9768089B2 (en) * 2013-03-13 2017-09-19 Globalfoundries Singapore Pte. Ltd. Wafer stack protection seal
DE102013106353B4 (de) * 2013-06-18 2018-06-28 Tdk Corporation Verfahren zum Aufbringen einer strukturierten Beschichtung auf ein Bauelement
US10510576B2 (en) * 2013-10-14 2019-12-17 Corning Incorporated Carrier-bonding methods and articles for semiconductor and interposer processing
KR102353030B1 (ko) 2014-01-27 2022-01-19 코닝 인코포레이티드 얇은 시트와 캐리어의 제어된 결합을 위한 물품 및 방법
SG11201608442TA (en) 2014-04-09 2016-11-29 Corning Inc Device modified substrate article and methods for making
DE102014113361A1 (de) * 2014-09-17 2016-03-17 Ev Group E. Thallner Gmbh Vorrichtung und Verfahren zum Ablösen eines Produktsubstrats von einem Trägersubstrat
KR102573207B1 (ko) 2015-05-19 2023-08-31 코닝 인코포레이티드 시트와 캐리어의 결합을 위한 물품 및 방법
CN117534339A (zh) 2015-06-26 2024-02-09 康宁股份有限公司 包含板材和载体的方法和制品
TW201825623A (zh) 2016-08-30 2018-07-16 美商康寧公司 用於片材接合的矽氧烷電漿聚合物
TWI821867B (zh) 2016-08-31 2023-11-11 美商康寧公司 具以可控制式黏結的薄片之製品及製作其之方法
TWI621231B (zh) * 2016-12-13 2018-04-11 南茂科技股份有限公司 晶片封裝結構的製作方法與基板結構
WO2019036710A1 (en) 2017-08-18 2019-02-21 Corning Incorporated TEMPORARY BINDING USING POLYCATIONIC POLYMERS
JP7431160B2 (ja) 2017-12-15 2024-02-14 コーニング インコーポレイテッド 基板を処理するための方法および結合されたシートを含む物品を製造するための方法
JP2019201030A (ja) * 2018-05-14 2019-11-21 東芝メモリ株式会社 半導体装置の製造方法
US10734285B2 (en) * 2018-06-28 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding support structure (and related process) for wafer stacking
CN114953214B (zh) * 2022-07-01 2024-03-19 苏州晶方光电科技有限公司 晶圆级光学透镜的切割方法

Family Cites Families (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761782A (en) 1971-05-19 1973-09-25 Signetics Corp Semiconductor structure, assembly and method
US4499655A (en) 1981-03-18 1985-02-19 General Electric Company Method for making alignment-enhancing feed-through conductors for stackable silicon-on-sapphire
US4394712A (en) 1981-03-18 1983-07-19 General Electric Company Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers
US4807021A (en) 1986-03-10 1989-02-21 Kabushiki Kaisha Toshiba Semiconductor device having stacking structure
US4897708A (en) 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
US4842699A (en) 1988-05-10 1989-06-27 Avantek, Inc. Method of selective via-hole and heat sink plating using a metal mask
US5191405A (en) 1988-12-23 1993-03-02 Matsushita Electric Industrial Co., Ltd. Three-dimensional stacked lsi
US5160779A (en) 1989-11-30 1992-11-03 Hoya Corporation Microprobe provided circuit substrate and method for producing the same
US5166097A (en) 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5239448A (en) 1991-10-28 1993-08-24 International Business Machines Corporation Formulation of multichip modules
US5404044A (en) 1992-09-29 1995-04-04 International Business Machines Corporation Parallel process interposer (PPI)
US5643831A (en) 1994-01-20 1997-07-01 Fujitsu Limited Process for forming solder balls on a plate having apertures using solder paste and transferring the solder balls to semiconductor device
WO1996008037A1 (en) 1994-09-06 1996-03-14 Sheldahl, Inc. Printed circuit substrate having unpackaged integrated circuit chips directly mounted thereto and method of manufacture
US6962829B2 (en) 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP4255161B2 (ja) 1998-04-10 2009-04-15 株式会社野田スクリーン 半田バンプ形成装置
JP3447961B2 (ja) 1998-08-26 2003-09-16 富士通株式会社 半導体装置の製造方法及び半導体製造装置
US20020017855A1 (en) 1998-10-01 2002-02-14 Complete Substrate Solutions Limited Visual display
US6295730B1 (en) 1999-09-02 2001-10-02 Micron Technology, Inc. Method and apparatus for forming metal contacts on a substrate
US6329631B1 (en) 1999-09-07 2001-12-11 Ray Yueh Solder strip exclusively for semiconductor packaging
TW434854B (en) 1999-11-09 2001-05-16 Advanced Semiconductor Eng Manufacturing method for stacked chip package
TW569424B (en) 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
JP4023076B2 (ja) 2000-07-27 2007-12-19 富士通株式会社 表裏導通基板及びその製造方法
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6406934B1 (en) 2000-09-05 2002-06-18 Amkor Technology, Inc. Wafer level production of chip size semiconductor packages
US6448506B1 (en) 2000-12-28 2002-09-10 Amkor Technology, Inc. Semiconductor package and circuit board for making the package
US6740950B2 (en) 2001-01-15 2004-05-25 Amkor Technology, Inc. Optical device packages having improved conductor efficiency, optical coupling and thermal transfer
JP4113679B2 (ja) 2001-02-14 2008-07-09 イビデン株式会社 三次元実装パッケージの製造方法
JP2002270718A (ja) 2001-03-07 2002-09-20 Seiko Epson Corp 配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
FR2823596B1 (fr) 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
JP2002373957A (ja) 2001-06-14 2002-12-26 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US7334326B1 (en) 2001-06-19 2008-02-26 Amkor Technology, Inc. Method for making an integrated circuit substrate having embedded passive components
JP3875867B2 (ja) 2001-10-15 2007-01-31 新光電気工業株式会社 シリコン基板の穴形成方法
JP3904484B2 (ja) 2002-06-19 2007-04-11 新光電気工業株式会社 シリコン基板のスルーホールプラギング方法
US7049691B2 (en) 2002-10-08 2006-05-23 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
JP2004228135A (ja) 2003-01-20 2004-08-12 Mitsubishi Electric Corp 微細孔への金属埋め込み方法
JP2004273563A (ja) 2003-03-05 2004-09-30 Shinko Electric Ind Co Ltd 基板の製造方法及び基板
US6908856B2 (en) 2003-04-03 2005-06-21 Interuniversitair Microelektronica Centrum (Imec) Method for producing electrical through hole interconnects and devices made thereof
US20050095835A1 (en) 2003-09-26 2005-05-05 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
US7276787B2 (en) 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US20050189635A1 (en) 2004-03-01 2005-09-01 Tessera, Inc. Packaged acoustic and electromagnetic transducer chips
US20050258545A1 (en) 2004-05-24 2005-11-24 Chippac, Inc. Multiple die package with adhesive/spacer structure and insulated die surface
JP4343044B2 (ja) 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
TWI242869B (en) 2004-10-15 2005-11-01 Advanced Semiconductor Eng High density substrate for multi-chip package
TWI254425B (en) 2004-10-26 2006-05-01 Advanced Semiconductor Eng Chip package structure, chip packaging process, chip carrier and manufacturing process thereof
JP3987521B2 (ja) 2004-11-08 2007-10-10 新光電気工業株式会社 基板の製造方法
JP4369348B2 (ja) 2004-11-08 2009-11-18 新光電気工業株式会社 基板及びその製造方法
KR100687069B1 (ko) 2005-01-07 2007-02-27 삼성전자주식회사 보호판이 부착된 이미지 센서 칩과 그의 제조 방법
TWI264807B (en) 2005-03-02 2006-10-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TWI244186B (en) 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
US7285434B2 (en) 2005-03-09 2007-10-23 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same
TWI261325B (en) 2005-03-25 2006-09-01 Advanced Semiconductor Eng Package structure of semiconductor and wafer-level formation thereof
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7767493B2 (en) 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7969015B2 (en) 2005-06-14 2011-06-28 Cufer Asset Ltd. L.L.C. Inverse chip connector
JP2007027451A (ja) 2005-07-19 2007-02-01 Shinko Electric Ind Co Ltd 回路基板及びその製造方法
JP4889974B2 (ja) 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
JP4716819B2 (ja) 2005-08-22 2011-07-06 新光電気工業株式会社 インターポーザの製造方法
US7488680B2 (en) 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers
TWI311356B (en) 2006-01-02 2009-06-21 Advanced Semiconductor Eng Package structure and fabricating method thereof
DE102006000687B4 (de) 2006-01-03 2010-09-09 Thallner, Erich, Dipl.-Ing. Kombination aus einem Träger und einem Wafer, Vorrichtung zum Trennen der Kombination und Verfahren zur Handhabung eines Trägers und eines Wafers
TWI303105B (en) 2006-01-11 2008-11-11 Advanced Semiconductor Eng Wafer level package for image sensor components and its fabricating method
TWI293499B (en) 2006-01-25 2008-02-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
TWI287274B (en) 2006-01-25 2007-09-21 Advanced Semiconductor Eng Three dimensional package and method of making the same
TWI287273B (en) 2006-01-25 2007-09-21 Advanced Semiconductor Eng Three dimensional package and method of making the same
US7304859B2 (en) 2006-03-30 2007-12-04 Stats Chippac Ltd. Chip carrier and fabrication method
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
JP5026038B2 (ja) 2006-09-22 2012-09-12 新光電気工業株式会社 電子部品装置
TWI315295B (en) 2006-12-29 2009-10-01 Advanced Semiconductor Eng Mems microphone module and method thereof
US7598163B2 (en) 2007-02-15 2009-10-06 John Callahan Post-seed deposition process
TW200839903A (en) 2007-03-21 2008-10-01 Advanced Semiconductor Eng Method for manufacturing electrical connections in wafer
TWI335654B (en) 2007-05-04 2011-01-01 Advanced Semiconductor Eng Package for reducing stress
US7553752B2 (en) 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
TWI335059B (en) 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
TWI387019B (zh) 2007-08-02 2013-02-21 Advanced Semiconductor Eng 在基材上形成穿導孔之方法
TWI357118B (en) 2007-08-02 2012-01-21 Advanced Semiconductor Eng Method for forming vias in a substrate
TWI344694B (en) 2007-08-06 2011-07-01 Siliconware Precision Industries Co Ltd Sensor-type package and method for fabricating the same
TWI345296B (en) 2007-08-07 2011-07-11 Advanced Semiconductor Eng Package having a self-aligned die and the method for making the same, and a stacked package and the method for making the same
JP5536322B2 (ja) 2007-10-09 2014-07-02 新光電気工業株式会社 基板の製造方法
US7691747B2 (en) 2007-11-29 2010-04-06 STATS ChipPAC, Ltd Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
TWI365483B (en) 2007-12-04 2012-06-01 Advanced Semiconductor Eng Method for forming a via in a substrate
US7838395B2 (en) 2007-12-06 2010-11-23 Stats Chippac, Ltd. Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same
US7851246B2 (en) 2007-12-27 2010-12-14 Stats Chippac, Ltd. Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device
PT2238618E (pt) 2008-01-24 2015-09-03 Brewer Science Inc Método para montagem reversível de uma bolacha de dispositivo num substrato de suporte
KR100963675B1 (ko) 2008-03-14 2010-06-15 제일모직주식회사 반도체 패키징용 복합기능 테이프 및 이를 이용한 반도체소자의 제조방법
US8072079B2 (en) 2008-03-27 2011-12-06 Stats Chippac, Ltd. Through hole vias at saw streets including protrusions or recesses for interconnection
US7741156B2 (en) 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
US7666711B2 (en) 2008-05-27 2010-02-23 Stats Chippac, Ltd. Semiconductor device and method of forming double-sided through vias in saw streets
TWI420640B (zh) 2008-05-28 2013-12-21 矽品精密工業股份有限公司 半導體封裝裝置、半導體封裝結構及其製法
US8101460B2 (en) 2008-06-04 2012-01-24 Stats Chippac, Ltd. Semiconductor device and method of shielding semiconductor die from inter-device interference
US7851893B2 (en) 2008-06-10 2010-12-14 Stats Chippac, Ltd. Semiconductor device and method of connecting a shielding layer to ground through conductive vias
US7863721B2 (en) 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
TWI365528B (en) 2008-06-27 2012-06-01 Advanced Semiconductor Eng Semiconductor structure and method for manufacturing the same
US8183087B2 (en) 2008-09-09 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component
US9559046B2 (en) 2008-09-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-in package-on-package structure using through silicon vias
US7772081B2 (en) 2008-09-17 2010-08-10 Stats Chippac, Ltd. Semiconductor device and method of forming high-frequency circuit structure and method thereof
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US7741148B1 (en) 2008-12-10 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support
US8017515B2 (en) 2008-12-10 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief
US8283250B2 (en) 2008-12-10 2012-10-09 Stats Chippac, Ltd. Semiconductor device and method of forming a conductive via-in-via structure
US8900921B2 (en) 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
US7786008B2 (en) 2008-12-12 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof
TWI387084B (zh) 2009-01-23 2013-02-21 Advanced Semiconductor Eng 具有穿導孔之基板及具有穿導孔之基板之封裝結構
JP2010206044A (ja) 2009-03-05 2010-09-16 Toshiba Corp 半導体装置の製造方法
TWI470766B (zh) 2009-03-10 2015-01-21 Advanced Semiconductor Eng 晶片結構、晶圓結構以及晶片製程
TWI380421B (en) 2009-03-13 2012-12-21 Advanced Semiconductor Eng Method for making silicon wafer having through via
TW201034150A (en) 2009-03-13 2010-09-16 Advanced Semiconductor Eng Silicon wafer having interconnection metal
TWI394253B (zh) 2009-03-25 2013-04-21 Advanced Semiconductor Eng 具有凸塊之晶片及具有凸塊之晶片之封裝結構
EP2419928A2 (en) 2009-04-16 2012-02-22 Süss Microtec Lithography GmbH Improved apparatus for temporary wafer bonding and debonding
TWI394221B (zh) 2009-04-30 2013-04-21 Advanced Semiconductor Eng 具有測試銲墊之矽晶圓及其測試方法
US20100327465A1 (en) 2009-06-25 2010-12-30 Advanced Semiconductor Engineering, Inc. Package process and package structure
JP2011018806A (ja) 2009-07-09 2011-01-27 Sumitomo Bakelite Co Ltd 半導体用フィルムおよび半導体装置の製造方法
US8471156B2 (en) 2009-08-28 2013-06-25 Advanced Semiconductor Engineering, Inc. Method for forming a via in a substrate and substrate with a via
TWI406380B (zh) 2009-09-23 2013-08-21 Advanced Semiconductor Eng 具有穿導孔之半導體元件及其製造方法及具有穿導孔之半導體元件之封裝結構
FR2957190B1 (fr) 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage par effets thermomecaniques.

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US20130203265A1 (en) 2013-08-08
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TW201334052A (zh) 2013-08-16

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