TWI521568B - A wafer structure, and a power element to which it is applied - Google Patents

A wafer structure, and a power element to which it is applied Download PDF

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TWI521568B
TWI521568B TW102144435A TW102144435A TWI521568B TW I521568 B TWI521568 B TW I521568B TW 102144435 A TW102144435 A TW 102144435A TW 102144435 A TW102144435 A TW 102144435A TW I521568 B TWI521568 B TW I521568B
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doped layer
layer
doped
wafer structure
metal oxide
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TW201435987A (zh
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zhong-ping Liao
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Silergy Semiconductor Technology Hangzhou Ltd
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Description

晶圓結構以及應用其的功率元件
本發明涉及半導體功率元件技術領域，更具體的說，是關於一種晶圓結構以及應用其的功率元件。
在功率元件製造程序中，一般採用的晶圓結構為：在原始的低阻半導體基底上向外延伸一層高阻層，即磊晶層，用來耐受高壓，低阻基底作為支撐而不增加更多的電阻。圖1(a)所示為現有技術中通常採用的晶圓結構的示意圖，其中1'為半導體基底，2'為單一層次、均勻摻雜的磊晶層，而圖1(b)所示為對應的磊晶層2'摻雜濃度示意圖，其中橫坐標C表示摻雜濃度的大小，縱坐標Y表示縱向深度。但是這種磊晶結構難以提高元件的終端耐壓參數(BV)。
參考圖2，所示為圖1所示的晶圓結構應用在採用溝槽填充程序製造的縱向超級接面金屬氧化物場效應電晶體(Super Junction MOSFET)的結構示意圖。由於磊晶結構在程序過程中形成的表面場氧化層的作用，易於使磊晶層2中N型雜質積聚在表面，因此在刻蝕的溝槽中填充P 型矽形成的P柱4在製造的過程中，其表面部分的P型雜質被中和，從而形成了向內聚攏的結構6，這種聚攏的結構使得SJMOS的終端在表面處不易耗盡，導致了其擊穿電壓偏低。
參考圖3，所示為圖1所示的晶圓結構應用在普通的垂直雙擴散金屬氧化物半導體場效應電晶體(VDMOS)終端中的結構示意圖，其中7為VDMOS的P型體區，8為耗盡層邊界，其構成的終端結構難以承受高壓，即耐壓係數較低，並且終端設計較為困難。
有鑒於現有技術的上述缺陷，本發明的目的在於提供一種晶圓結構以及應用其的功率元件，以克服現有技術中的功率元件耐壓不高的問題。
為實現上述目的，本發明提供如下技術方案：依據本發明一實施例的一種晶圓結構，包括：高濃度摻雜的第一摻雜層；依次位於所述第一摻雜層上的第二摻雜層和第三摻雜層；其中，所述第三摻雜層為本徵層。
較佳的，所述第二摻雜層的摻雜濃度為均勻分佈或梯度分佈。
較佳的，所述第二摻雜層的雜質類型與所述第一摻雜層的雜質類型相同或相反。
較佳的，所述第二摻雜層和第三摻雜層在所述第一摻 雜層上依次磊晶生長形成。
依據本發明一實施例的一種功率元件，包括依據本發明的任一晶圓結構。
較佳的，所述功率元件為金屬氧化層半導體場效電晶體(MOSFET)、絕緣閘雙極型電晶體(IGBT)或二極體。
較佳的，所述金屬氧化層半導體場效電晶體(MOSFET)為縱向超級接面金屬氧化物場效應電晶體或垂直雙擴散金屬氧化物半導體場效應電晶體。
較佳的，所述縱向超級接面金屬氧化物場效應電晶體由溝槽填充程序製造。
經由上述的技術方案可知，與現有技術相比，本發明提供了一種新的晶圓結構，其中摻雜濃度較高的第一摻雜層作為基底結構，位於第一摻雜層上的第二摻雜層具有一定的摻雜濃度，而最上方的第三摻雜層為本徵材質，這樣由第二摻雜層和第三摻雜層作為雙層的磊晶結構應用在功率元件中。依據本發明的實施例不僅可以提高功率元件的耐壓，同時擊穿電壓的穩定性也得到了較大的改善，並具有更強的程序容差能力和更高的終端可靠性。通過下文較佳的實施例的具體描述，本發明的上述和其他優點更顯而易見。
1'‧‧‧半導體基底
2'‧‧‧磊晶層
1‧‧‧第一摻雜層
2‧‧‧第二摻雜層
3‧‧‧第三摻雜層
4‧‧‧P柱
5‧‧‧碗狀結構
6‧‧‧聚攏結構
7‧‧‧P型體區
8‧‧‧耗盡層邊界
71‧‧‧P型體區形成的等位環
72‧‧‧浮空環結構
為了更清楚地說明本發明實施例或現有技術中的技術 方案，下面將對實施例或現有技術描述中所需要使用的圖式作簡單地介紹，顯而易見地，下面描述中的圖式僅僅是本發明的實施例，對於本領域具有通常知識者來講，在不付出創造性勞動的前提下，還可以根據提供的圖式獲得其他的圖式。
圖1所示為現有晶圓結構中的磊晶結構和摻雜濃度分佈的示意圖；圖2所示為現有的晶圓結構應用在縱向超級接面金屬氧化物場效應電晶體的結構示意圖。
圖3所示為現有的晶圓結構應用在垂直雙擴散金屬氧化物半導體場效應電晶體中的結構示意圖。
圖4所示為依據本發明的晶圓結構及其摻雜濃度分佈的示意圖；圖5所示為依據本發明的晶圓結構應用在縱向超級接面金屬氧化物場效應電晶體的結構示意圖；圖6所示為依據本發明的晶圓結構應用在垂直雙擴散金屬氧化物半導體場效應電晶體的結構示意圖；圖7所示為圖6中VDMOS結構沿AA'方向的剖面圖。
以下結合圖式對本發明的幾個較佳的實施例進行詳細描述，但本發明並不僅僅限於這些實施例。本發明涵蓋任何在本發明的精髓和範圍上做的替代、修改、等效方法以 及方案。為了使公眾對本發明有徹底的瞭解，在以下本發明較佳的實施例中詳細說明了具體的細節，而對本領域具有通常知識者來說沒有這些細節的描述也可以完全理解本發明。
圖4中所示的依據本發明的晶圓結構，其包括第一摻雜層1以及依次位於其上的第二摻雜層2和第三摻雜層3；其中所述第一摻雜層1為高濃度摻雜，所述第二摻雜層2具有一定的摻雜雜質，但一般為低濃度摻雜，而所述第三摻雜層的摻雜濃度低於所述第二摻雜層或為沒有摻雜雜質的本徵材質。其中所述第二摻雜層2中摻雜濃度可以如圖4(a)中所示的均勻分佈，也可以採用圖4(b)中的摻雜濃度連續梯度變化。通常，所述第二摻雜層2的厚度一般要大於所述第三摻雜層3。
所述第二摻雜層2的雜質類型可以與所述第一摻雜層1的雜質類型相同或相反，例如圖4中所示的，當所述第二摻雜層2的摻雜類型為N-摻雜時，對應的所述第一摻雜層1可以為N+摻雜或P+摻雜，由功率元件製造過程中的具體要求而定。
在實際應用中，一般可將第一摻雜層1作為半導體基底，所述第二摻雜層2和第三摻雜層3作為磊晶層在其上方依次磊晶生長形成，他們的基礎材質保持一致，如比較常用的半導體基底材料為重摻雜砷或磷的矽材料，而第二摻雜層為輕摻雜磷的矽磊晶，第三摻雜層為本徵摻雜矽磊晶。
本發明提供一種功率元件，其包括依據本發明實現的任一晶圓結構，並在所述晶圓結構中形成其有源區域。這樣的功率元件較佳為金屬氧化層半導體場效電晶體(MOSFET)、絕緣閘雙極型電晶體(IGBT)，也可以是二極體。
下面以縱向超級接面金屬氧化物場效應電晶體(Super Junction MOSFET)和垂直雙擴散金屬氧化物半導體場效應電晶體(VDMOS)為例對依據本發明的功率元件的結構和優點進行具體說明，其中所述第三摻雜層為本徵層。
參考圖5，所示為依據本發明的晶圓結構應用在縱向超級接面MOS電晶體的結構示意圖；其中第一摻雜層1為N型重摻雜的矽基底，第二摻雜層2為N型輕摻雜，其摻雜濃度為均勻分佈，所述超級接面MOS電晶體由溝槽填充程序製造，在蝕刻形成的溝槽中填充P型矽形成的P柱結構4，繼而形成氧化層(Field Oxide)和金屬層(Metal)，由於第三摻雜層3的區域沒有摻雜雜質，因此P型矽在第三摻雜層3部分由於製造過程中的高溫擴散會形成碗狀結構5，從而使得超級接面MOS電晶體的終端結構表面容易耗盡，提高了擊穿電壓，而且採用這種晶圓結構的功率元件具有更強的程序容差能力和更高的終端可靠性。
參考圖6，所示為依據本發明的晶圓結構應用在VDMOS的結構示意圖，其中71為P型體區形成的等位 環，72為浮空環結構。第三摻雜層3在承受高壓時，其耗盡層將在表層拓展，因此耗盡層邊界8的曲率將發生變化，在第三摻雜層3中耗盡層曲率降低也將降低PN接面的臨界電場，從而提高了功率元件的擊穿電壓。
另一方面可以從元件的縱向耐壓上分析：參考圖7所示的圖6結構中沿AA'方向的剖面圖，可以看出圖6中終端的浮空環和晶圓結構形成了PIN-N+結構，由於本徵層的存在，因此浮空環71部分的擊穿電壓得到了提升，因此終端的縱向耐壓進一步得到提高。
同樣的，依據本發明的磊晶結構同樣也適用於二極體元件，其結構與原理與圖6所示的VDMOS結構相似，在此不再贅述。
另外，還需要說明的是，在本文中，術語“包括”、“包含”或者其任何其他變體意在涵蓋非排他性的包含，從而使得包括一系列要素的過程、方法、物品或者設備不僅包括那些要素，而且還包括沒有明確列出的其他要素，或者是還包括為這種過程、方法、物品或者設備所固有的要素。在沒有更多限制的情況下，由語句“包括一個......”限定的要素，並不排除在包括所述要素的過程、方法、物品或者設備中還存在另外的相同要素。
依照本發明的實施例如上文所述，這些實施例並沒有詳盡敘述所有的細節，也不限制該發明僅為所述的具體實施例。顯然，根據以上描述，可作很多的修改和變化。本說明書選取並具體描述這些實施例，是為了更好地解釋本 發明的原理和實際應用，從而使所屬技術領域技術人員能很好地利用本發明以及在本發明基礎上的修改使用。本發明僅受申請專利範圍及其全部範圍和等效物的限制。
1‧‧‧第一摻雜層
2‧‧‧第二摻雜層
3‧‧‧第三摻雜層
4‧‧‧P柱
5‧‧‧碗狀結構

Claims (8)

  1. 一種晶圓結構，其特徵在於，包括：高濃度摻雜的第一摻雜層；依次位於該第一摻雜層上的第二摻雜層和第三摻雜層；其中，該第三摻雜層為本徵層。
  2. 根據申請專利範圍第1項所述的晶圓結構，其中，該第二摻雜層的摻雜濃度為均勻分佈或梯度分佈。
  3. 根據申請專利範圍第1項所述的晶圓結構，其中，該第二摻雜層的雜質類型與該第一摻雜層的雜質類型相同或相反。
  4. 根據申請專利範圍第1項所述的晶圓結構，其中，該第二摻雜層和第三摻雜層在該第一摻雜層上依次磊晶生長形成。
  5. 一種功率元件，其特徵在於，包括申請專利範圍第1至4項中任一項所述的晶圓結構。
  6. 根據申請專利範圍第5項所述的功率元件，其中，該功率元件為金屬氧化層半導體場效電晶體(MOSFET)、絕緣閘雙極型電晶體(IGBT)或二極體。
  7. 根據申請專利範圍第6項所述的功率元件，其中，該金屬氧化層半導體場效電晶體(MOSFET)為縱向超級接面金屬氧化物場效應電晶體或垂直雙擴散金屬氧化物半導體場效應電晶體。
  8. 根據申請專利範圍第7項所述的功率元件，其中，該縱向超級接面金屬氧化物場效應電晶體由溝槽填充程序 製造。
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