TWI517394B - 供半導體應用之含正電性金屬的層 - Google Patents

供半導體應用之含正電性金屬的層 Download PDF

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TWI517394B
TWI517394B TW101132364A TW101132364A TWI517394B TW I517394 B TWI517394 B TW I517394B TW 101132364 A TW101132364 A TW 101132364A TW 101132364 A TW101132364 A TW 101132364A TW I517394 B TWI517394 B TW I517394B
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metal
group
layer
substrate
precursor molecule
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TW101132364A
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TW201327827A (zh
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派翠希歐 羅梅洛
史考特 克蘭德寧
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英特爾股份有限公司
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description

供半導體應用之含正電性金屬的層
本發明之具體例通常係關於積體電路裝置、半導體裝置、金屬互連、電晶體、正形的膜、原子層沉積程序、化學氣相沉積程序、及化學沉積程序。
向著更小更高積體電路(IC)及其他半導體裝置的進展對於構成該等裝置所使用之技術及材料有極大需求。通常，積體電路晶片也稱為微晶片、矽晶片、或晶片。IC晶片在多種普通裝置中發現，諸如在電腦、汽車、電視、CD播放機、及手機中的微處理器。多個IC晶片一般被建構在矽晶圓(一種具有例如300毫米直徑之薄的矽碟)上且在處理後切割該晶圓以產生個別的晶片。具有約90奈米特徵尺寸周長(feature sizes around)之1平方公分的IC晶片可包含數億個組件。現今之技術正推向甚至小於45奈米之特徵尺寸。IC晶片之組件包括例如電晶體諸如CMOS(互補金屬氧化物半導體)裝置、電容結構體、電阻結構體、及在各組件及各外部裝置間提供電子連接之金屬線。其它半導體裝置包括例如多種二極體、雷射、光學偵測器、及磁場感應器。
為供包含正電性金屬元素之半導體裝置的製造，正電 性金屬及高正電性金屬之沉積因為有不良因素之結合而出現困難。該等不良因素包括還原該等正電性金屬所需之極高的能量及大部分之正電性金屬對碳、氮、及氧之高親合性。使用CVD(化學氣相沉積)或ALD(原子層沉積)程序沉積正電性金屬可導致非所欲之非化學計量的二相及三相(諸如金屬-氧化物、-氮化物、-碳化物、或這些物質之組合物)的沉積。碳、氮、及/或氧常是非所欲之成分，彼可使所要之由一或多種之正電性金屬組成的膜的效能變差。
本發明之具體例提供使用ALD及/或CVD程序形成包含正電性金屬之層的方法，形成包含一或多種正電性金屬之層的方法，及形成包含多個包含一或多種正電性金屬之層的半導體裝置的方法。在本發明之具體例中，該膜是薄的或超薄的(少於100埃厚度之膜)及/或正形膜。有利地，依照本發明之具體例的膜並不包括明顯量之碳、氮、及氧。在本發明之具體例中，包含正電性金屬之膜包含總量少於15原子%之碳、氮、及氧雜質。
通常，原子層沉積(ALD)是一種用在半導體處理工業中的技術，一般用以沉積超薄正形膜。在一般的ALD程序中，待塗覆膜之基材表面係連續地曝於氣相反應物(先質)中。該表面重複曝於該反應物將在該表面上連續產生薄的正形產物層。在該表面曝於每一氣相反應物之後，將反應物氣體及反應副產物從反應室清除。
通常，化學氣相沉積(CVD)是一種用以在基材表面 上產生膜層的方法。在CVD程序中，基材表面曝於揮發性反應物先質，後者在該基材表面上進行反應且形成所要之膜材料。可以使用ALD及CVD以沉積多種形式之材料，包括例如單晶、多晶、非晶、及磊晶膜。CVD及ALD程序一般係在特化裝置一部分的真空室中進行。
圖1A描述在基材上形成包含一或多種正電性金屬之層的ALD方法。依照本發明之具體例的膜沉積程序能將薄的正形膜沉積在基材上，該基材具有多個微米及奈米級特徵結構及多種具有高縱橫比之微米及奈米級特徵結構。在圖1A中，其上將沉積薄的正形膜的基材表面係在該膜沉積程序中隨意地加熱。在本發明之具體例中，該基材在沉積期間經加熱至至少高於室溫。即使需要最少之熱能以供該沉積，加熱可能維持一致的沉積條件。該膜沉積程序可在相對低溫下進行，例如沉積可在介於30及500℃之溫度下進行。
該基材表面曝於包含正電性金屬之第一先質分子。在本發明之具體例中，該正電性金屬是選自元素週期表2-7族之金屬及/或鋁。在本發明之具體例中，正電性金屬是諸如Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W、及Mn之金屬。該第一先質分子包含直接之金屬-矽及/或金屬-鍺鍵結。在本發明之具體例中，該第一先質分子包含1或2個金屬原子且該金屬原 子是相同之金屬原子或二種不同之金屬原子。包含金屬-矽及/或金屬-鍺直接鍵結之該第一先質分子的金屬中心可隨意地具有經由N、P、O、或S原子所結合之配位的路易士鹼。藉由例如利用惰性氣體諸如氮、氦、氖、氬、氪、或氙沖洗該進行沉積之真空室，移除不在表面上之任何先質分子(及可能存在之任何其他氣態物質)。然後使基材表面曝於第二先質分子(共反應物)。該第二先質分子是揮發性MXn化合物，其中X是鹵素或含氧之配位基且n是介於且包括2及6的數目。使用包含金屬-矽及/或金屬-鍺直接鍵結之正電性金屬以沉積膜的反應圖解顯示於式(1)中。
在式(1)中，m及n是介於且包括2及6的數目，R1、R2、及R3是相同或不同的且是烴基或包含一或多個雜原子(諸如鹵素、O、N、S、P、Si及/或Ge)之烴基，X是鹵素或烷氧基(-OR，其中R是烴或含雜原子之烴，諸如烷基或含雜原子之烷基)，E是矽及/或鍺，M1及M2是選自元素週期表2-7族及/或鋁之正電性金屬，且p是1或2，且當p是2時，該包含分子(M1)p-(ER1R2R3)m之正電性金屬可以是相同或不同的。烴包括例如分枝及未分枝之烷基、芳基、環烷基、烯類、炔類、環狀基團、及多環基團。金屬M1及M2可以是相同的金屬或不同的金屬。在本發明之具體例中，M1及M2是金屬，諸如Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、 W、及Mn。有用的鹵素包括氟、氯、溴、及碘。正在成長之膜中，金屬-金屬鍵結之形成及揮發性產物(R1-3)3EX之形成是驅使反應向前之因素。也可能以氣態反應物與惰性氣體(諸如氮、氦、氖、氬、氪、或氙)之混合物形式將反應物及/或共反應物供應至該室。
然後，任何殘留之氣態共反應物及氣態反應產物藉由例如利用惰性氣體(諸如氬或氮)沖洗該室而由該室移除。將該基材表面曝於第一反應物、移除任何未黏附至該基材表面的殘留氣態反應物、將該基材曝於共反應物、及由該室移除任何氣態共反應物(及氣態反應產物)等步驟重複多次。這些步驟重複次數取決於在該基材表面上所得之正電性金屬層的所要厚度。該等步驟可僅進行一次或進行多次。
圖1B描述用於形成包含正電性金屬之層在基材上的另外的方法。依照本發明之具體例的膜沉積程序能將薄的正形膜沉積在基材上，該基材具有多種微米及奈米級特徵結構及多種具有高縱橫比之微米及奈米級特徵結構。在圖1B中，將在其上沉積薄的正形膜的基材表面係在該膜沉積期間隨意地被加熱。在本發明之具體例中，該基材在沉積期間至少被加熱至高於室溫。即使該沉積需要最少熱能，加熱可能維持一致的沉積條件。該膜沉積程序可在相對低溫下進行，例如沉積可在介於30及500℃之溫度下進行。
該基材表面係曝於包含正電性金屬之第一先質分子。 在本發明之具體例中，該正電性金屬是選自元素週期表2-7族之金屬及/或鋁。在本發明之具體例中，正電性金屬是諸如Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W、及Mn之金屬。該第一先質分子包含直接之金屬-矽及/或金屬-鍺鍵結。在本發明之具體例中，該第一先質分子包含1或2個金屬原子且該金屬原子是相同之金屬原子或不同之金屬原子混合。包含金屬-矽及/或金屬-鍺直接鍵結之該第一先質分子的金屬中心可隨意地具有經由N、P、O、或S原子所結合之配位的路易士鹼。藉由例如利用惰性氣體沖洗該進行沉積之真空室，移除任何殘留之氣態先質分子(及可能存在之任何其他氣態物質)。然後基材表面曝於第二先質分子(共反應物)。該第二反應物是氫。使用包含金屬-矽及/或金屬-鍺直接鍵結之正電性金屬以沉積膜的反應圖解顯示於式(2)中。
在式(2)中，m是介於且包括2及6的數目，E是矽及/或鍺，R1、R2、及R3是相同或不同的且是烴基或包含一或多個雜原子(諸如鹵素、O、N、S、P、Si及/或Ge)之烴基，M是選自元素週期表2-7族及/或鋁之正電性金屬，且p是1或2，且當p是2或3時，該包含分子Mp-(ER1R2R3)m之正電性金屬可以相同或不同。烴包括例如分枝及未分枝之烷基、芳基、環烷基、烯類、炔類、環狀基團、及多環基團。在本發明之具體例中，Mp是一或 多種金屬，諸如Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W、及Mn。在膜沉積中可以使用任何普遍形式之氫，例如有利用或無利用電漿活化及存在或不存在另外之惰性氣體(諸如氮、氦、氖、氬、氪、或氙)之分子氫。在該基材表面上形成反應性金屬氫化物鍵結。在該ALD程序之熱條件下，金屬氫化物分解成分子氫及金屬。反應產物從該表面清除而留下超薄金屬層。
然後，任何殘留之氣態共反應物及氣態反應產物藉由例如利用惰性氣體(諸如氬或氮)沖洗該室而由該室移除。將該基材表面曝於第一反應物、移除任何未黏附至該基材表面的殘留氣態反應物、將該基材曝於共反應物、及由該室移除任何氣態共反應物(及氣態反應產物)等步驟重複多次。這些步驟的重複次數取決於在該基材表面上所得的正電性金屬層的所要厚度。這些步驟也可僅進行一次。
在圖1A及1B之替代具體例中，進行更類似於CVD之技術，且若有該氣態反應物及共反應物，則彼等係同時提供至基材表面以形成正電性金屬層。在另外之替代具體例中，殘留之氣態反應物及共反應物及氣態產物由該室移除，供應氣態反應物及共反應物至該基材表面的程序係重複多次以產生具有所要厚度之層。
在本發明之具體例中，包含正電性金屬之膜在曝於任何潛在氧化劑(例如曝於空氣)之前具有金屬態(零氧化 狀態)之正電性金屬。若該膜不受氧化劑侵襲，則該正電性金屬仍處於零氧化狀態。
圖2A-F顯示在本發明之具體例中有用的先質分子。包含正電性金屬、1-2個金屬、金屬-矽及/或金屬-鍺直接鍵結、及其他鍵結至Si及/或Ge之官能基的其他先質分子也是可能的。在圖2A-F中，在該官能基-ER1R2R3內，R1、R2、及R3是相同或不同的且是烷基、芳基、包含在E與主要基團元素(諸如Si、Ge、N、P、O或S)或雜環基團之間的直接鍵結的基團，且E是Si或Ge。在圖2A中，M1是正電性金屬，例如Be、Mg、或Ca。在圖2B-E中，M2是正電性金屬，例如Ti、Sc、或Y，E是矽或鍺。在圖2F中，M3是正電性金屬，例如Ti、Zr或Hf，E是矽或鍺。在本發明之實例中，R是甲基。在本發明之另一具體例中，-ER1R2R3包含二個甲基及苯甲基作為R官能基。在本發明之另一具體例中，先質分子是((CH3)3Si)3Al：N(CH3)2(CH2CH3)、((CH3)2ArSi)3Al：N(CH3)2(CH2CH3)、((CH3)3Si)3Al(啶)、((CH3)3Ge)3Al(啶)、((C4H9)3Si)2Mn、((C4H9)3Si)2Mn．N(CH3)3、((CH3)3Ge)2Mn(tmeda)及((C4H9)3Si)2Ti．N(CH3)3，其中Ar是隨意包含一或多個雜原子之芳族或烴基團且「tmeda」是四甲基乙二胺。
依照本發明之具體例的程序可用以產生超薄金屬層，其係在例如平面、三閘、及疊合之奈米線電晶體裝置及互 連件(通孔及線)內的閘電極及源極/汲極接點應用中作為阻障物、晶種層、襯裡、覆層，及/或作為一級傳導互連金屬之正形層。依照本發明之具體例的方法有用以例如沉積NMOS工作功能金屬、NMOS金屬擴散阻障物、PMOS工作功能金屬、及/或黏合/襯裡層。依照本發明之具體例的金屬層具有低濃度之Si及/或Ge的存在，由於使用包含金屬-矽及/或金屬-鍺直接鍵結而用以形成該膜之先質。在依照本發明之具體例的膜中所存在的Si及/或Ge的濃度範圍介於0.5及10.0原子%之間。再另一具體例中，在膜中所存在之Si及/或Ge的濃度範圍介於2及15原子%之間，或2及8原子%之間。
在本發明之另外具體例中，產生包含正電性金屬之金屬層，其在該層中具有較高濃度之Si及/或Ge。一般，使用CVD程序以產生具有較高Si及/或Ge含量的金屬矽化物及/或金屬鍺化物膜。例如，TiSi是在半導體製造中所用而依照本發明之具體例所產生之傳導性材料。在依照本發明之另外具體例的正電性金屬膜中所存在之Si及/或Ge的濃度範圍介於10.0至67原子%之間。
圖3A-I顯示在本發明之具體例中有用的另外的先質分子。包含2-7族金屬及/或Al之不同組合物、包含1至2個金屬原子、及連結至該Si及/或Ge的不同官能基的其他先質分子是可能的。
圖4提供簡化的三閘電晶體結構。在圖4中，絕緣基材405包含閘電極410及源極415及汲極420區。該絕緣 基材405係由例如半導體基材組成，絕緣材料層(諸如SiO2)形成在該半導體基材上。通道區430的三邊上具有閘介電區425及閘電極區410。閘電極區410係由依本發明之具體例的金屬層組成。例如使用在本文中所述之使薄的正形膜能沉積的方法，至少部分地形成該閘電極區410。這些金屬層具有低濃度之Si及/或Ge存在，在該先質分子中所含之濃度範圍是介於0.5及10.0原子%(或介於2及15原子%，或2及8原子%)之Si或Ge及99.5-75.0原子%(或98-70原子%，或98-72原子%)之一或多種2-7族金屬或Al。在已經沉積該正形層後，該電極區可隨意地使用不同沉積程序(諸如利用不同先質之ALD或CVD程序)填充導電材料。隨意地，黏合層及/或阻障層(未顯示)係介於該閘電極區425及該閘電極區410之間。該源極415及該汲極420區係由例如導電P-或N-型半導體材料形成。閘介電層425是絕緣材料，例如二氧化矽(SiO2)、氧氮化矽(SiOxNy)、氮化矽(Si3N4)。該閘介電層425也可以是高k閘介電材料，例如介電金屬氧化物。該通道區430可包含例如摻雜或未摻雜之矽、單晶矽、矽及鍺之混合物、或III-V族化合物半導體(一種包含週期表之III及V(或13及15)族元素的化合物)，例如砷化銦鎵(InGaAs)、磷化銦(InP)、及砷化銦鋁(InAlAs)。通常，三閘電晶體結構具有三邊被閘介電物及閘電極環繞的通道區。所繪製之特徵結構的其他構形及形狀對於三閘電晶體而言也是可能的，例如具有不 同形狀之源極及汲極區。另外，電晶體具有其他相關之特徵結構，其為簡化之故並未繪製。例如，該閘電極區一般部分地藉由絕緣間隔件(spacer)所限定，該電晶體結構可被覆蓋在絕緣材料中且導電通孔將該源極及汲極連接至其他裝置及該容納該電晶體之半導體晶片區。在本發明之另外具體例中，該導電通孔(未顯示)具有墊在該接點內側之金屬層，該金屬層具有低濃度之Si或Ge存在，濃度範圍介於0.5及10.0原子%(或介於2及15原子%，或介於2及8原子%)之Si或Ge。在本發明之另外具體例中，膜包含低濃度之Si或Ge，在該先質分子中所存在之濃度範圍介於0.5及10.0原子%(或2及15原子%，或2及8原子%)之Si或Ge及99.5-75.0原子%(或98-70原子%，或98-72原子%)之一或多種2-7族金屬及/或鋁。在本發明之另外具體例中，膜包含低濃度之Si或Ge，在該先質分子中所存在之濃度範圍介於0.5及10.0原子%(或2及15原子%，或2及8原子%)之Si或Ge及99.5-75.0原子%(或98-70原子%，或98-72原子%)之一或多種2-7族金屬及/或鋁，及總量低於15原子%的碳、氮、及氧雜質。在本發明之另外具體例中，依照本文所述之方法形成該墊在該接點內部之層。此層可沉積在介於該源極/汲極區與該接點金屬間的薄擴散阻障層上方。
圖5A-C說明疊合之奈米線電晶體裝置。圖5A之概圖顯示半個疊合之奈米線電晶體裝置以促進說明。圖5B係以已相對圖5A中之視圖旋轉45°的透視圖方式代表圖 5A之裝置且閘介電層及閘金屬現已包括在圖5B中。圖5C顯示經疊合之奈米電晶體裝置，其沿著相對圖5A之切面旋轉90°的平面被切割，且該裝置本身已旋轉-45°。在圖5A中，基材505容納絕緣間隔件510及源極/汲極區515。經說明為二通(two per)電晶體之奈米線通道區520係與該源極/汲極區515接觸。奈米線通道區520包含例如矽、矽及鍺、或III-V族化合物半導體，例如砷化銦鎵(InGaAs)、磷化銦(InP)、及砷化銦鋁(InAlAs)。在圖5B-C中，閘介電材料525設置在通道區520上且閘電極區530設置在該閘介電材料525上。該閘介電材料525是絕緣材料，諸如二氧化矽(SiO2)、氧氮化矽(SiOxNy)、氮化矽(Si3N4)、或高k介電材料。如本文中所述之程序可用來沉積一環繞該閘介電材料525之薄的正形金屬層535。該薄的正形金屬層535含有低濃度之Si或Ge，濃度範圍介於0.5及10.0原子%(或介於2及15原子%，或介於2及8原子%)之Si或Ge。在本發明之另外具體例中，膜包含低濃度之Si或Ge，其在該先質分子中所存在之濃度範圍介於0.5及10.0原子%(或介於2及15原子%，或介於2及8原子%)之Si或Ge及99.5-75.0原子%(或98-70原子%，或98-77原子%)之一或多種2-7族金屬及/或鋁。在本發明之另外具體例中，膜包含低濃度之Si或Ge，在該先質分子中所存在之濃度範圍介於0.5及10.0原子%(或2及15原子%，或2及8原子%)之Si或Ge及99.5-75.0原子%(或98-70原子 %，或98-72原子%)之一或多種2-7族金屬及/或鋁，及總量低於15原子%的碳、氮、及氧雜質。殘留之閘電極區530可包含與該薄的正形金屬層535相同之金屬或不同的導電物質且可藉由相同的方法或不同的方法沉積。在另一具體例中，該閘電極區530可包含例如材料，諸如Ti、W、Ta、Al、及其合金、及其與稀土元素(諸如Er、Dy)或貴金屬(諸如Pt)之合金、及氮化物(諸如TaN、及TiN)。隨意地，黏合及/或阻障層(未顯示)係介於該閘介電材料區525與該閘電極區530之間。用於所說明之特徵結構的其他構形及形狀對於疊合之奈米線電晶體也是可能的，諸如具有不同數目之奈米線電晶體者(諸如一、二、或三或更多條奈米線)及不同形狀之源極及汲極區。
通常，高k介電材料是一種具有介電常數大於SiO2之介電常數的介電材料。SiO2之介電常數是3.9。例示之高k介電材料包括二氧化鉿(HfO2)、氧化鉿矽、氧化鑭、氧化鑭鋁、二氧化鋯(ZrO2)、氧化鋯矽、二氧化鈦(TiO2)、五氧化鉭(Ta2O5)、氧化鋇鍶鈦、氧化鋇鈦、氧化鍶鈦、氧化釔、氧化鋁、氧化鉛鈧鉭、鈮酸鉛鋅、及在半導體技術中已知的其他材料。
在本發明之另外具體例中，使用依照本發明之具體例的程序以沉積用於BEOL(線後端)互連應用之金屬。這些應用包括黏合層、襯裡、阻障物、及用於減少電移動之覆蓋層、及互連金屬本身。圖6說明金屬互連結構，諸如溝或通孔。在圖6中，基材605容納金屬溝或通孔610。 該金屬溝或通孔610係在絕緣層615內，該絕緣層係例如介電中間層(ILD)。介電材料包括低k介電材料及二氧化矽。隨意之層620是一種由介電材料(諸如氮化矽、氧氮化矽、及二氧化矽)組成之蝕刻停止(etchstop)層。阻障層625使金屬溝或通孔610與該介電層615及620分開。該結構隨意地也包括覆蓋層635，其將金屬溝或通孔610與沉積在金屬溝或通孔610上方之另外的介電層640(諸如ILD)分開。該金屬溝或通孔610隨意地電連接至下方之第二金屬溝或通孔645。金屬溝或通孔610及645係由例如銅、鋁、銀、及其合金組成。另外隨意地，圖6之結構包含該覆蓋層635，但有一不同的阻障層625或無阻障層625。在本發明之具體例中，金屬溝或通孔610及640係由銅組成。在本發明之具體例中，阻障層625可包含W、Hf、及/或Ta，且用於減少電移動之金屬覆蓋層635可包含W。W、Hf、及/或Ta之薄的正形層依照本發明之具體例沉積在介電中間層(ILD)(其係例如由介電材料諸如低k材料或SiO2組成)上方，然後在電鍍之前塗覆ALD Cu膜。覆蓋層可以選擇性地沉積在與介電表面相關之經暴露的金屬表面。在介電表面上之原子層沉積可以經由其表面官能化作用，利用薄的有機膜(其包括但不限於自發組合之單層及胺基(有機)矽烷)抑制。如先前討論的，依照本發明之具體例之在沉積後未經改質的正電性金屬膜具有低濃度之Si或Ge存在，濃度範圍介於0.5及10.0原子%(或介於2及15原子%，或介於2及8原子 %)之Si或Ge。在本發明之另外具體例中，膜包含低濃度之Si或Ge，在該先質分子中所存在之濃度範圍介於0.5及10.0原子%(或介於2及15原子%，或介於2及8原子%)之Si或Ge及99.5-75.0原子%(或98-70原子%，或98-72原子%)之一或多種2-7族金屬及/或鋁(例如W、Hf、及/或Ta)。在本發明之另外具體例中，膜包含低濃度之Si或Ge，在該先質分子中所存在之濃度範圍介於0.5及10.0原子%(或2及15原子%，或2及8原子%)之Si或Ge及99.5-75.0原子%(或98-70原子%，或98-72原子%)之一或多種2-7族金屬及/或鋁，及總量低於15原子%的碳、氮、及氧雜質。
一般用於介電層、特徵結構、及/或介電中間層(ILD)之介電材料包括二氧化矽及低k介電材料。可用之另外的介電材料包括摻雜碳之氧化物(CDO)、氮化矽、有機聚合物諸如全氟環丁烷或聚四氟乙烯、氟矽酸鹽玻璃(FSG)、及/或有機矽酸鹽諸如矽倍半氧烷、矽氧烷、或有機矽酸鹽玻璃。該介電層可包括孔(pores)以進一步減低介電常數。
在本文中所示之裝置的組件可包含另外的層，諸如襯裡及將包含不同材料(例如金屬層與絕緣層)的層分開的黏合層，且例如依照構成該裝置時所用之製造方法及該裝置之所要性質，為簡化之故說明為單一層之組件可包含相同或不同材料之多個層。
本發明之實施係容納在基材上，諸如半導體基材。可 形成依照本發明之具體例的正電性金屬層於其上的基材表面包括例如H終端之矽、二氧化矽、矽、矽鍺、III-V族(或另一週期表欄編碼方式中的13-14族)化合物半導體、主族氧化物、金屬、及/或二元或混合氧化物。各層或包含裝置之層也可描述為該基材或部分的該基材，其上製造本發明之具體例。其上建構半導體裝置之基材主體一般是半導體晶圓，其經割開以產生個別IC晶片。其上建構晶片之基材主體一般是矽晶圓，雖然本發明之具體例與所用之基材形式無關。該基材也可由鍺、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵、銻化鎵、及/或其他III-V族材料(其為單獨或與矽或二氧化矽之組合物)或其他絕緣材料組成。
圖7說明依照本發明之實施的計算裝置1000。該計算裝置1000容納主機板1002。該主機板1002可包括多個組件，包括但不限於處理器1004及至少一個通信晶片1006。該處理器1004經物理及電性地偶合至該主機板1002。在某些實施中，該至少一個通信晶片1006也經物理及電性地偶合至該主機板1002。
計算裝置1000依照其應用可包括其他可以或可以不經物理及電性地偶合至該主機板1002的組件。這些其他組件包括但不限於依電性記憶體(例如DRAM)、非依電性記憶體(例如ROM)、圖像處理器、數位訊號處理器、密碼處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、聲訊編碼/解碼器、影像編碼/ 解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速度計、迴轉儀、揚聲器、相機、及大量儲存裝置(諸如硬碟驅動器、光碟(CD)、數位光碟(DVD)等等)。
通信晶片1006令用於數據傳遞之無線通信能往返於該計算裝置1000。可以使用用詞“無線”及其衍生詞以描述可經由調控的電磁輻射的使用，通過非固態媒介傳送數據的電路、裝置、系統、方法、技術、通信頻道等。該用詞並不意謂相關裝置不含有任何電線，雖然在某些具體例中，彼可以不含有。該通信晶片1006可以實施很多無線標準或協定之任一者，包括但不限於Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、長期演進技術(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生者、以及定名為3G、4G、5G以上的任何其他無線協定。該計算裝置1000可包括多個通信晶片1006。例如，第一通信晶片1006可專用於較短範圍之無線通信，諸如Wi-Fi及藍牙，而第二通信晶片1006可專用於較長範圍之無線通信，諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其他者。
該計算裝置1000之處理器1004包括封裝在該處理器1004內之積體電路晶粒。在本發明之一些實施中，該處理器之積體電路晶粒包括依照本發明之實施所形成之一或多種裝置，諸如電晶體及/或金屬互連。用詞“處理器”可以 指明任何裝置或裝置之部分，彼處理來自暫存器及/或記憶體之電子數據以將該電子數據變成可儲存於暫存器及/或記憶體中的其他電子數據。
該通信晶片1006也包括封裝在該通信晶片1006內之積體電路晶粒。依照本發明之其它實施，該通信晶片之積體電路晶粒包括一或多種依照本發明之實施所形成之裝置，諸如電晶體及/或金屬互連。
在另一實施中，在該計算裝置1000內所容納之其它組件可含有積體電路晶粒，其包括一或多種依照本發明之實施所形成之裝置，諸如電晶體及/或金屬互連。
在多種實施中，該計算裝置1000可以是膝上型電腦、易網機(netbook)、筆記型電腦、智慧型手機、輸入板(tablet)、個人數位助理(PDA)、及超行動PC、手機、桌上型電腦、伺服器、印表機、掃瞄器、監視器、機上盒、娛樂控制單元、數位相機、可提音響、或數位錄影機。在另一實施中，該計算裝置1000可以是處理數據的任何其他電子裝置。
在先前描述中列出很多特定細節，諸如對於電晶體、互連、及材料系統的布局，以對本發明之具體例提供通盤了解。精於此技術之人士會明瞭：本發明之具體例可以在沒有這些特定細節之狀況下進行。在本發明之其它具體例中，沒有詳細描述習知的特徵，諸如積體電路設計布局，以致不會不必要地混淆本發明之具體例。另外，要了解：在圖中所顯示之各種具體例是說明性的表示且不一定是按 比例繪製的。
精於相關技術之人士領會：通過整個揭示及多種所顯示及描述之組件的結合及取代，改良及變化是可能的。整個此說明書中“一個具體例”之引用意指：與該具體例相關所描述之特別的特徵、結構、材料、或特性被包括在本發明之至少一個具體例中，但不必要指明彼出現在每一具體例中。另外，在該等具體例中所揭示之特別的特徵、結構、材料、或特性可在一個以上之具體例中以任何合適方式被結合。在其他具體例中可以包括多種另外的層及/或結構及/或可以省略所描述之特徵。
405‧‧‧絕緣基材
410‧‧‧閘電極
415‧‧‧源極
420‧‧‧汲極
425‧‧‧閘介電層
430‧‧‧通道區
505‧‧‧基材
510‧‧‧絕緣間隔件
515‧‧‧源極/汲極區
520‧‧‧奈米線通道區
525‧‧‧閘介電材料/區
530‧‧‧閘電極區
535‧‧‧薄的正形金屬層
605‧‧‧基材
610‧‧‧通孔
615‧‧‧絕緣層
620‧‧‧蝕刻停止層
625‧‧‧阻障層
635‧‧‧覆蓋層
640‧‧‧通孔
645‧‧‧金屬溝或通孔
1000‧‧‧計算裝置
1002‧‧‧主機板
1004‧‧‧處理器
1006‧‧‧通信晶片
圖1A-B圖示有用於形成包含正電性金屬之薄的正形膜在基材表面上的方法。
圖2A-F說明一些有用於本發明之具體例的先質分子。
圖3A-I說明另外之有用於本發明之具體例的例示的先質分子。
圖4是說明三閘電晶體裝置的概略圖示。
圖5A-C是說明堆疊之奈米線電晶體裝置的概略圖示。
圖6說明金屬互連結構。
圖7是依照本發明之實施所建構之計算裝置。
505‧‧‧基材
510‧‧‧絕緣間隔件
515‧‧‧源極/汲極區
520‧‧‧奈米線通道區

Claims (38)

  1. 一種奈米線電晶體裝置，其包含形成該電晶體裝置之通道區的懸吊的奈米線、設置在該懸吊的奈米線上的介電材料層、設置在該介電材料層上之金屬層，其中該金屬層包含99.5-75.0原子%之2-7族金屬或Al及Si或Ge，Si或Ge之存在量介於0.5及10.0原子%之間，其中該奈米線係懸吊在閘電極中且該金屬層形成該閘電極的部份。
  2. 如申請專利範圍第1項之裝置，其中該金屬層包含總量少於15原子%的碳、氮、及氧。
  3. 如申請專利範圍第1項之裝置，其中該介電材料層包含二氧化矽(SiO2)、氧氮化矽(SiOxNy)、氮化矽(Si3N4)、或高k介電材料。
  4. 如申請專利範圍第1項之裝置，其中該奈米線係包含矽、矽及鍺之混合物、或III-V族化合物半導體。
  5. 如申請專利範圍第1項之裝置，其中該裝置包含二條懸吊的奈米線。
  6. 一種電晶體裝置，其包含通道結構，該通道結構具有頂部表面及一對側向相對之側壁、設置在該頂部表面及該對側向相對之側壁上的介電層、及設置在該在頂部表面及該對側向相對之側壁上之介電層上的金屬層，其中該金屬層包含99.5-75.0原子%之2-7族金屬或Al及Si或Ge，Si或Ge之存在量介於0.5及10.0原子%之間。
  7. 如申請專利範圍第6項之裝置，其中該金屬層包含總量少於15原子%的碳、氮、及氧。
  8. 如申請專利範圍第6項之裝置，其中該介電材料層包含二氧化矽(SiO2)、氧氮化矽(SiOxNy)、氮化矽(Si3N4)、或高k介電材料。
  9. 如申請專利範圍第6項之裝置，其中該通道結構包含單晶矽、矽、矽及鍺之混合物、或III-V族化合物半導體。
  10. 一種半導體裝置，其包含具有一表面之基材，設置在該基材表面上之介電材料層，在該介電材料層中所形成之溝或通孔，該溝或通孔具有側壁及底部表面，設置在該側壁及底部表面上之阻障層，其中該阻障層包含99.5-75.0原子%之2-7族金屬及Si或Ge，Si或Ge之存在量介於0.5及10.0原子%之間，及在井內之金屬區，其中該阻障層是在該金屬區與該介電材料層之間。
  11. 如申請專利範圍第10項之裝置，其中該2-7族金屬是W、Hf、Ta或其混合物。
  12. 如申請專利範圍第10項之裝置，其中該金屬層包含總量少於15原子%的碳、氮、及氧。
  13. 如申請專利範圍第10項之裝置，其中該金屬區包含銀、銅、或鋁。
  14. 一種半導體裝置，其包含具有一表面之基材， 設置在該基材表面之介電材料層，在該介電材料層中所形成之溝或通孔，在該溝或通孔內之金屬區，其中該金屬區具有一表面，及設置在該金屬區表面上的覆蓋層，其中該覆蓋層包含99.5-75.0原子%之2-7族金屬及Si或Ge，Si或Ge之存在量介於0.5及10.0原子%之間。
  15. 如申請專利範圍第14項之裝置，其中2-7族金屬是W。
  16. 如申請專利範圍第14項之裝置，其中該金屬層包含總量少於15原子%的碳、氮、及氧。
  17. 如申請專利範圍第14項之裝置，其中該金屬區包含銀、銅、或鋁。
  18. 一種用於形成含正電性金屬的層之方法，其包含提供具有表面之基材，將該基材表面曝於氣相第一先質分子中，其中該第一先質分子包含金屬M1，其中該金屬M1是2-7族金屬或Al且該金屬M1直接鍵結至至少二個矽、鍺或矽及鍺原子，移除任何殘留之氣態第一先質分子，將該基材表面曝於第二氣相先質分子M2Xn，其中X是鹵素且n是介於且包括2及6的數目，M2是2-7族金屬或Al，且M1及M2是相同之金屬或不同之金屬，移除任何殘留之氣態第二先質分子，及將該基材曝於於該第一先質分子、移除任何氣態第一 先質分子、將該基材曝於該第二先質分子、及移除任何殘留之氣態第二先質分子等步驟重複至少一次，以在該基材表面上產生包含M1及M2之層。
  19. 如申請專利範圍第18項之方法，其中M1及M2是選自Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W、及Mn。
  20. 如申請專利範圍第18項之方法，其中該第一先質分子包含二個2-7族金屬原子或Al。
  21. 如申請專利範圍第18項之方法，其中該第一先質分子係選自((CH3)3Si)3Al．N(CH3)2(CH2CH3)、((CH3)2ArSi)3Al．N(CH3)2(CH2CH3)、((CH3)3Si)3Al(啶)、((CH3)3Ge)3Al(啶)、((C4H9)3Si)2Mn、((C4H9)3Si)2Mn．N(CH3)3、((CH3)3Ge)2Mn(四甲基乙二胺)及((C4H9)3Si)2Ti．N(CH3)3。
  22. 如申請專利範圍第18項之方法，其中M1係鍵結至至少二個官能基，其為-SiR1R2R3、-GeR1R2R3、或其混合物，其中R1、R2及R3是烷基(其係相同或不同且選自含雜原子及含非雜原子之烷基)、芳基、環烷基、烯、炔、環及多環基團，其中該雜原子係選自鹵素、O、N、S、P、Si、及Ge。
  23. 如申請專利範圍第18項之方法，其中M1是Al、Ti、Sc、Y、Zr、或Hf且M1係鍵結至至少三個官能基，其為-SiR1R2R3、-GeR1R2R3、或其混合物，其中R1、R2及R3是烷基，其係相同或不同且選自烷基、芳基、環烷基、 烯、炔、環及多環基團，其中該雜原子係選自鹵素、O、N、S、P、Si、及Ge。
  24. 一種用於形成含正電性金屬的層之方法，其包含提供具有表面之基材，將該基材表面曝於氣相第一先質分子中，其中該第一先質分子包含金屬M1，其中該金屬M1是2-7族金屬或Al且該金屬M1直接鍵結至至少二個矽、鍺或矽及鍺原子，移除任何殘留之氣態第一先質分子，將該基材表面曝於第二氣相先質分子M2Xn，其中X是烷氧基(alkoxide group)且n是介於且包括2及6的數目，M2是2-7族金屬或Al，且M1及M2是相同之金屬或不同之金屬，移除任何殘留之氣態第二先質分子，及將該基材曝於於該第一先質分子、移除任何氣態第一先質分子、將該基材曝於該第二先質分子、及移除任何殘留之氣態第二先質分子等步驟重複至少一次，以在該基材表面上產生包含M1及M2之層。
  25. 如申請專利範圍第24項之方法，其中M1及M2是選自Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W、及Mn。
  26. 如申請專利範圍第24項之方法，其中該第一先質分子包含二個2-7族金屬原子或Al。
  27. 如申請專利範圍第24項之方法，其中該第一先質分子係選自((CH3)3Si)3Al．N(CH3)2(CH2CH3)、 ((CH3)2ArSi)3Al．N(CH3)2(CH2CH3)、((CH3)3Si)3Al(啶)、((CH3)3Ge)3Al(啶)、((C4H9)3Si)2Mn、((C4H9)3Si)2Mn．N(CH3)3、((CH3)3Ge)2Mn(四甲基乙二胺)及((C4H9)3Si)2Ti．N(CH3)3。
  28. 如申請專利範圍第24項之方法，其中M1係鍵結至至少二個官能基，其為-SiR1R2R3、-GeR1R2R3、或其混合物，其中R1、R2及R3是烷基，其係相同或不同且選自烷基、芳基、環烷基、烯、炔、多環基團。
  29. 如申請專利範圍第24項之方法，其中M1是Al、Ti、Sc、Y、Zr、或Hf且M1係鍵結至至少三個官能基，其為-SiR1R2R3、-GeR1R2R3、或其混合物，其中R1、R2及R3是烷基，其係相同或不同且選自烷基、芳基、環烷基、烯、炔及多環基團。
  30. 一種用於形成含正電性金屬的層之方法，其包含提供具有表面之基材，將該基材表面曝於先質分子中，其中該先質分子包含金屬，其中該金屬是2-7族金屬或Al且該金屬直接鍵結至至少二個矽、鍺或矽及鍺原子，移除任何殘留之氣態先質分子，將該基材表面曝於氫，移除任何殘留之氫及氣態反應產物，及將該基材曝於於該先質分子、移除任何氣態先質分子、將該基材曝於氫、及移除任何氫及氣態反應產物等步驟重複多次，以在該基材表面上產生包含該金屬之層。
  31. 如申請專利範圍第30項之方法，其中該金屬是選自Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W、及Mn。
  32. 如申請專利範圍第30項之方法，其中該先質分子包含二個2-7族金屬原子或Al。
  33. 如申請專利範圍第30項之方法，其中以氫分子或經電漿活化之氫形式供應氫。
  34. 如申請專利範圍第30項之方法，其中該先質分子係選自((CH3)3Si)3Al．N(CH3)2(CH2CH3)、((CH3)2ArSi)3Al．N(CH3)2(CH2CH3)、((CH3)3Si)3Al(啶)、((CH3)3Ge)3Al(啶)、((C4H9)3Si)2Mn、((C4H9)3Si)2Mn．N(CH3)3、((CH3)3Ge)2Mn(四甲基乙二胺)及((C4H9)3Si)2Ti．N(CH3)3。
  35. 如申請專利範圍第30項之方法，其中該金屬係Al、Ti、Sc、Y、Zr、或Hf且該金屬係鍵結至至少三個官能基，其為-SiR1R2R3、-GeR1R2R3、或其混合物，其中R1、R2及R3是烷基(其係相同或不同且選自含雜原子及含非雜原子之烷基)、芳基、環烷基、烯、炔、環及多環基團，其中雜原子係選自鹵素、O、N、S、P、Si、及Ge。
  36. 一種數據處理裝置，其包含：主機板；安裝在該主機板上之通信晶片；及安裝在該主機板上之處理器，該處理器包含： 奈米線電晶體裝置，其包含形成該電晶體裝置之通道區的懸吊的奈米線、設置在該懸吊的奈米線上的介電材料層、設置在該介電材料層上之金屬層，其中該金屬層包含99.5-75.0原子%之2-7族金屬或Al及Si或Ge，Si或Ge之存在量介於0.5及10.0原子%之間，其中該奈米線係懸吊在閘電極中且該金屬層形成該閘電極的部份。
  37. 一種數據處理裝置，其包含：主機板；安裝在該主機板上之通信晶片；及安裝在該主機板上之處理器，該處理器包含：電晶體裝置，其包含通道結構，該通道結構具有頂部表面及一對側向相對之側壁、設置在該頂部表面及該對側向相對之側壁上的介電層、及設置在該在頂部表面及該對側向相對之側壁上之介電層上的金屬層，其中該金屬層包含99.5-75.0原子%之2-7族金屬或Al及Si或Ge，Si或Ge之存在量介於0.5及10.0原子%之間。
  38. 一種數據處理裝置，其包含：主機板；安裝在該主機板上之通信晶片；及安裝在該主機板上之處理器，該處理器包含：具有一表面之基材，設置在該基材表面之介電材料層，在該介電材料層中所形成之溝或通孔，該溝或通孔具有側壁及底部表面， 設置在該側壁及底部表面上之阻障層，其中該阻障層包含99.5-75.0原子%之2-7族金屬及Si或Ge，Si或Ge之存在量介於0.5及10.0原子%之間，及在該壁內之金屬區，其中該阻障層是在該金屬區與該介電材料層之間。
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