CN103843144B - 用于半导体应用的含正电性金属的层 - Google Patents

用于半导体应用的含正电性金属的层 Download PDF

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CN103843144B
CN103843144B CN201180073845.8A CN201180073845A CN103843144B CN 103843144 B CN103843144 B CN 103843144B CN 201180073845 A CN201180073845 A CN 201180073845A CN 103843144 B CN103843144 B CN 103843144B
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metal
layer
substrate
precursor molecule
atoms
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CN103843144A (zh
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P·E·罗梅罗
S·B·克伦德宁
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Intel Corp
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Abstract

本发明实施方案提供了用于通过ALD(原子层沉积)和/或CVD(化学气相沉积)工艺形成包含正电性金属的层、包含一种或多种正电性金属的层、以及包括含有一种或多种正电性金属的层的半导体器件的方法。在本发明实施方案中，所述层是薄或超薄的(小于厚的膜)和/或是共形膜。另外提供了包括金属层的晶体管器件、金属互连件和计算装置，所述金属层包含一种或多种正电性金属。

Description

用于半导体应用的含正电性金属的层
技术领域
本发明的实施方案一般涉及集成电路装置、半导体器件、金属互连件、晶体管、共形膜(conformal film)、原子层沉积工艺、化学气相沉积工艺和化学沉积工艺。
背景技术
对越来越小、集成度更高的集成电路(IC)和其它半导体器件的推动产生了对用于构造所述装置/器件的技术和材料的巨大需求。通常，集成电路管芯又称为微芯片、硅片或芯片。IC芯片常见于各种常用装置，例如计算机中的微处理器、汽车、电视、CD播放机和蜂窝式电话。多个IC芯片典型地构建在硅晶片(一种薄的硅圆片，具有例如300mm的直径)上，加工之后将晶片切开，产生单独的芯片。特征尺寸是约90nm的1cm2的IC芯片可以包括上亿个组件。现有技术推动特征尺寸甚至小于45nm。IC芯片的组件例如包括诸如CMOS(互补金属氧化物半导体)器件的晶体管、电容结构、电阻结构、以及在组件和外部设备之间提供电联接的金属线。其它的半导体器件包括例如各种二极管、激光器、光探测器和磁场传感器。
附图说明
图1A-B示出了可用于在基底表面上形成包含正电性金属的薄共形膜的方法。
图2A-F示出了可用于本发明实施方案的一些前体分子。
图3A-I示出了可用于本发明实施方案的其它示例性前体分子。
图4是示出三栅极晶体管器件的示意图。
图5A-C是示出堆叠的纳米线晶体管器件的示意图。
图6示出了金属互连结构。
图7是根据本发明实施方案构建的计算装置。
具体实施方式
正电性金属和高度正电性金属的沉积归因于不利因素的组合对包含这些金属元素的半导体器件的制造提出了挑战。所述不利因素包括为还原正电性金属所需要的非常高的能量、以及大多数正电性金属对碳、氮和氧的高亲合性。使用CVD(化学气相沉积)或ALD(原子层沉积)工艺的正电性金属沉积可导致不理想的非化学计量的二元相和三元相，例如金属氧化物、金属氮化物、金属碳化物或这些物类的组合的沉积。碳、氮和/或氧往往是不理想的组分，其可降低理想的由一种或多种正电性金属构成的膜的性能。
本发明的实施方案提供了使用ALD和/或CVD工艺用于形成包含正电性金属的层的方法，所述层包含一种或多种正电性金属，以及用于形成包含一种或多种正电性金属的层的半导体器件的方法。在本发明实施方案中，该膜是薄或超薄的(小于厚的膜)和/或是共形膜。有利地是，根据本发明实施方案的膜不包含大量的碳、氮和氧。在本发明的一个实施方案中，包含正电性金属的膜具有总量小于15原子％的碳、氮和氧的杂质。
通常原子层沉积(ALD)是半导体加工工业中典型地用于沉积超薄共形膜的技术。在典型的ALD工艺中，待涂布的膜的基底表面连续暴露于气相反应物(前体)中。表面重复暴露于反应物而在表面上连续产生薄的共形产物层。在表面暴露于各气相反应物之后，将反应气体和反应副产物从反应腔室吹扫出。
通常，化学气相沉积(CVD)是用以在基底表面上产生膜层的工艺。在CVD工艺中，基底表面暴露于挥发性反应物前体中，反应物前体在基底表面上进行反应，形成理想的膜材料。ALD和CVD可用于以各种形式沉积材料，包括例如单晶的、多晶的、无定形的和外延的膜。CVD和ALD工艺典型地在真空室中实施，真空室是专业设备的一部分。
图1A描述了用于在基底上形成包含一种或多种正电性金属的层的ALD方法。根据本发明实施方案的膜沉积工艺能够在基底上沉积微米级和纳米级特征的薄共形膜，并且微米级和纳米级特征具有高纵横比。在图1A中，将在其上沉积薄共形膜的基底表面任选地在膜沉积工艺过程中被加热。在本发明实施方案中，基底在沉积过程中被加热至至少高于室温。即使沉积只需要少量热能，加热可允许保持一致的沉积条件。膜沉积工艺可以发生在相对较低的温度下，例如沉积可发生在30-500℃的温度下。
所述基底表面暴露于包含正电性金属的第一前体分子。在本发明实施方案中，所述正电性金属是选自元素周期表第2-7族的金属和/或Al。在本发明的一个实施方案中，所述正电性金属是例如Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W和Mn的金属。所述第一前体分子包含直接的金属硅键和/或直接的金属锗键。在本发明实施方案中，所述第一前体分子包含1或2个金属原子，并且所述金属原子是全部相同的金属原子或两种不同的金属原子。包含直接的金属硅键和/或直接的金属锗键的第一前体分子的金属中心可以任选地具有通过N、P、O或S原子配位的配位路易斯碱。通过例如用惰性气体，例如氮气、氦气、氖气、氩气、氪气或氙气吹扫正发生沉积的真空室来去除任何不在表面上的前体分子(和可能存在的任何其它气态物类)。然后使基底表面暴露于第二前体分子(共反应物)。所述第二前体分子是挥发性MXn化合物，其中X是卤素或含氧配体，n是在2-6之间且包括2和6的数。使用包含直接的金属硅键和/或直接的金属锗键的正电性金属来沉积膜的反应图解如式(1)所示。
在式(1)中，m和n是在2-6之间且包括2和6的数，R1、R2和R3是相同或不同的，并且是烃基或包含一个或多个杂原子的烃基，所述杂原子例如是卤素、O、N、S、P、Si和/或Ge，X是卤素或醇盐(-OR，其中R是烃或含杂原子的烃，例如烷基或含杂原子的烷基)，E是硅和/或锗，M1和M2是选自元素周期表第2-7族的正电性金属和/或Al，并且p是1或2，并且当p是2时，包含分子(M1)p-(ER1R2R3)m的正电性金属可以是相同或不同的。烃包括例如支化和非支化的烷基、芳基、环烷基、烯基、炔基、环状基团和多环基团。金属M1和M2可以是相同的金属或不同的金属。在本发明的一个实施方案中，M1和M2是例如Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W和Mn的金属。可用的卤素包括氟、氯、溴和碘。在生长的膜中的金属-金属键的形成和挥发性产物(R1-3)3EX的形成是驱动反应前行的因素。还可以以气态反应物与惰性气体，例如氮气、氦气、氖气、氩气、氪气或氙气的混合物向腔室供应反应物和/或共反应物。
然后例如通过用诸如氩气或氮气的惰性气体吹扫腔室而从腔室去除任何剩余的气态共反应物和气态反应产物。将基底表面暴露于第一反应物，去除未附着于基底表面的任何剩余的气态反应物，将基底暴露于共反应物，以及从腔室去除任何气态共反应物(和气态反应产物)的要素(element)重复多次。这些要素重复的次数由基底表面上所得的正电性金属层的理想厚度来决定。这些要素可仅进行一次或多次。
图1B描述了在基底上形成包含正电性金属的层的另外方法。根据本发明实施方案的膜沉积工艺能够在基底上沉积具有微米级和纳米级特征的薄共形膜，并且微米级和纳米级特征具有高纵横比。在图1B中，将在其上沉积薄共形膜的基底表面任选地在膜沉积工艺过程中被加热。在本发明实施方案中，基底在沉积过程中被加热至至少高于室温。即使沉积只需要少量热能，加热可允许保持一致的沉积条件。膜沉积工艺可以发生在相对较低的温度下，例如，沉积可以发生在30-500℃的温度下。
所述基底表面暴露于包含正电性金属的第一前体分子。在本发明实施方案中，所述正电性金属是选自元件周期表第2-7族的金属和/或Al。在本发明实施方案中，所述正电性金属是例如Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W和Mn的金属。所述第一前体分子包含直接的金属硅键和/或直接的金属锗键。在本发明实施方案中，所述第一前体分子包含1-2个金属原子，并且金属原子是全部相同的金属原子或不同的金属原子的混合。包含直接的金属硅键和/或直接的金属锗键的第一前体分子的金属中心可以任选地具有通过N、P、O或S原子配位的配位路易斯碱。通过例如用惰性气体吹扫发生沉积的真空室来去除任何剩余的气态前体分子(和可能存在的任何其它气态物种)。然后使基底表面暴露于第二前体分子(共反应物)。第二反应物是氢。使用包含直接的金属硅键和/或直接的金属锗键的正电性金属沉积膜的反应图解如式(2)所示。
在式(2)中，m是在2-6之间且包括2和6的数，E是硅和/或锗，R1、R2和R3是相同或不同的，并且是烃基或包含一个或多个杂原子的烃基，所述杂原子例如是卤素、O、N、S、P、Si和/或Ge，M是选自元素周期表第2-7族的正电性金属和/或Al，并且p是1或2，并且当p是2或3时，包含分子(M)p-(ER1R2R3)m的正电性金属可以是相同或不同的。烃包括例如支化和非支化的烷基、芳基、环烷基、烯基、炔基、环状基团和多环基团。在本发明的一个实施方案中，Mp是一种或多种金属，例如Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W和Mn。任何常见形式的氢，例如使用或未使用等离子体活化的分子氢，并且在另外的惰性气体，例如氮气、氦气、氖气、氩气、氪气或氙气的存在下或不存在下可用于膜沉积。活性金属氢化物键在基底表面上形成。在ALD工艺的热条件下，金属氢化物分解成分子氢和金属。从表面吹扫反应产物，留下超薄的金属层。
然后例如通过用如氩气或氮气的惰性气体吹扫腔室而从腔室去除任何剩余的气态共反应物和气态反应产物。将基底表面暴露于第一反应物，去除未附着于基底表面的任何剩余的气态反应物，将基底暴露于共反应物，以及从腔室去除任何气态共反应物(和气态反应产物)的要素重复多次。这些要素重复的次数由基底表面上所得的正电性金属层的理想厚度来决定。这些要素可以仅实施一次。
在图1A和1B的可选实施方案中，实施更类似于CVD的技术，并且同时向基底表面一起提供气态反应物和共反应物(若有)以形成正电性金属的层。在其他可选实施方案中，从腔室去除剩余的气态反应物和共反应物以及气态产物，多次重复向基底表面供应气态反应物和共反应物的工艺，以产生具有理想厚度的层。
在本发明实施方案中，包含正电性金属的膜在暴露于任何可能的氧化物，例如暴露于空气之前具有处于单质金属(零氧化态)的正电性金属。如果该膜受保护而避免氧化剂，则正电性金属保持在零氧化态。
图2A-F示出了可用于本发明实施方案的前体分子。包含正电性金属、1-2个金属原子、直接的金属硅键和/或直接的金属锗键和键合至Si和/或Ge的其他官能团的其它前体分子也是可能的。在图2A-F中，在官能团-ER1R2R3中，R1、R2和R3是相同或不同的，并且是烷基、芳基、在E和主族元素，例如Si、Ge、N、P、O或S之间包含直接键的基团或杂环基团，并且E是Si或Ge。在图2A中，M1是正电性金属，例如Be、Mg或Ca。在图2B-E中，M2是正电性金属，例如是Ti、Sc或Y，E是硅或锗。在图2F中，M3是正电性金属，例如Ti、Zr或Hf，E是硅或锗。在本发明的一个实施方案中，R是甲基。在本发明的另一个实施方案中，-ER1R2R3包含两个甲基和苯甲基作为R官能团。在本发明的又一个实施方案中，前体分子是((CH3)3Si)3Al:N(CH3)2(CH2CH3)、((CH3)2ArSi)3Al:N(CH3)2(CH2CH3)、((CH3)3Si)3Al(奎宁环)、((CH3)3Ge)3Al(奎宁环)、((C4H9)3Si)2Mn、((C4H9)3Si)2Mn·N(CH3)3、((CH3)3Ge)2Mn(tmeda)和((C4H9)3Si)2Ti N(CH3)3，其中Ar是任选包含一个或多个杂原子的芳基或烃基，并且tmeda是四甲基乙二胺。
根据本发明实施方案的工艺可用于产生超薄的金属层，其用于例如栅极电极和平坦、三栅极和堆叠的纳米线晶体管器件的源极/漏极接触应用、以及作为势垒层、种晶层、衬垫、帽(cap)、和/或作为主要的导电互连金属的共形层的互连件(过孔(via)和线)。根据本发明实施方案的方法可以用于例如沉积NMOS功函数金属、NMOS金属扩散势垒层、PMOS功函数金属和/或粘合层/衬垫层。由于使用包含直接的金属硅键和/或直接的金属锗键的前体来形成膜，根据本发明实施方案的金属层存在低水平的Si和/或Ge。根据本发明实施方案的膜中存在的Si和/或Ge的水平是0.5-10.0原子％。在另外的实施方案中，膜中存在的Si和/或Ge的水平是2-15原子％、或2和8原子％。
在本发明另外的实施方案中，所产生的包含正电性金属的金属层在层中具有更高的Si和/或Ge的水平。典型地，CVD工艺用来产生具有更高Si和/或Ge含量的金属硅化物膜和/或金属锗化物膜。例如，TiSi是用于根据本发明实施方案产生的半导体制造的导电材料。根据本发明另外的实施方案的正电性金属膜中存在的Si和/或Ge的水平是10.0-67原子％。
图3A-I示出了可用于本发明实施方案的另外的前体分子。包含第2-7族金属的不同组合和/或Al、包含1-2个金属原子、以及键合至Si和/或Ge的不同官能团的其它前体分子也是可能的。
图4提供了简化的三栅极晶体管结构。在图4中，绝缘基底405包括栅极电极410和源极415和漏极420的区域。绝缘基底405由例如具有其上形成的绝缘材料，例如SiO2的半导体基底构成。沟道区430在三个侧面具有栅极介电区425和栅极电极区410。栅极电极区410由根据本发明实施方案的金属层构成。电极区410至少部分地例如使用在此所述的允许沉积薄共形层的方法形成。这些金属层存在的Si或Ge的水平低，其水平是0.5-10.0原子％的Si或Ge(或者2-15原子％、或2和8原子％)，并且前体分子中存在的一种或多种第2-7族金属或Al的水平是99.5-75.0原子％(或98-70原子％、或98-72原子％)。在共形层已经沉积之后，电极区可以任选地使用不同的沉积工艺，例如使用不同前体的ALD或CVD工艺而用导电材料填充。任选地，粘合层和/或势垒层(未显示)处于栅极介电区425和栅极电极区410之间。源极415区和漏极420的区域例如由导电的P型或N型半导体材料形成。栅极介电层425是绝缘材料，例如二氧化硅(SiO2)、氮氧化硅(SiOxNy)、氮化硅(Si3N4)。栅极介电层425还可以是高k栅极的介电材料，例如金属氧化物介电体。沟道区430可以由例如掺杂或未掺杂的硅、单晶硅、硅和锗的混合物或III-V族化合物半导体(包括周期表第III族和第V(或13和15)族元素的化合物)，例如砷化铟镓(InGaAs)、磷化铟(InP)和砷化铟铝(InAlAs)构成。通常，三栅晶体管结构具有在三个侧面被栅极介电体和栅极电极包围的沟道区。用于所示特征的其它结构和形状也可用于三栅极晶体管，例如具有不同形状的源极区和漏极区的那些。此外，具有其它相关特征的晶体管为了简要而未画出。例如，栅极电极区典型地由绝缘间隔件限定，晶体管结构可以覆盖在绝缘材料中，并且导电过孔将源极区和漏极区连接至其它器件和容纳晶体管的半导体芯片区域。在本发明的其他实施方案中，导电过孔(未显示)具有衬垫在触点内侧的金属层，该金属层所存在的Si或Ge水平低，其水平是0.5-10.0原子％的Si或Ge(或2-15原子％、或2和8原子％)。在本发明的另一个实施方案中，该膜包含低水平的Si或Ge，其水平是0.5-10.0原子％的Si或Ge(或2-15原子％、或2和8原子％)，并且前体分子中存在的一种或多种第2-7族金属和/或Al的水平是99.5-75.0原子％(或98-70原子％、或98-72原子％)。在本发明另外的实施方案中，该膜包含低水平的Si或Ge，其水平是0.5-10.0原子％的Si或Ge(或2-15原子％、或2和8原子％)，并且前体分子中存在的一种或多种第2-7族金属和/或Al的水平是99.5-75.0原子％(或98-70原子％、或98-72原子％)，并且碳、氮和氧杂质总量低于15原子％。在本发明另外的实施方案中，衬垫触点内侧的层根据在此所述的方法形成。该层可以沉积在源极/漏极区域和触点金属之间的薄扩散势垒层上。
图5A-C示出了堆叠的纳米线晶体管器件。图5A的图显示了半个堆叠纳米线晶体管器件以便于说明。图5B表示以相对图5A的视角旋转45°的透视图中图5A的器件，栅极介电体层和栅极金属现已包括在图5B中。图5C显示了沿着相对图5A的切割平面旋转90°的平面切割，并且器件自身已旋转-45°的堆叠纳米线晶体管器件。在图5A中，基底505容纳绝缘间隔件510和源极/漏极区515。纳米线沟道区520(每个晶体管中示出两个)与源极/漏极区515接触。纳米线沟道区520包含例如硅、硅和锗或III-V族化合物半导体，例如砷化铟镓(InGaAs)、磷化铟(InP)和砷化铟铝(InAlAs)。在图5B-C中，栅极介电体525布置在沟道区520上，栅极电极区530布置在栅极介电体525上。栅极介电体525是绝缘材料，例如二氧化硅(SiO2)、氮氧化硅(SiOxNy)、氮化硅(Si3N4)或高k介电材料。在此所述的工艺可用以在栅极介电体525周围沉积薄的金属共形层535。薄的金属共形层535存在的Si或锗水平低，其水平是0.5-10.0原子％的Si或Ge(或2-15原子％、或2和8原子％)。在本发明的又一个实施方案中，膜包含低水平的Si或Ge，其水平是0.5-10.0原子％的Si或Ge(或2-15原子％、或2和8原子％)，并且前体分子中存在的一种或多种第2-7族金属和/或Al的水平是99.5-75.0原子％(或98-70原子％、或98-77原子％)。在本发明另外的实施方案中，膜包含低水平的Si或Ge，其水平是0.5-10.0原子％的Si或Ge(或2-15原子％、或2和8原子％)，并且前体分子中存在的一种或多种第2-7族金属和/或Al的水平是99.5-75.0原子％(或98-70原子％、或98-72原子％)，并且碳、氮和氧杂质总量低于15原子％。其余的栅极电极区530可以包含相同的金属或不同的导电物质作为薄的金属共形层535，并且可以通过相同或不同的方法沉积。在另外的实施方案中，栅极电极区530可以包含例如Ti、W、Ta、Al及其合金、以及其与稀土元素，例如Er、Dy或如Pt的贵金属的合金，以及氮化物，例如TaN和TiN的材料。任选地，粘合层和/或势垒层(未显示)在栅极介电区525和栅极电极区530之间。用于所述特征的其它结构和形状也可用于堆叠的纳米线晶体管，例如具有不同数量的纳米线晶体管(例如一个、两个或三个或更多个纳米线)以及具有不同形状的源极和漏极区的那些。
通常，高k介电体是介电常数大于SiO2的介电材料。SiO2的介电常数是3.9。示例性的高k介电材料包括二氧化铪(HfO2)、铪硅氧化物、氧化镧、镧铝氧化物、二氧化锆(ZrO2)、锆硅氧化物、二氧化钛(TiO2)、五氧化钽(Ta2O5)、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物、铌锌酸铅、以及半导体领域已知的其它材料。
在本发明另外的实施方案中，根据本发明实施方案的方法被用于沉积BEOL(后段工艺)互连应用的金属。这些应用包括粘合层、衬垫、势垒层、用于减少电迁移的帽、以及互连金属自身。图6示出了金属互连结构，例如沟槽或过孔。在图6中，基底605容纳金属沟槽或过孔610。金属沟槽或过孔610在绝缘层615内，绝缘层例如是层间介电材料(ILD)。介电材料包括低k介电体和二氧化硅。任选的层620是由介电材料，例如氮化硅、氮氧化硅和二氧化硅构成的阻蚀层。势垒层625将金属沟槽或过孔610从介电层615和620隔离。该结构任选地还包括帽层(capping layer)635，其从沉积在金属沟槽或过孔610上的另外的介电层640(例如ILD)隔离金属沟槽或过孔610。金属沟槽或过孔610任选地电联接至下伏的第二金属沟槽或过孔645。金属沟槽或过孔610和645由例如铜、铝、银及其合金构成。进一步任选地，图6的结构包括帽层635，但是包括不同的势垒层625，或者不包括势垒层625。在本发明的一个实施方案中，金属沟槽或过孔610和645由铜构成。在本发明实施方案中，势垒层625可以包含W、Hf和/或Ta，用于减少电迁移的金属帽635可以包含W。薄的共形层W、Hf和/或Ta根据本发明实施方案沉积在层间介电材料(ILD)上(由例如低k材料或SiO2的介电材料构成)，然后在电镀之前用ALD Cu膜涂布。帽层可以相对于介电表面选择性地沉积在暴露的金属表面上。介电表面上的原子层沉积可以通过使用薄有机膜的其表面官能化进行抑制，其包括但不限于自组装的单层和氨基(有机)硅烷。如前面所讨论，根据本发明实施方案的正电性金属膜(即沉积之后未改性的)所存在的Si或Ge的水平低，其水平是0.5-10.0原子％的Si或Ge(或2-15原子％、或2和8原子％)。在本发明的其他实施方案中，膜包含低水平的Si或Ge，其水平是0.5-10.0原子％的Si或Ge(或2-15原子％、或2和8原子％)，并且前体分子中存在的一种或多种第2-7族金属和/或Al(例如W、Hf和/或Ta)的水平是99.5-75.0原子％(或98-70原子％、或98-72原子％)。在本发明另外的实施方案中，膜包含低水平的Si或Ge，其水平是0.5-10.0原子％的Si或Ge(或2-15原子％、或2和8原子％)，并且前体分子中存在的一种或多种第2-7族金属和/或Al的水平是99.5-75.0原子％(或98-70原子％、或98-72原子％)，并且碳、氮和氧杂质总量低于15原子％。
用于介电层、特征和/或层间介电材料(ILD)的典型介电材料包括二氧化硅和低k介电材料。可以使用的其他介电材料包括碳掺杂的氧化物(CDO)、氮化硅、有机聚合物，例如全氟环丁烷或聚四氟乙烯、氟硅酸盐玻璃(FSG)和有机硅酸盐，例如倍半硅氧烷、硅氧烷、有机硅酸盐玻璃。该介电层可以包括孔以进一步降低介电常数。
在此显示的器件组件可以包括附加层，例如衬垫层和粘合层，其将包括不同材料的层，例如金属层与绝缘层隔离，为了简要，以一层示出的组件可以包括多个相同或不同材料的层，其例如取决于用于构造器件的制造工艺和理想的器件性能。
本发明的实施方案容纳在基底上，例如半导体基底上。其上可形成本发明实施方案的正电性金属层的基底表面包含例如H封端的硅、二氧化硅、硅、硅锗、第III-V族(或以附加的周期表栏号方案的第13-14族)化合物半导体、主族氧化物、金属和/或二元或混合的金属氧化物。层和包括器件的层还可以被称为制造本发明实施方案的基底或基底的一部分。其上构建半导体器件的基底典型地是被切分得到单独IC芯片的半导体晶片。虽然本发明实施方案并不依赖于所用基底的类型，但是其上构建半芯片的基底典型地是硅晶片。所述基底还可以由锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、锑化镓和/或其它的第III-V族材料构成，或者单独地或与硅或二氧化硅或其它的绝缘材料组合而构成。
图7示出了根据本发明的一个实施方案的计算装置1000。计算装置1000容纳主板1002。主板1002可以包括一些组件，其包括但不限于处理器1004和至少一个通信芯片1006。处理器1004物理联接且电联接至主板1002。在一些实施方案中，至少一个通信芯片1006也物理联接且电联接至主板1002。
取决于其应用，计算装置1000可以包括其它组件，其可以或可以不物理联接且电联接至主板1002。这些其它组件包括但不限于易失性存储器(如DRAM)、非易失性存储器(如ROM)、图像处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)装置、指南针、加速表、陀螺仪、扬声器、摄像机和大容量存储装置(如硬盘驱动器、压缩光盘(CD)、数字通用光盘(DVD)等)。
通信芯片1006能使往返于计算装置1000的数据传输进行无线通信。术语“无线”及其派生词可以用于描述电路、器件、系统、方法、技术、信道等，其可以通过使用调谐电磁辐射通过非固体介质通信数据。该术语并不暗指相关的器件不具有任何的线，虽然在一个实施方案中其可以不具有。通信芯片1006可以执行一些无线标准或协议的任何一种，其包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、它们的派生物、以及指明是3G、4G、5G及以上的任何其它无线协议。计算装置1000可以包括多个通信芯片1006。例如，第一通信芯片1006可以专用于较短范围的无线通信，例如Wi-Fi和蓝牙，而第二通信芯片1006可以专用于较长范围的无线通信，例如GPS,EDGE、GPRS、CDMA、WiMAX、LTE和Ev-DO等。
计算装置1000的处理器1004包括封装在处理器1004内的集成电路管芯。在本发明一些实施方案中，处理器的集成电路管芯包括一个或多个根据本发明实施方案形成的器件，例如晶体管和/或金属互连件。术语“处理器”可以是指任何装置或装置部分，其处理来自寄存器和/或存贮器的电子数据以将这些电子数据变换成可以存储在寄存器和/或存贮器中的其它电子数据。
通信芯片1006也包括封装在通信芯片1006内的集成电路管芯。根据本发明另一个实施方案，通信芯片的集成电路管芯包括一个或多个根据本发明实施方案形成的器件，例如晶体管和/或金属互连件。
在另一实施方案中，容纳在计算装置1000内的另一个组件可以具有集成电路管芯，其包括一个或多个根据本发明实施方案形成的器件，例如晶体管和/或金属互连件。
在各种实施方案中，计算装置1000可以是膝上型、网络本、笔记本、智能手机、平板电脑、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制器、数码相机、便携式音乐播放器或数字录像机。在其他实施方案中，计算装置1000可以是能处理数据的任何其它电子器件。
在上述说明书中阐述了许多具体细节，例如晶体管、互连件和材料方案的布局，以便为本发明实施方案提供彻底的了解。对于本领域技术人员明显地是，本发明实施方案可以不用这些具体细节进行实施。另外，为了不会不必要地使本发明的实施方案不清楚，没有详细说明众所周知的特征，例如集成电路设计布局。此外，应理解附图中所示的不同实施方案是示意性表示，并不一定按比例描绘。
相关领域的技术人员知道，可以对所显示和说明的各种组件的公开内容、组合和替换进行改进和变化。遍及本说明书所指的“一个实施方案”或“实施方案”是指针对实施方案描述的一种具体的特征、结构、材料或特性包括在本发明的至少一个实施方案中，但是不一定是指它们存在于每个实施方案中。此外，实施方案中所公开的具体特征、结构、材料或性能可以以任何适当的方式在一个或多个实施方案中组合。可以包括各种其它的层和/或结构，和/或所说明的特征可以在其它实施方案中略去。

Claims (14)

1.一种半导体装置，其包括：
具有表面的基底，
布置在基底表面上的介电材料层，
形成在所述介电材料层中的沟槽或过孔，所述沟槽或过孔具有侧壁和底表面，
布置在所述侧壁和底表面上的势垒层，其中所述势垒层包含99.5-75.0原子％的第2-7族金属以及Si或Ge，Si或Ge的存在量是0.5-10.0原子％的Si或Ge，以及
阱内的金属区，其中所述势垒层在金属区与介电材料层之间。
2.根据 权利要求1所述 的装置，其中所述第2-7族金属是W、Hf、Ta或它们的组合。
3.根据 权利要求1所述 的装置，其中所述金属层包含总量小于15原子％的碳、氮和氧。
4.根据 权利要求1所述 的装置，其中所述金属区由银、铜或铝构成。
5.一种半导体装置，其包括：
具有表面的基底，
布置在基底表面上的介电材料层，
形成在介电材料层中的沟槽或过孔，
所述沟槽或过孔内的金属区，其中所述金属区具有表面，以及
布置在金属区表面上的帽层，其中帽层包含99.5-75.0原子％的第2-7族金属以及Si或Ge，Si或Ge的存在量是0.5-10.0原子％的Si或Ge。
6.根据 权利要求5所述 的装置，其中所述第2-7族金属是W。
7.根据 权利要求5所述 的装置，其中所述金属层包含总量小于15原子％的碳、氮和氧。
8.根据 权利要求5所述 的装置，其中所述金属区由银、铜或铝构成。
9.一种用于制造层的方法，其包括：
提供具有表面的基底，
将基底表面暴露于气相第一前体分子，其中所述第一前体分子包含金属M1，其中金属M1是第2-7族金属或Al，并且金属M1与至少两个硅、锗、或硅和锗原子直接键合，
去除任何剩余的气态第一前体分子，
将基底表面暴露于第二气相前体分子M2Xn，其中X是卤素，n是在2-6之间且包括2和6的数，M2是第2-7族金属或Al，并且M1和M2是相同的金属或不同的金属，
去除任何剩余的气态第二前体分子，以及
重复以下要素至少一次，以便在基底表面上产生包含M1和M2的层：将基底暴露于第一前体分子，去除任何气态第一前体分子，将基底暴露于第二前体分子，以及去除任何剩余的气态第二前体分子。
10.根据 权利要求9所述 的方法，其中M1和M2选自：Zr、Be、Mg、Ca、Sr、Al、Sc、Y、Ti、Hf、V、Nb、Ta、Cr、Mo、W和Mn。
11.根据 权利要求9所述 的方法，其中所述第一前体分子包含两个第2-7族金属原子或Al原子。
12.根据 权利要求9所述 的方法，其中所述第一前体分子选自：((CH3)3Si)3Al·N(CH3)2(CH2CH3)、((CH3)2ArSi)3Al·N(CH3)2(CH2CH3)、((CH3)3Si)3Al(奎宁环)、((CH3)3Ge)3Al(奎宁环)、((C4H9)3Si)2Mn、((C4H9)3Si)2Mn·N(CH3)3、((CH3)3Ge)2Mn(四甲基乙二胺)和((C4H9)3Si)2Ti·N(CH3)3。
13.根据 权利要求9所述 的方法，其中M1与至少两个官能团键合，所述官能团是-SiR1R2R3、-GeR1R2R3或它们的组合，其中R1、R2和R3是相同或不同的烷基，并选自以下：含杂原子和不含杂原子的烷基、芳基、环烷基、烯基、炔基、环状基团和多环基团，其中杂原子选自：卤素、O、N、S、P、Si和Ge。
14.根据 权利要求9所述 的方法，其中M1是Al、Ti、Sc、Y、Zr或Hf，并且M1与至少三个官能团键合，所述官能团是-SiR1R2R3、-GeR1R2R3或它们的组合，其中R1、R2和R3是相同或不同的烷基，并选自：烷基、芳基、环烷基、烯基、炔基、环状基团和多环基团，其中杂原子选自：卤素、O、N、S、P、Si和Ge。
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TWI582997B (zh) 2017-05-11
US20150243508A1 (en) 2015-08-27
US20130270513A1 (en) 2013-10-17
US9390932B2 (en) 2016-07-12

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