WO2018118086A1

WO2018118086A1 - Gallium-based co-reactants for fabricating metal silicide and metal germanide films

Info

Publication number: WO2018118086A1
Application number: PCT/US2016/068579
Authority: WO
Inventors: Patricio E. Romero; Scott B. Clendenning; Cen TAN
Original assignee: Intel Corporation
Priority date: 2016-12-23
Filing date: 2016-12-23
Publication date: 2018-06-28

Abstract

Gallium-based co-reactants for fabricating metal silicide and metal germanide films, and integrated circuit structures including such films, are described. In a first example, a discrete acyclic molecule includes a gallium-based moiety having a central gallium atom, and a silicon-based moiety having a central silicon atom. The central silicon atom of the silicon-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. In a second example, a discrete acyclic molecule includes a gallium-based moiety having a central gallium atom, and a germanium-based moiety having a central germanium atom. The central germanium atom of the germanium-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. In either case, a neutral Lewis basic ligand is bonded to the central gallium atom of the gallium-based moiety.

Description

GALLIUM-BASED CO-REACTANTS FOR FABRICATING METAL SILICIDE AND METAL

GERMANIDE FILMS TECHNICAL FIELD

[0001] Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, gallium-based co-reactants for fabricating metal silicide and metal germanide films, and integrated circuit structures including such films. BACKGROUND

[0002] For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips.

[0003] For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yielding bulk silicon substrate infrastructure. Scaling multi- gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

[0004] Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed in order to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

[0005] Variability in conventional and state-of-the-art fabrication processes may limit the possibility to further extend them into the sub-10 nm range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic representing a mechanism in the formation of a M(Al)C film.

[0007] Figure 2 illustrates chemical drawing representations of discrete acyclic molecules including a gallium-based moiety, in accordance with an embodiment of the present disclosure.

[0008] Figure 3 illustrates a schematic representation of the synthesis of a discrete acyclic molecule including a gallium-based moiety, in accordance with an embodiment of the present disclosure.

[0009] Figure 4 is a plot of a thermal profile showing complete evaporation with minimal decomposition at temperature suitable for ALD processing, in accordance with an embodiment of the present disclosure.

[0010] Figure 5 illustrates a plan view and corresponding cross-sectional view of a metallization layer of an integrated circuit structure, in accordance with an embodiment of the present disclosure.

[0011] Figure 6A illustrates a cross-sectional view of a semiconductor device having a metal silicide or germanide layer on a source or drain region, in accordance with an embodiment of the present invention.

[0012] Figure 6B illustrates a cross-sectional view of another semiconductor device having a metal silicide or germanide layer on a source or drain region, in accordance with an embodiment of the present invention.

[0013] Figure 7A illustrates a cross-sectional view of a non-planar semiconductor device having a metal silicide or germanide layer as a workfunction layer of a gate electrode, in accordance with an embodiment of the present disclosure.

[0014] Figure 7B illustrates a plan view taken along the a-a’ axis of the semiconductor device of Figure 7A, in accordance with an embodiment of the present disclosure.

[0015] Figure 8 illustrates a computing device in accordance with one implementation of an embodiment of the disclosure.

[0016] Figure 9 is an interposer implementing one or more embodiments of the disclosure. DESCRIPTION OF THE EMBODIMENTS

[0017] Gallium-based co-reactants for fabricating metal silicide and metal germanide films, and integrated circuit structures including such films, are described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0018] Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as“upper”, “lower”,“above”,“below,”“bottom,” and“top” refer to directions in the drawings to which reference is made. Terms such as“front”,“back”,“rear”, and“side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0019] Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0020] Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0021] Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

[0022] One or more embodiments described herein are directed to gallium-based co- reactants for metal (e.g., titanium) silicide and germanide films. Embodiments may be applicable to or include one or more of atomic layer deposition (ALD), chemical vapor deposition, gate layer fabrication, thin films, or transistor fabrication.

[0023] To provide context, many conformal N-type work function metals have the chemical formula M(Al)C where M = Ti, Zr, Hf, Ta, Nb or V. Such films are typically formed in an ALD-like process where a metal halide, typically a metal chloride, is pulsed followed by a purge. A pulse of an alkyl-aluminum co-reactant is provided to achieve a targeted chemical composition.

[0024] In accordance with an embodiment of the present disclosure, a new molecular co- reactant motif for the atomic layer deposition (ALD) of conductive and metallic films containing silicon or germanium is described. It is to be appreciated that known metal aluminum carbide films, M(Al)C, typically suffer from high resistance on the order of several thousand ^ȍācm at a thickness of 5-10 nm. When used as a gate work function metal or contact metals, such a high resistance degrades device performance. In accordance with one or more embodiments described herein, incorporation of silicon or germanium atoms is performed to decrease resistivity and lower the work function, two requisites for future implementation in FEOL manufacturing schemes. In one embodiment, molecules such as those described below are provided as competent co-reactants to deliver Si or Ge during ALD processing, enabling the deposition of films of the form M(Ga)CSi or M(Ga)CGe.

[0025] To provide further context, the incorporation of silicon or germanium atoms is believed to be beneficial to decrease resistivity and lower the work function of state-of-the-art M(Al)C films, two requisites for future implementation in FEOL manufacturing schemes.

Traditional co-reactants are unable to accomplish such heteroatom incorporation due to a lack of proper chemical reactivity and functionality.

[0026] In accordance with one or more embodiments of the present disclosure, an alkyl- gallium co-reactant containing a large silicon (“silyl”) group or germanium (“germyl” or “germanyl”) group, is described as an alternative to traditional alkyl-aluminum co-reactants to deposit an ALD M(Ga)CSi or ALD M(Ga)CGe film. In one embodiment, the use of such new alkyl-gallium co-reactants in addition to an alkyl-aluminum precursor enables access to

MAl(Ga)CSi and MAl(Ga)CGe films. Such ALD films may be used as gate work function metals or as contact metals, for example. In an embodiment, the newly developed molecules based on gallium can accomplish decreased resistivity and tune the workfunction of state-of-the- art M(Al)C films by organometallic trans-metalation of carefully chosen silyl or germyl groups. The incorporation of Ga, Si or Ge may lower or increase the workfunction compared to a traditional M(Al)C film. In an embodiment, it is this ability to tune the work function to achieve a desired Vt for the device that demonstrates the advantages of such films. In other

embodiments, such films are used as low resistivity BEOL barrier/liners. For example, a low resistivity ALD TaAlGaCSi film may provide a superior barrier to a high resistance ALD TaNx film.

[0027] Figure 1 is a schematic representing a mechanism in the formation of a M(Al)C film. At part (a), a hydroxylated surface is provided. TiCl₄ is added and reacted to generate HCl, and a purge is performed to provide the structure in part (b) and to remove the HCl. Al(CH3)3 is then added and reacted to generate ClAl(CH₃)₂, and a purge is performed to provide the structure in part (c) and to remove the ClAl(CH3)2. More Al(CH3)3 is then added to provide the structure in part (d). Upon reaction of the structure of part (d), such as thermal heating, a TiAlC film (e) is formed, and by-products such as CH4, CH3CH3, and H2 are removed. The process may be repeated a number of times to deposit a film of a desired thickness. Similar mechanisms are envisioned for other reactants such as TiCl4, HfCl4, ZrCl4, TaCl5, NbCl5, or VCl4.

[0028] Referring again to Figure 1, the final composition of the film in (e) is largely dictated by the molecular make-up of the organo-aluminum co-reactant, which is responsible for two thirds of the elemental distribution (i.e., Al and C). Therefore, by changing the ligand nature around the aluminum center, a different final composition is expected to result. In accordance with one or more embodiments described herein, a new co-reactant motif based on gallium, instead of aluminum, is described to deliver films of the form M(Ga)CSi.

[0029] As exemplary molecular structures, Figure 2 illustrates chemical drawing representations of discrete acyclic molecules including a gallium-based moiety, in accordance with an embodiment of the present disclosure.

[0030] Referring to the left-hand portion (a) of Figure 2, a discrete acyclic molecule 200 includes a gallium-based moiety having a central gallium atom, and a silicon-based moiety having a central silicon atom. The central silicon atom of the silicon-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. A neutral Lewis basic ligand (L) is bonded to the central gallium atom of the gallium-based moiety.

[0031] In one embodiment, the central gallium atom of the gallium-based moiety of molecule 200 is bonded to two alkyl groups (e.g., ethyl groups), as is depicted. In one embodiment, the central silicon atom of the silicon-based moiety is bonded to three trialkyl-silyl groups (e.g., trimethyl-silyl groups), as is depicted. In one embodiment, the neutral Lewis basic ligand (L) is selected from the group consisting of a P(alkyl)₃ ligand, an N-heterocyclic carbene ligand, and amine ligand, and a sulfide ligand. In a particular embodiment, the chemical formula of the discrete acyclic molecule is as represented by the structure 200.

[0032] Referring to the right-hand portion (b) of Figure 2, a discrete acyclic molecule 300 includes a gallium-based moiety having a central gallium atom, and a germanium-based moiety having a central germanium atom. The central germanium atom of the germanium-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. A neutral Lewis basic ligand (L) is bonded to the central gallium atom of the gallium-based moiety.

[0033] In one embodiment, the central gallium atom of the gallium-based moiety of molecule 250 is bonded to two alkyl groups (e.g., ethyl groups), as is depicted. In one embodiment, the central germanium atom of the germanium-based moiety is bonded to three trialkyl-germyl groups (e.g., trimethyl-germyl groups), as is depicted. In one embodiment, the neutral Lewis basic ligand (L) is selected from the group consisting of a P(alkyl)₃ ligand, an N- heterocyclic carbene ligand, and amine ligand, and a sulfide ligand. In a particular embodiment, the chemical formula of the discrete acyclic molecule is as represented by the structure 250.

[0034] The molecules of Figure 2 may be synthesized by a salt metathesis reaction. As exemplified by a route for a silyl group, Figure 3 illustrates a schematic representation of the synthesis of a discrete acyclic molecule including a gallium-based moiety, in accordance with an embodiment of the present disclosure.

[0035] Referring to Figure 3, an alkali metal derivative of the silyl group of molecule 200 is reacted with a halide derivative of the gallium group of molecule 200. In one embodiment, the alkali metal derivative is a potassium derivative solvated with two tetrahydrofuran (THF) molecules and the halide derivative is a chloro derivative, as is depicted in Figure 3. At (a), potassium chloride is precipitated out to provide the Ga-Si based discrete molecule 306. At (b), the final THF molecule is replaced with a Lewis basic ligand (L).

[0036] The molecules described in association with Figure 2, may be sufficiently stable to be used in a heated process, such as an atomic layer deposition process. As an example, Figure 4 is a plot 400 of a thermal profile showing complete evaporation with minimal decomposition at temperature suitable for ALD processing, in accordance with an embodiment of the present disclosure.

[0037] A full thermal analysis of a silicon-containing co-reactant 200, where L = PMe3, is shown in Figure 4. In an embodiment, Figure 4 demonstrates that although traditional co- reactants utilize aluminum as the central atom, as compared to embodiments described herein based on gallium, similar motifs for aluminum were found to have limited thermal stability and are thus unsuitable for ALD processes. It is also to be appreciated that an organo-aluminum co- reactant may not completely react with a metal halogen bonds on the surface of a growing film. Accordingly, in another embodiment of the present disclosure, an organo-aluminum precursor followed by an organo-gallium precursor are both used to further tune a film composition and properties. In one such embodiment, films of the form MAl(Ga)CSi and MAl(Ga)CGe are fabricated.

[0038] In an embodiment, metal silicide and metal germanide films described herein are suitable to provide a low resistance, ALD N-type work function metals for next generation devices. It is to be appreciated that low resistance N-type work function metals may be required to achieve improved Si, SiGe, Ge and two-dimensional (2D) material channel device

performance. In one embodiment, metal silicide and metal germanide films described herein are N-type work function layers that include significant amounts of gallium, e.g., in the range of 2-25 atomic %. In an embodiment, molecules described herein are suitable as co-reactants for the ALD deposition of low resistivity and tunable, N-type work function silicide or germanide materials.

[0039] In another aspect, molecules described in association with Figure 2 may be used in an atomic layer deposition (ALD) process to form a metal silicide or metal germanide film. In an exemplary embodiment, a method of fabricating a metal silicide or germanide film includes providing a substrate in an atomic layer deposition (ALD) chamber, the substrate having a surface. The method also includes co-reacting a metal (M) halide source and a discrete acyclic molecule source to form a layer on the surface of the substrate, the layer including M(Ga)CSi or M(Ga)CGe.

[0040] In one embodiment, the method further includes co-reacting the metal (M) halide source and the discrete acyclic molecule source with an organo-aluminum source to further provide aluminum (Al) in the layer of M(Ga)CSi or M(Ga)CGe. In one embodiment, the metal (M) halide source is a metal (M) chloride source. In one embodiment, M is selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) and vanadium (V).

[0041] In an embodiment, the layer including M(Ga)CSi or M(Ga)CGe has a total composition including between 2-25 atomic % gallium. In a particular such embodiment, the total composition includes M between 10-60 atomic %, C between 2-50 atomic %, Si or Ge between 2-50 atomic %. In a specific such embodiment, in the case that Al is included, the total composition includes Al between 2-25 atomic %.

[0042] In one embodiment, the layer is M(Ga)CSi, and each of the molecules of the discrete acyclic molecule source each include a gallium-based moiety having a central gallium atom, a silicon-based moiety having a central silicon atom, where the central silicon atom of the silicon-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond, and a neutral Lewis basic ligand bonded to the central gallium atom of the gallium-based moiety, such as described in association with molecule 200 of Figure 2.

[0043] In one embodiment, the layer is M(Ga)CGe, and each of the molecules of the discrete acyclic molecule source each include a gallium-based moiety having a central gallium atom, a germanium-based moiety having a central germanium atom, where the central germanium atom of the germanium-based moiety and the central gallium atom of the gallium- based moiety are covalently bonded to one another with a single bond, and a neutral Lewis basic ligand bonded to the central gallium atom of the gallium-based moiety, such as described in association with molecule 250 of Figure 2.

[0044] In another aspect, an integrated circuit structure includes a feature having a surface. A metal silicide or germanide layer is on the surface of the feature. The metal silicide or germanide layer includes M(Ga)CSi or M(Ga)CGe. In one embodiment, the feature is a conductive line trench of a back end-of-line (BEOL) metallization layer, an example of which is described below in association with Figure 5. In another embodiment, the feature is a source or drain contact trench exposing a semiconductor source or drain structure, examples of which are described below in association with Figures 6A and 6B. In another embodiment, the feature is a gate trench, and the surface is a gate dielectric layer, an example of which is described below in association with Figures 7A and 7B.

[0045] In a first such aspect, Figure 5 illustrates a plan view and corresponding cross- sectional view of a metallization layer of an integrated circuit structure, in accordance with an embodiment of the present disclosure. Referring to Figure 5, a metallization layer 500 includes a pattern of conductive lines 502 and interlayer dielectric (ILD) lines 504. The metallization layer 500 may be patterned in a grating-like pattern with conductive lines 502 spaced at a constant pitch and having a constant width, as is depicted in Figure 5. Although not shown, the conductive lines 502 may have interruptions (i.e., cuts or plugs) at various locations along the lines. The pattern, for example, may be fabricated by a pitch halving or pitch quartering approach, as described above. Some of the conductive lines may be associated with underlying vias, such as line 502’ shown as an example in the cross-sectional view.

[0046] In an embodiment, the term“grating” for conductive lines 502 and ILD lines 504 is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have conductive lines 502 and/or ILD lines 504 spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach.

[0047] In an embodiment, the conductive lines 502 (and, possibly, underlying via structures) are composed of one or more metal or other conductive structures. The conductive lines 502 are also sometimes referred to in the art as traces, wires, lines, metal, interconnect lines or simply interconnects. In a particular embodiment, each of the conductive lines 502 includes a barrier layer 512 and a conductive fill material 510.

[0048] In an embodiment, the barrier layer 512 is a metal silicide or germanide layer, such as described above. In one embodiment, the metal silicide or germanide layer includes M(Ga)CSi or M(Ga)CGe. In a specific such embodiment, the metal silicide or germanide layer has a total composition including between 2-25 atomic % gallium. In a particular such embodiment, the total composition includes M between 10-60 atomic %, C between 2-50 atomic %, Si or Ge between 2-50 atomic %. In an embodiment, the metal silicide or germanide layer further includes aluminum (Al). In a specific such embodiment, in the case that Al is included, the total composition includes Al between 2-25 atomic %.

[0049] In an embodiment, M is selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) and vanadium (V). In an embodiment, the conductive fill material 510 is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.

[0050] Accordingly, in an embodiment, an integrated circuit structure includes a feature having a surface (conductive line trench of a back end-of-line (BEOL) metallization layer). A metal silicide or germanide layer 512 is on the surface of the conductive line trench. In one such embodiment, the metal silicide or germanide layer 512 is a barrier layer for a conductive line 502.

[0051] In an embodiment, ILD lines 504 are composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0052] It is to be appreciated that the layers and materials described in association with Figure 5 are typically formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, although not depicted, the structure depicted in Figure 5 may be fabricated on underlying lower level back end of line (BEOL) interconnect layers.

[0053] In a second such aspect, Figures 6A and 6B illustrate cross-sectional views of semiconductor devices having a metal silicide or germanide layer on a source or drain region, in accordance with an embodiment of the present invention.

[0054] Referring to Figure 6A, a semiconductor structure 600 includes a gate structure 602 above a substrate 604. The gate structure 602 includes a gate dielectric layer 602A, a workfunction layer 602B, and a gate fill 602C. A source region 608 and a drain region 610 are on opposite sides of the gate structure 602. Source or drain contacts 612 are electrically connected to the source region 608 and the drain region 610, and are spaced apart of the gate structure 602 by one or both of an inter-layer dielectric layer 614 or gate dielectric spacers 616. The source region 608 and the drain region 610 are regions of the substrate 604.

[0055] In an embodiment, the source or drain contacts 612 include a metal silicide or germanide layer 612A, such as described above, and a conductive trench fill material 612B. In one embodiment, the metal silicide or germanide layer includes M(Ga)CSi or M(Ga)CGe. In a specific such embodiment, the metal silicide or germanide layer has a total composition including between 2-25 atomic % gallium. In a particular such embodiment, the total composition includes M between 10-60 atomic %, C between 2-50 atomic %, Si or Ge between 2-50 atomic %. In an embodiment, the metal silicide or germanide layer further includes aluminum (Al). In a specific such embodiment, in the case that Al is included, the total composition includes Al between 2-25 atomic %.

[0056] In an embodiment, M is selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) and vanadium (V). In an embodiment, the conductive trench fill material 612B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0057] Referring to Figure 6B, a semiconductor structure 650 includes a gate structure 652 above a substrate 654. The gate structure 652 includes a gate dielectric layer 652A, a workfunction layer 652B, and a gate fill 652C. A source region 658 and a drain region 660 are on opposite sides of the gate structure 652. Source or drain contacts 662 are electrically connected to the source region 658 and the drain region 660, and are spaced apart of the gate structure 652 by one or both of an inter-layer dielectric layer 664 or gate dielectric spacers 666. The source region 658 and the drain region 660 are epitaxial and/or embedded material regions formed in etched-out regions of the substrate 654. As is depicted, in an embodiment, the source region 658 and the drain region 660 are raised source and drain regions.

[0058] In an embodiment, the source or drain contacts 662 include a metal silicide or germanide layer 662A, such as described above, and a conductive trench fill material 662B. In one embodiment, the metal silicide or germanide layer includes M(Ga)CSi or M(Ga)CGe. In a specific such embodiment, the metal silicide or germanide layer has a total composition including between 2-25 atomic % gallium. In a particular such embodiment, the total composition includes M between 10-60 atomic %, C between 2-50 atomic %, Si or Ge between 2-50 atomic %. In an embodiment, the metal silicide or germanide layer further includes aluminum (Al). In a specific such embodiment, in the case that Al is included, the total composition includes Al between 2-25 atomic %.

[0059] In an embodiment, M is selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) and vanadium (V). In an embodiment, the conductive trench fill material 612B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0060] Accordingly, in an embodiment, referring collectively to Figures 6A and 6B, an integrated circuit structure includes a feature having a surface (source or drain contact trench exposing a semiconductor source or drain structure). A metal silicide or germanide layer 612A or 662A is on the surface of the source or drain contact trench. It is to be appreciated that conventional silicide or germanide processes involve consumption of an exposed silicon or germanium material of a source or drain regions. Such consumption can degrade device performance. In contrast, in accordance with an embodiment of the present disclosure, a surface (649 or 699) of the semiconductor source (608 or 658) or drain (610 or 660) structure is not eroded or consumed, or is not substantially eroded or consumed beneath the source or drain contact trench. In one such embodiment, the lack of consumption or erosion arises from the deposition of an as-deposited silicide or germanide, in contrast to a conventional consumption process.

[0061] In a third such aspect, one or more embodiments described herein are directed to fabricating semiconductor devices, such as for metal oxide semiconductor (MOS) device fabrication. As an example, Figure 7A illustrates a cross-sectional view of a non-planar semiconductor device having a metal silicide or germanide layer as a workfunction layer of a gate electrode, in accordance with an embodiment of the present disclosure. Figure 7B illustrates a plan view taken along the a-a’ axis of the semiconductor device of Figure 7A, in accordance with an embodiment of the present disclosure.

[0062] Referring to Figure 7A, a semiconductor structure or device 700 includes a non- planar active region (e.g., a fin structure including protruding fin portion 704 and sub-fin region 705) formed from substrate 702, and within isolation region 706. A gate line 708 is disposed over the protruding portions 704 of the non-planar active region as well as over a portion of the isolation region 706. As shown, gate line 708 includes a gate electrode 750/799 and a gate dielectric layer 752. In one embodiment, gate line 708 may also include a dielectric cap layer 754. A gate contact 714, and overlying gate contact via 716 are also seen from this perspective, along with an overlying metal interconnect 760, all of which are disposed in inter-layer dielectric stacks or layers 770. Also seen from the perspective of Figure 7A, the gate contact 714 is, in one embodiment, disposed over isolation region 706, but not over the non-planar active regions.

[0063] In accordance with an embodiment of the present disclosure, the layer 799 of gate electrode 750/799 is a metal silicide or germanide layer, such as described above. In one embodiment, the metal silicide or germanide layer 799 is in a gate trench, and is on or above gate dielectric layer 752. In one embodiment, an intervening ALD reliability layer may also be included between the metal silicide or germanide layer 799 and the gate dielectric layer 752. In one such embodiment, the metal silicide or germanide layer 799 is a workfunction layer of a metal gate electrode of a transistor 700 of the integrated circuit structure. In a particular embodiment, the transistor 700 is an N-type (NMOS) transistor, and the metal silicide or germanide layer 799 has an N-type workfunction. In an embodiment, the workfunction is between about 3.9 eV and about 4.2 eV.

[0064] Accordingly, in an embodiment, the semiconductor structure or device 700 has a feature (gate line 708) having a surface (gate dielectric layer 752). A metal silicide or germanide layer (layer 799 of gate electrode 750/799) is gate dielectric layer 752. In one embodiment, the metal silicide or germanide layer 799 includes M(Ga)CSi or M(Ga)CGe. In a specific such embodiment, the metal silicide or germanide layer 799 has a total composition including between 2-25 atomic % gallium. In a particular such embodiment, the total composition includes M between 10-60 atomic %, C between 2-50 atomic %, Si or Ge between 2-50 atomic %. In an embodiment, the metal silicide or germanide layer 799 further includes aluminum (Al). In a specific such embodiment, in the case that Al is included, the total composition includes Al between 2-25 atomic %. In an embodiment, M is selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) and vanadium (V).

[0065] Referring to Figure 7B, the gate line 708 is shown as disposed over the protruding fin portions 704. Source and drain regions 704A and 704B of the protruding fin portions 704 can be seen from this perspective. In one embodiment, the source and drain regions 704A and 704B are doped portions of original material of the protruding fin portions 704. In another embodiment, the material of the protruding fin portions 704 is removed and replaced with another semiconductor material, e.g., by epitaxial deposition. In either case, the source and drain regions 704A and 704B may extend below the height of dielectric layer 706, i.e., into the sub-fin region 705.

[0066] In an embodiment, the semiconductor structure or device 700 is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three- dimensional body. In one such embodiment, the gate electrode and gate electrode materials of gate lines 708 surround at least a top surface and a pair of sidewalls of the three-dimensional body.

[0067] Substrate 702 may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, substrate 702 is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, antimony, boron, gallium or a combination thereof, to form active region 704. In one embodiment, the concentration of silicon atoms in bulk substrate 702 is greater than 97%. In another embodiment, bulk substrate 702 is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. Bulk substrate 702 may alternatively be composed of a group III-V material. In an embodiment, bulk substrate 702 is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate 702 is composed of a III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, magnesium, beryllium, zinc, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

[0068] Isolation region 706 may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, the isolation region 706 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

[0069] In an embodiment, the gate dielectric layer 752 is composed of a high-K material. For example, in one embodiment, the gate dielectric layer 752 is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the substrate 702. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 752 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride.

[0070] In an embodiment, layer 750 of the gate electrode 750/799 is composed of a non- workfunction-setting conductive fill material formed above the metal silicide workfunction- setting layer 799. In one such embodiment, the conductive fill material 750 includes a material such as but not limited to, tungsten (W), aluminum (Al), or copper (Cu). In one embodiment, one or more conductive barrier layers (such as titanium nitride or tantalum nitride) is between layers 750 and 799 of the gate electrode. In some implementations, the gate electrode may consist of a“U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0071] In an embodiment, the dielectric cap layer 754 and/or dielectric spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent or overlying conductive contacts, such as self-aligned contacts. For example, in one embodiment, the dielectric cap layer 754 and/or dielectric spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

[0072] Gate contact 714, overlying gate contact via 716, and/or overlying metal interconnect 760 may be composed of a conductive material. In an embodiment, one or more of the contacts, interconnects or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

[0073] In an embodiment (although not shown), providing structure 700 involves formation of a contact pattern which is essentially perfectly aligned to an existing gate pattern while eliminating the use of a lithographic step with exceedingly tight registration budget. In one such embodiment, this approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.

[0074] Furthermore, the gate stack structure 708 may be fabricated by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF₆. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH₄OH or

tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.

[0075] In an embodiment, one or more approaches described herein contemplate essentially a dummy and replacement gate process in combination with a dummy and

replacement contact process to arrive at structure 700. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature anneal of at least a portion of the permanent gate stack. For example, in a specific such embodiment, an anneal of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed, is performed at a temperature greater than approximately 600 degrees Celsius. The anneal is performed prior to formation of the permanent contacts.

[0076] Referring again to Figure 7A, the arrangement of semiconductor structure or device 700 places the gate contact over isolation regions. Such an arrangement may be viewed as inefficient use of layout space in certain applications. In another embodiment, however, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region. In general, prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via, one or more embodiments of the present disclosure include first using a gate aligned trench contact process. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e.g., for integrated circuit fabrication. In an embodiment, a trench contact pattern is formed as aligned to an existing gate pattern. By contrast, conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches. For example, a conventional process may include patterning of a poly (gate) grid with separate patterning of contact features.

[0077] It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. For example, in one embodiment, dummy gates need not ever be formed prior to fabricating gate contacts over active portions of the gate stacks. The gate stacks described above may actually be permanent gate stacks as initially formed. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a trigate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) or smaller technology node.

[0078] In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193nm immersion lithography (i193), extreme ultra-violet (EUV) and/or electron beam direct write (EBDW) lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

[0079] Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

[0080] Figure 8 illustrates a computing device 800 in accordance with one

implementation of the disclosure. The computing device 800 houses a board 802. The board 802 may include a number of components, including but not limited to a processor 804 and at least one communication chip 806. The processor 804 is physically and electrically coupled to the board 802. In some implementations the at least one communication chip 806 is also physically and electrically coupled to the board 802. In further implementations, the

communication chip 806 is part of the processor 804.

[0081] Depending on its applications, computing device 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[0082] The communication chip 806 enables wireless communications for the transfer of data to and from the computing device 800. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 806 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 800 may include a plurality of communication chips 806. For instance, a first communication chip 806 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 806 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0083] The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more structures fabricated to include a metal silicide or metal germanide film, in accordance with implementations of embodiments of the disclosure. The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0084] The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. In accordance with another implementation of

embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more structures fabricated to include a metal silicide or metal germanide film, in accordance with implementations of embodiments of the disclosure.

[0085] In further implementations, another component housed within the computing device 800 may contain an integrated circuit die that includes one or more structures fabricated to include a metal silicide or metal germanide film, in accordance with implementations of embodiments of the disclosure.

[0086] In various implementations, the computing device 800 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 800 may be any other electronic device that processes data.

[0087] Figure 9 illustrates an interposer 900 that includes one or more embodiments of the disclosure. The interposer 900 is an intervening substrate used to bridge a first substrate 902 to a second substrate 904. The first substrate 902 may be, for instance, an integrated circuit die. The second substrate 904 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 900 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 900 may couple an integrated circuit die to a ball grid array (BGA) 906 that can subsequently be coupled to the second substrate 904. In some embodiments, the first and second substrates 902/904 are attached to opposing sides of the interposer 900. In other embodiments, the first and second substrates 902/904 are attached to the same side of the interposer 900. And in further embodiments, three or more substrates are interconnected by way of the interposer 900.

[0088] The interposer 900 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further

implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[0089] The interposer may include metal interconnects 908 and vias 910, including but not limited to through-silicon vias (TSVs) 912. The interposer 900 may further include embedded devices 914, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 900. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 900.

[0090] Thus, embodiments described herein include gallium-based co-reactants for fabricating metal silicide and metal germanide films, and integrated circuit structures including such films.

[0091] The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0092] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. [0093] Example embodiment 1: A discrete acyclic molecule includes a gallium-based moiety having a central gallium atom, and a silicon-based moiety having a central silicon atom. The central silicon atom of the silicon-based moiety and the central gallium atom of the gallium- based moiety are covalently bonded to one another with a single bond. A neutral Lewis basic ligand is bonded to the central gallium atom of the gallium-based moiety.

[0094] Example embodiment 2: The discrete acyclic molecule of example embodiment 1, wherein the central gallium atom of the gallium-based moiety is bonded to two alkyl groups.

[0095] Example embodiment 3: The discrete acyclic molecule of example embodiment 1 or 2, wherein the central silicon atom of the silicon-based moiety is bonded to three trialkyl-silyl groups.

[0096] Example embodiment 4: The discrete acyclic molecule of example embodiment 1, 2 or 3, wherein the neutral Lewis basic ligand is selected from the group consisting of a P(alkyl)3 ligand, an N-heterocyclic carbene ligand, and amine ligand, and a sulfide ligand.

[0097] Example embodiment 5: The discrete acyclic molecule of example embodiment 1, wherein the chemical formula of the discrete acyclic molecule is represented by:

.

[0098] Example embodiment 6: A discrete acyclic molecule includes a gallium-based moiety having a central gallium atom, and a germanium-based moiety having a central germanium atom. The central germanium atom of the germanium-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. A neutral Lewis basic ligand is bonded to the central gallium atom of the gallium-based moiety.

[0099] Example embodiment 7: The discrete acyclic molecule of example embodiment 6, wherein the central gallium atom of the gallium-based moiety is bonded to two alkyl groups.

[00100] Example embodiment 8: The discrete acyclic molecule of example embodiment 6 or 7, wherein the central germanium atom of the germanium-based moiety is bonded to three trialkyl-germyl groups.

[00101] Example embodiment 9: The discrete acyclic molecule of example embodiment 6, 7 or 8, wherein the neutral Lewis basic ligand is selected from the group consisting of a P(alkyl)3 ligand, an N-heterocyclic carbene ligand, and amine ligand, and a sulfide ligand.

[00102] Example embodiment 10: The discrete acyclic molecule of example embodiment 6, wherein the chemical formula of the discrete acyclic molecule is represented by:

.

[00103] Example embodiment 11: A method of fabricating a metal silicide or germanide film includes providing a substrate in an atomic layer deposition (ALD) chamber, the substrate having a surface. The method also includes co-reacting a metal (M) halide source and a discrete acyclic molecule source to form a layer on the surface of the substrate, the layer including M(Ga)CSi or M(Ga)CGe.

[00104] Example embodiment 12: The method of example embodiment 11, further including co-reacting the metal (M) halide source and the discrete acyclic molecule source with an organo-aluminum source to further provide aluminum (Al) in the layer of M(Ga)CSi or M(Ga)CGe.

[00105] Example embodiment 13: The method of example embodiment 11 or 12, wherein the metal (M) halide source is a metal (M) chloride source.

[00106] Example embodiment 14: The method of example embodiment 11, 12 or 13, wherein M is selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) and vanadium (V).

[00107] Example embodiment 15: The method of example embodiment 11, 12, 13 or 14, wherein each of the molecules of the discrete acyclic molecule source includes a gallium-based moiety having a central gallium atom, a silicon-based moiety having a central silicon atom, wherein the central silicon atom of the silicon-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond, and a neutral Lewis basic ligand bonded to the central gallium atom of the gallium-based moiety.

[00108] Example embodiment 16: The method of example embodiment 11, 12, 13 or 14, wherein each of the molecules of the discrete acyclic molecule source includes a gallium-based moiety having a central gallium atom, a germanium-based moiety having a central germanium atom, wherein the central germanium atom of the germanium-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond, and a neutral Lewis basic ligand bonded to the central gallium atom of the gallium-based moiety.

[00109] Example embodiment 17: The method of example embodiment 11, 12, 13 or 14, 15 or 16, wherein the layer including M(Ga)CSi or M(Ga)CGe has a total composition including between 2-25 atomic % gallium.

[00110] Example embodiment 18: An integrated circuit structure includes a feature having a surface. A metal silicide or germanide layer is on the surface of the feature. The metal silicide or germanide layer includes M(Ga)CSi or M(Ga)CGe and has a total composition including between 2-25 atomic % gallium. M is selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) and vanadium (V).

[00111] Example embodiment 19: The method of example embodiment 18, wherein the metal silicide or germanide layer further includes aluminum (Al).

[00112] Example embodiment 20: The method of example embodiment 18 or 19, wherein the feature is a gate trench, and the surface is a gate dielectric layer.

[00113] Example embodiment 21: The method of example embodiment 20, wherein the metal silicide or germanide layer is a workfunction layer of a metal gate electrode of a transistor of the integrated circuit structure.

[00114] Example embodiment 22: The method of example embodiment 18 or 19, wherein the feature is a conductive line trench of a back end-of-line (BEOL) metallization layer.

[00115] Example embodiment 23: The method of example embodiment 22, wherein the metal silicide or germanide layer is barrier layer for a conductive line.

[00116] Example embodiment 24: The method of example embodiment 18 or 19, wherein the feature is a source or drain contact trench exposing a semiconductor source or drain structure.

[00117] Example embodiment 25: The method of example embodiment 24, wherein a surface of the semiconductor source or drain structure is not eroded beneath the source or drain contact trench.

Claims

What is claimed is: 1. A discrete acyclic molecule, comprising:

a gallium-based moiety having a central gallium atom;

a silicon-based moiety having a central silicon atom, wherein the central silicon atom of the silicon-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond; and

a neutral Lewis basic ligand bonded to the central gallium atom of the gallium-based moiety.

2. The discrete acyclic molecule of claim 1, wherein the central gallium atom of the gallium- based moiety is bonded to two alkyl groups.

3. The discrete acyclic molecule of claim 1, wherein the central silicon atom of the silicon-based moiety is bonded to three trialkyl-silyl groups.

4. The discrete acyclic molecule of claim 1, wherein the neutral Lewis basic ligand is selected from the group consisting of a P(alkyl)3 ligand, an N-heterocyclic carbene ligand, and amine ligand, and a sulfide ligand.

5. The discrete acyclic molecule of claim 1, wherein the chemical formula of the discrete acyclic molecule is represented by:

.

6. A discrete acyclic molecule, comprising:

a gallium-based moiety having a central gallium atom;

a germanium-based moiety having a central germanium atom, wherein the central germanium atom of the germanium-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond; and a neutral Lewis basic ligand bonded to the central gallium atom of the gallium-based moiety.

7. The discrete acyclic molecule of claim 6, wherein the central gallium atom of the gallium- based moiety is bonded to two alkyl groups.

8. The discrete acyclic molecule of claim 6, wherein the central germanium atom of the germanium-based moiety is bonded to three trialkyl-germyl groups.

9. The discrete acyclic molecule of claim 6, wherein the neutral Lewis basic ligand is selected from the group consisting of a P(alkyl)₃ ligand, an N-heterocyclic carbene ligand, and amine ligand, and a sulfide ligand.

10. The discrete acyclic molecule of claim 6, wherein the chemical formula of the discrete acyclic molecule is represented by:

.

11. A method of fabricating a metal silicide or germanide film, the method comprising:

providing a substrate in an atomic layer deposition (ALD) chamber, the substrate having a surface; and

co-reacting a metal (M) halide source and a discrete acyclic molecule source to form a layer on the surface of the substrate, the layer comprising M(Ga)CSi or M(Ga)CGe.

12. The method of claim 11, further comprising co-reacting the metal (M) halide source and the discrete acyclic molecule source with an organo-aluminum source to further provide aluminum (Al) in the layer comprising M(Ga)CSi or M(Ga)CGe.

13. The method of claim 11, wherein the metal (M) halide source is a metal (M) chloride source.

14. The method of claim 11, wherein M is selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) and vanadium (V).

15. The method of claim 11, wherein the molecules of the discrete acyclic molecule source each comprise a gallium-based moiety having a central gallium atom, a silicon-based moiety having a central silicon atom, wherein the central silicon atom of the silicon-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond, and a neutral Lewis basic ligand bonded to the central gallium atom of the gallium-based moiety.

16. The method of claim 11, wherein the molecules of the discrete acyclic molecule source each comprise a gallium-based moiety having a central gallium atom, a germanium-based moiety having a central germanium atom, wherein the central germanium atom of the germanium-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond, and a neutral Lewis basic ligand bonded to the central gallium atom of the gallium-based moiety.

17. The method of claim 11, wherein the layer comprising M(Ga)CSi or M(Ga)CGe has a total composition including between 2-25 atomic % gallium.

18. An integrated circuit structure comprising:

a feature having a surface;

a metal silicide or germanide layer on the surface of the feature, the metal silicide or

germanide layer comprising M(Ga)CSi or M(Ga)CGe and having a total composition including between 2-25 atomic % gallium, wherein M is selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) and vanadium (V).

19. The integrated circuit structure of claim 18, wherein the metal silicide or germanide layer further comprises aluminum (Al).

20. The integrated circuit structure of claim 18, wherein the feature is a gate trench, and the surface is a gate dielectric layer.

21. The integrated circuit structure of claim 20, wherein the metal silicide or germanide layer is a workfunction layer of a metal gate electrode of a transistor of the integrated circuit structure.

22. The integrated circuit structure of claim 18, wherein the feature is a conductive line trench of a back end-of-line (BEOL) metallization layer.

23. The integrated circuit structure of claim 22, wherein the metal silicide or germanide layer is barrier layer for a conductive line.

24. The integrated circuit structure of claim 18, wherein the feature is a source or drain contact trench exposing a semiconductor source or drain structure.

25. The integrated circuit structure of claim 24, wherein a surface of the semiconductor source or drain structure is not eroded beneath the source or drain contact trench.