CN103988308B - 晶体管中的应变补偿 - Google Patents
晶体管中的应变补偿 Download PDFInfo
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- CN103988308B CN103988308B CN201180075405.6A CN201180075405A CN103988308B CN 103988308 B CN103988308 B CN 103988308B CN 201180075405 A CN201180075405 A CN 201180075405A CN 103988308 B CN103988308 B CN 103988308B
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Abstract
提供了具有包括交替的压缩和拉伸应变外延材料层的沟道区的晶体管结构。交替的外延层可以在单栅极晶体管结构和多栅极晶体管结构中形成沟道区。在可替换的实施例中,选择性地蚀刻掉两个交替的层中的一层,以形成剩余材料的纳米带或纳米线。得到的应变纳米带或纳米线形成晶体管结构的沟道区。还提供了包括晶体管的计算设备,所述晶体管包括由交替的压缩和拉伸应变外延层组成的沟道区,以及包括晶体管的计算设备,所述晶体管包括由应变的纳米带或纳米线组成的沟道区。
Description
技术领域
本发明的实施例总体上涉及集成电路器件,更具体地,涉及晶体管、多栅极晶体管、PMOS和NMOS晶体管以及纳米带和纳米线晶体管。
背景技术
向着越来越小的更高度集成的电路(IC)及其他半导体器件推进对用于构造器件的技术和材料提出了极高的要求。通常,集成电路芯片也称为微芯片、硅芯片或芯片。可以在各种常见设备中发现IC芯片,例如在计算机、汽车、电视机、游戏系统、CD播放器、和蜂窝电话中。典型地在硅晶圆(薄硅盘,具有例如300mm的直径)上构造多个IC芯片,并且在处理后,将晶圆切片以生成单个的芯片。具有在约90nm附近特征尺寸的1cm2的IC芯片可以包括上亿个部件。当前的技术将特征尺寸推进到甚至小于32nm。IC芯片的部件例如包括诸如CMOS(互补金属氧化物半导体)器件的晶体管、电容性结构、电阻性结构、和金属线,其在部件与外部器件之间提供电子连接。其他半导体器件例如包括各种二极管、激光器、光电检测器、和磁场传感器。
附图说明
图1A-B是示出三栅极晶体管结构的横截面视图的示意图。
图2A-B是示出双栅极晶体管结构的横截面视图的示意图。
图3A-B是示出在沟道区中包括纳米线或纳米带的晶体管结构的横截面视图的示意图。
图4示出了单栅极晶体管结构的横截面视图。
图5是说明用于制造晶体管的沟道区的方法的流程图。
图6是说明用于制造晶体管的沟道区的其他方法的流程图。
图7是根据本发明的实现方式构造的计算设备。
具体实施方式
随着晶体管元件的间距日益变小,源极和漏极区体积收缩,并且通过源极和漏极区提供单轴晶体管沟道应力变得越来越困难。在晶体管的沟道区中的应力可以改进晶体管性能。因此,在不依赖于源极和漏极区提供应力的情况下将应力包含在沟道区中的器件是有用的。本发明的实施例提供了具有从衬底给予应力的沟道结构的晶体管。还提供了包括夹层的压缩和拉伸层的沟道结构和制造这种沟道结构的方法。本发明的另外实施例提供了在沟道区中具有多个应变纳米带或纳米线的晶体管。有利地,本发明的实施例提供了具有应变的沟道结构的晶体管,所述应变的沟道结构具有相当大的高度同时在沟道结构中保持应变。
图1A-B显示了具有应变的沟道区的三栅极晶体管结构。图1B表示沿图1A的结构的1-1(垂直切入纸面)的视图。得到的横截面视图旋转45°。在图1A-B中,衬底105容纳沟道区,其包括相对应变的外延夹层110和115。相对应变的外延夹层110和115相对于衬底105表面上的材料或者是压缩应变的或者是拉伸应变的。例如,层110是拉伸应变的,层115是压缩应变的,或者相反地,层110是压缩应变的,层115是拉伸应变的。通过相对于衬底105材料或衬底105表面上的材料层(“衬底”)的晶格的晶格失配来产生相对应变的外延夹层110和115。为衬底105选择的材料例如可以是包括来自周期表的III、IV和/或V族的元素及其组合的任何材料。随后,在衬底105上在外延沉积过程中生长具有较大(较小)晶格常数的第一层110。生长的第一层110低于其临界层厚度,以确保在第一层110中保持完全的压缩(拉伸)应变。随后,在第一层100的顶部上在外延沉积过程中生长具有相对于衬底105的较小(较大)的晶格常数的第二层115。生长的第二层115低于其临界层厚度,以确保完全的拉伸(压缩)应变。在本发明的实施例中,在最小到无应变弛豫的情况下,可以将具有交替的压缩和拉伸应变样式的额外连续层110和115生长到极高的高度。通常,夹层可以包括纯元素和/或元素的混合物,例如Si和Ge、及III-V族半导体材料(包括在周期表的III和V族列中找到的元素的材料)。在本发明的实施例中,沟道结构可以包括量子势阱,在其中薄器件层相邻于与沟道材料相比具有较大带隙的层,或者夹在它们之间。在本发明的实施例中,衬底105包括SiXGe1-X,层110(或层115)包括SiYGe1-Y,其中,Y>X,层115(或层110)包括SiZGe1-Z,其中,Z<X、1>X≥0且1≥Y>0且1>Z≥0。在另外的实施例中,衬底105包括InP,层110(或层115)包括InXGa1-XAs,其中,1≥X>0.53,层115(或层110)包括InYGa1-YAs,其中,0.53>Y≥0。在进一步的实施例中,衬底105包括GaSb,层110(或层115)包括AlSb,层115(或层110)包括InAs。在进一步的另外实施例中,衬底105包括Ge,层110(或层115)包括SiXGe1-X,层115(或层110)包括InYGa1-YAs,其中,1≥X>0且1≥Y>0。在进一步的另外实施例中,衬底105是GaAs,层110(或层115)是GaAsXP1-X,其中,X是在1与0之间的数,层115(或层110)包括InYGa1-YP,其中,1≥Y>0.51。发现通过使用包括交替的压缩和拉伸应变外延材料的层的外延夹层结构,可以构造在层中保持应变的沟道结构,同时具有比在晶体管的沟道区中产生应变的传统方法更高的高度。在本发明的实施例中,晶体管的沟道区具有高度h1,其范围在10nm到100nm之间或在25nm到85nm之间,尽管其他高度也是可能的。尽管在图1中显示了相对应变的外延夹层110和115具有12层,但115和110也可以具有其他层数,例如包括及在3和25层之间,或者在5和25层之间,然而也可以是其他数量。
在图1A中,源极和漏极区120和125与沟道区110和115的端部邻接。在本发明的实施例中,在沟道区中保持相对于衬底的沟道应变,无需使用在沟道中产生应变的源极/漏极材料。晶体管结构还包括栅极电介质135和栅极电极140。如图1B中可以见到,栅极电介质135布置在沟道区的三个侧上:两个侧横切第三侧。栅极电极140布置在栅极电介质135上。可任选的,绝缘隔离层145和146(图1A)与栅极电介质135和栅极电极140邻接。典型地将晶体管结构覆盖在绝缘电介质层中,绝缘电介质层被部分显示为绝缘区150和151(图1A)。
图2A-B显示了具有应变的沟道区的双栅极(两个栅极)晶体管结构。图2B表示沿图2A的结构的2-2(垂直切入纸面)的视图。得到的横截面视图旋转45°。在图2A-B中,衬底205容纳沟道区,其包括相对应变的外延夹层210和215。相对应变的外延夹层210和215相对于衬底205表面上的材料或者是压缩应变的或者是拉伸应变的。例如,层210是拉伸应变的,层215是压缩应变的,或者相反地,层210是压缩应变的,层215是拉伸应变的。通过相对于衬底205材料或衬底105表面上的材料层(“衬底”)的晶格的晶格失配来产生相对应变的外延夹层210和215。为衬底205选择的材料例如可以是包括来自周期表的III、IV和/或V族的元素及其组合的任何材料。随后,在衬底205上在外延沉积过程中生长具有较大(较小)晶格常数的第一层210。生长的第一层210低于其临界层厚度,以确保在第一层210中保持完全的压缩(拉伸)应变。随后,在第一层200的顶部上在外延沉积过程中生长具有相对于衬底205的较小(较大)晶格常数的第二层215。生长的第二层215低于其临界层厚度,以确保完全的拉伸(压缩)应变。在本发明的实施例中,在最小到无应变弛豫的情况下,可以将具有交替的压缩和拉伸应变样式的额外连续层210和215生长到极高的高度。通常,夹层可以包括纯元素和/或元素的混合物,例如Si和Ge、及III-V族半导体材料(包括在周期表的III和V族列中找到的元素的材料)。在本发明的实施例中,沟道结构可以包括量子势阱,在其中薄器件层相邻于与沟道材料相比具有较大带隙的层,或者夹在它们之间。在本发明的实施例中,衬底205包括SiXGe1-X,层210(或层215)包括SiYGe1-Y,其中,Y>X,层215(或层210)包括SiZGe1-Z,其中,Z<X、1>X≥0、1≥Y>0且1>Z≥0。在另外的实施例中,衬底205包括InP,层210(或层215)包括InXGa1-XAs,其中,1≥X>0.53,层215(或层210)包括InYGa1-YAs,其中,0.53>Y≥0。在进一步的实施例中,衬底205包括GaSb,层210(或层215)包括AlSb,层215(或层210)包括InAs。在进一步的另外实施例中,衬底205包括Ge,层210(或层215)包括SiXGe1-X,层215(或层210)包括InYGa1-YAs,其中,1≥X>0且1≥Y>0。在进一步的另外实施例中,衬底205是GaAs,层210(或层215)是GaAsXP1-X,其中,1>X≥0是在1与0之间的数,层215(或层210)包括InYGa1-YP,其中,1≥Y>0.51。发现通过使用包括交替的压缩和拉伸应变外延材料的层的外延夹层结构,可以构造在层中保持应变的沟道结构,同时其具有比在晶体管的沟道区中产生应变的传统方法更大的高度。在本发明的实施例中,晶体管的沟道区具有高度h1,其范围在10nm到100nm之间或在25nm到85nm之间,尽管其他高度也是可能的。尽管在图2中显示了相对应变的外延夹层210和215具有12层,但210和215也可以具有其他层数,例如包括及在3和25层之间,或者在5和25层之间。
在图2A中,源极和漏极区220和225与沟道区210和215的端部邻接。在本发明的实施例中,在沟道区中保持相对于衬底的沟道应变,无需使用源极/漏极应力源。在沟道区210和215的侧上布置另外的绝缘区252。在图2B中,晶体管结构还包括栅极电介质235和栅极电极240。将栅极电介质235布置在沟道区的两个相反侧上。将栅极电极240布置在栅极电介质235上。可任选的,绝缘隔离层245和246(图2A)与栅极电介质235和栅极电极240邻接。典型地将晶体管结构覆盖在绝缘电介质层中,所述绝缘电介质层被部分显示为绝缘区250和251(图2A)。
图3A-B显示了具有应变的纳米带或纳米线沟道区的晶体管结构。通常,可以认为纳米带具有大于高度的宽度(长度尺寸是沿线或带的长度的尺寸)。图3A-B的结构类似于图1-2(A-B)的结构,但在实施例中,将拉伸层蚀刻掉,以产生PMOS纳米线或纳米带沟道区,或者相反地,将压缩层蚀刻掉,以产生NMOS纳米线或纳米带沟道区。图3B表示沿图3A的结构的3-3(垂直切入纸面)的视图。得到的横截面视图旋转45°。在图3A-B中,衬底305容纳包括纳米带或纳米线310的沟道区。使纳米带或纳米线310相对于衬底形变。在本发明的实施例中,纳米带或纳米线310在PMOS沟道中压缩应变,在NMOS沟道中拉伸应变。可任选地,外延夹层区315和316位于在源极和漏极320和325与纳米带或纳米线310区之间的晶体管结构中。可任选的外延夹层区315和316包括呈现交替的压缩和拉伸(或者反之亦然)应变层的层。通常,夹层可以包括纯元素和/或元素的混合物,例如Si和Ge、及III-V族半导体材料(包括由周期表的III和V族列中找到的元素组成的材料)。在本发明的实施例中,具有压缩应变纳米线或纳米带的晶体管具有包括SiXGe1-X的衬底305表面材料、包括SiYGe1-Y的第二外延材料、和包括SiZGe1-Z的第三外延材料,其中,Y>X,Z<X、1>X≥0且1≥Y>0且1>Z≥0。在具有压缩应变纳米线或纳米带的可替换的实施例中,衬底305包括InP,第二外延材料包括InXGa1-XAs,其中,1≥X>0.53,第三外延材料包括InYGa1-YAs,其中,0.53>Y≥0,或者衬底305包括GaSb,第二外延材料包括AlSb,第三外延材料包括InAs。在具有压缩应变纳米线或纳米带的进一步实施例中,衬底305包括Ge,第二外延材料包括SiXGe1-X,其中,1≥X>0,第三外延材料包括InYGa1-YAs,其中,且1≥Y>0,或者衬底305包括GaAs,第二外延材料包括GaAsXP1-X,其中,1>X≥0,第三外延材料包括InYGa1-YP,其中,1≥Y>0.51。在具有拉伸应变纳米线或纳米带的实施例中,衬底305包括SiXGe1-X,第二外延材料包括SiYGe1-Y,第三外延材料包括SiZGe1-Z,其中,Y<X,Z>X、1>X≥0且1>Y>0且1>Z≥0。在具有拉伸应变纳米线或纳米带的进一步实施例中,衬底305包括Ge,第二外延材料包括InYGa1-YAs,其中,1≥Y>0,第三外延材料包括SiXGe1-X,其中,且1≥X>0,或者衬底305包括GaAs,第二外延材料包括InYGa1-YP,其中,1≥Y>0.51,第三外延材料包括GaAsXP1-X,其中,1>X≥0。在随后的处理事件中,蚀刻掉第二外延材料(或者部分地,留下外延夹层区315和316,或者完全地,不留下外延夹层区315和316),以产生包括第三外延材料的纳米线或纳米带310。在本发明的实施例中,纳米线310例如包括Ge、SiXGe1-X,或者由包括来自周期表的III、IV和V族的一个或多个元素的材料组成。尽管在图3A-B中显示了四条纳米线或纳米带310,但其他数量的纳米线或纳米带310也是可能的,例如在晶体管中纳米线或纳米带的数量包括或在1到10之间、在2到10之间、在3到10之间,然而也可以是其他数量。
在图3A中,源极和漏极区320和325与可任选的外延夹层区315和316邻接,或者与纳米带或纳米线310的端部(未示出)邻接。在本发明的实施例中,在沟道区中保持相对于衬底的沟道应变,无需使用源极/漏极应力源。在实施例中,不存在外延夹层区315和316,纳米线或纳米带310接触源极和漏极区320和325。绝缘层330布置在纳米带或纳米线310与衬底305之间,并能够充当在栅极与衬底305之间的底部栅极隔离。在图3A-B中,晶体管结构还包括栅极电介质335和栅极电极340。将栅极电介质335布置在纳米带或纳米线310上。将栅极电极340布置在栅极电介质335上。可任选的,绝缘隔离层345和346与栅极电介质335和栅极电极340邻接。典型地将晶体管结构覆盖在绝缘电介质层中,绝缘电介质层被部分地显示为绝缘区350和351。
图4示出了具有应变的沟道区的单栅极晶体管结构。对于单栅极晶体管,其他结构也是可能的,例如具有相对于彼此不同定向的部件的结构,和具有不同形状和/或大小的部件的结构。例如,也可以是具有相对于沟道区不凹陷的源极和漏极区的单栅极晶体管结构。在图4中,衬底层405由可任选的绝缘沟槽407包围,并容纳包括相对应变的外延夹层410和415的沟道区。相对应变的外延夹层410和415相对于衬底或者是压缩应变的或者是拉伸应变的。例如,层410是拉伸应变的,层415是压缩应变的,或者相反地,层410是压缩应变的,层415是拉伸应变的。通过相对于衬底晶格的晶格失配来产生相对应变的外延夹层410和415。为衬底405所选择的材料例如可以是包括来自周期表的III、IV和/或V族的元素及其组合的任何材料。通常,外延夹层410和415可以包括纯元素和/或元素的混合物,例如Si和Ge、及III-V族半导体材料(包括在周期表的III和V族列中找到的元素的材料)。衬底405与外延夹层410和415可以包括为相对于图1-2(A-B)的衬底和外延夹层所说明的材料。可任选的绝缘沟槽407包括绝缘材料,可以将晶体管结构与组成半导体芯片的其他器件电隔离。将源极和漏极区420和425显示为相对于沟道区凹陷。栅极电极区430在沟道区的一侧上,并由栅极电介质区435与沟道区分离。在器件制造过程中形成可任选的绝缘隔离层440,以便于制造并用于电隔离晶体管栅极区。尽管在图4中显示了相对应变的外延夹层410和415具有6层,但层415和410也可以具有其他数量,例如包括及在3和25层之间,或者在5和25层之间,然而也可以是其他数量。
图5说明了用于为三栅极或双栅极晶体管结构制造应变的外延层叠沟道区的方法。在图5中,提供衬底,在其表面上的具有第一外延材料,所述第一外延材料具有第一晶格常数。第一外延材料可以是外延材料的层。在衬底的表面上沉积第二外延材料,其具有大于(压缩膜)或小于(拉伸膜)第一外延材料的晶格常数的第二晶格常数。随后将第三外延材料沉积在第二外延材料上,第三外延材料相对于衬底的晶格常数具有较大的晶格常数(压缩)或较小的晶格常数(拉伸)。如果作为压缩层沉积第二层,那么就作为拉伸层沉积第三层,第二和第三膜构成应变补偿叠层。相反地,如果作为拉伸层沉积第二层,那么就作为压缩层沉积第三层。例如可以借助超高真空化学气相沉积(UHV-CVD)、快速加热化学气相沉积(RTCVD)或分子束外延(MBE)来沉积外延材料。将交替的外延拉伸和压缩应变材料层(分别具有相对于衬底的较小或较大晶格常数的材料)沉积在衬底上,以产生呈现双轴应变的层的堆叠。人们认为在晶体管的沟道区的制造过程中,拉伸和压缩夹层(在相对方向上应变并彼此相邻的层)对于弛豫更为稳定,因为形成以使得一层松弛的位错会增大在另一个中的应变。因为平衡的叠层系统的弛豫要求是相反的,可以为沟道区产生更大的总临界厚度。通常,对于大于1.3%的晶格失配,不使用应变补偿的单膜叠层在无驰豫或缺陷形成的情况下不能生长超过50nm高。在本发明的实施例中,层的堆叠可以从3到25层或者从5到25层,和/或10nm和100nm或在25nm到85nm之间的高度。相对于图1A-B和2A-B说明了用于外延层的示例性的材料。将包括相对应变的夹层的结构构图为晶体管沟道尺寸(例如构图为用于finfet结构的鳍片),将衬底双轴应变转换为衬底单轴应变。随后将栅极电介质材料沉积在层叠的晶体管沟道区的一个、两个或三个侧上(如所示的,例如相对于图1A-B、2A-B和4)。随后将栅极电极材料沉积在栅极电介质材料上。
图6说明了用于为包括应变的纳米带或纳米线的晶体管制造沟道区的方法。在图6中,提供衬底,在其表面上具有第一外延材料,所述第一外延材料具有第一晶格常数。第一外延材料可以是材料的层。在衬底的表面上沉积第二外延材料,其具有大于(压缩膜)或小于(拉伸膜)第一外延材料的晶格常数的第二晶格常数。随后将第三外延材料沉积在第二外延材料上,第三外延材料相对于衬底的晶格常数具有较大的晶格常数(压缩)或较小的晶格常数(拉伸)。如果作为压缩层沉积第二层,那么就作为拉伸层沉积第三层,第二和第三膜构成应变补偿叠层。相反地,如果作为拉伸层沉积第二层,那么就作为压缩层沉积第三层。例如可以借助UHV-CVD、RTCVD或MBE来沉积外延材料。将交替的外延拉伸和压缩应变材料层(分别具有相对于衬底的较小或较大晶格常数的材料)沉积在衬底上,产生呈现双轴应变的层的堆叠。人们认为在晶体管的沟道区的制造过程中,拉伸和压缩夹层(在相对的方向上应变并彼此相邻的层)对于弛豫更为稳定,因为形成以使得一层松弛的位错会增大在另一个中的应变。因为在制造过程中平衡了系统的弛豫要求,可以为应变的沟道区产生更大的总临界厚度。通常,对于大于1.3%的晶格失配,没有使用应变补偿的单膜叠层在无驰豫或缺陷形成的情况下不能生长超过50nm。相对于图3A-B说明了用于外延层的示例性的材料。
将包括相对应变层的结构构图为晶体管纳米线或纳米带沟道尺寸(例如构图为鳍片),将衬底双轴应变转换为衬底单轴应变。随后围绕经构图的沟道区和形成于沟道区端部的源极/漏极区形成虚拟栅极。可任选地,虚拟栅极区由在两侧上的隔离层限定。去除虚拟栅极材料,并执行选择性蚀刻以去除压缩应变外延层或拉伸应变外延层,产生剩余材料的纳米线或纳米带。在源极与漏极区之间悬挂纳米线或纳米带。在本发明的单实施例中,在选择性蚀刻后在纳米线或纳米带的端部保留拉伸和压缩夹层的区域。这些夹层区在纳米线或纳米带的端部与源极/漏极区之间。在其他实施例中,在选择性蚀刻后没有保留拉伸和压缩夹层的区域。在(围绕)露出的纳米带或纳米线的四个侧上沉积栅极电介质材料。随后将栅极电极材料沉积在栅极电介质覆盖的纳米带或纳米线的四个侧上的栅极电介质材料之上,产生例如根据图3A-B的沟道区结构。
栅极电介质材料例如包括绝缘材料,所述绝缘材料例如是二氧化硅(SiO2)、氮氧化硅、氮化硅、和/或高k电介质材料。通常,高k电介质是介电常数大于SiO2的介电常数的电介质材料。示例性的高k电介质材料包括二氧化铪(HfO2)、硅酸铪、氧化镧、铝酸镧、氧化锆(ZrO2)、硅酸锆、二氧化钛(TiO2)、五氧化钽(TaO5)、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、钽酸钪铅、和铌酸锌铅,及半导体领域中已知的其他材料。栅极电极材料例如包括诸如Ti、W、Ta、Al及其合金的材料,及具有诸如Er、Dy的稀土元素、或者诸如Pt的贵金属的合金,和诸如TaN和TiN的氮化物。用于源极和/或漏极的材料例如包括用于NMOS的Si、碳掺杂的Si、磷掺杂的Si和用于PMOS应用的硼掺杂的SiXGe1-X、硼掺杂的Ge、硼掺杂的GeXSn1-X和p掺杂的III-V族化合物。
用于介电层、部件和/或夹层电介质(ILD)的典型电介质材料包括二氧化硅和低k电介质材料。可用使用的另外的电介质材料包括碳掺杂氧化物(CDO)、氮化硅、氮氧化硅、碳化硅、诸如八氟环丁烷或聚四氟乙烯、氟硅酸盐玻璃(FSG)的有机聚合物、和/或诸如倍半硅氧烷、硅氧烷的有机硅酸盐或有机硅酸盐玻璃。电介质层可以包括微孔,以进一步减小介电常数。
本文所示的器件可以包括附加的结构,例如包围器件的绝缘层、附加的衬底层、将源极和漏极连接到IC器件的其他部件的金属沟槽和通孔,及其他附加的层和/或器件。例如取决于用于构造器件和所期望的器件特性的制造过程,为了简单而示出为一层的部件可以包括相同或不同材料的多个层。
将本发明的实现方式容纳在诸如半导体晶圆之类的衬底上。可以在其上形成根据本发明实施例的晶体管结构的衬底的表面例如包括H终止(氢终止)的硅、二氧化硅、硅、锗化硅、III-V族(或另外的周期表列标号方案中的13-14族)化合物半导体、主族氧化物、金属、和/或二元或混合金属氧化物。层和包括器件的层也可以说明为在其上构造了本发明的实施例的衬底或衬底的部分。在其上构造半导体器件的衬底基体典型地是半导体晶圆,将其切片以产生单个IC芯片。在其上构造芯片的基体衬底典型地是硅晶圆,尽管本发明的实施例不依赖于所用的衬底的类型。衬底也可以包括锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、锑化镓,和/或单独的或结合硅、二氧化硅的其他III-V族材料或者其他绝缘材料。
图7示出了根据本发明的一个实现方式的计算设备1000。计算设备1000容纳母板1002。母板1002可以包括多个部件,包括但不限于,处理器1004和至少一个通信芯片1006。处理器1004物理且电耦合到母板1002。在一些实现方式中,至少一个通信芯片1006也物理且电耦合到母板1002。
取决于其应用,计算设备1000可以包括其他部件,其会或不会物理且电耦合到母板1002。这些其他部件包括但不限于,易失性存储器(例如,DRAM)、非易失性存储器(例如ROM)、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、指南针、加速度计、陀螺仪、扬声器、相机和大容量储存设备(例如,硬盘驱动器、光盘(CD)、数字多用途盘(DVD)等等)。
通信芯片1006实现了无线通信,用于往来于计算设备1000传送数据。术语“无线”及其派生词可以用于描述可以通过非固态介质借助使用调制电磁辐射传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并非暗示相关设备不包含任何导线,尽管在一些实施例中它们可以不包含。通信芯片1006可以实施多个无线标准或协议中的任意一个,包括但不限于,Wi-Fi(IEEE802.11族)、WiMAX(IEEE802.16族)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物,以及被指定为3G、4G、5G及之后的任何其他无线协议。计算设备1000可以包括多个通信芯片1006。例如,第一通信芯片1006可以专用于近距离无线通信,例如Wi-Fi和蓝牙,第二通信芯片1006可以专用于远距离无线通信,例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备1000的处理器1004包括封装在处理器1004内的集成电路晶片。在本发明的一些实现方式中,处理器的集成电路晶片包括一个或多个器件,例如根据本说明的实现方式构成的晶体管。术语“处理器”可以指代任何设备或设备的部分,其处理来自寄存器和/或存储器的电子数据,将该电子数据转变为可以存储在寄存器和/或存储器中的其他电子数据。
通信芯片1006也包括封装在通信芯片1006内的集成电路晶片。根据本发明的另一个实现方式,通信芯片的集成电路晶片包括一个或多个器件,例如根据本发明的实现方式构成的晶体管。
在进一步的实现方式中,容纳在计算设备1000中的另一个部件可以包含集成电路晶片,其包括一个或多个器件,例如根据本发明的实现方式构成的晶体管。
在多个实现方式中,计算设备1000可以是膝上型电脑、上网本电脑、笔记本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描器、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数码摄像机。在进一步的实现方式中,计算设备1000可以是处理数据的任何其他电子设备。
在前面的说明中,阐述了许多特定细节,例如用于晶体管的布局和材料状况,以便提供对本发明实施例的透彻理解。对于本领域技术人员来说,可以实施本发明的实施例而无需这些特定细节是显而易见的。在其他实例中,没有详细说明公知的特征,例如用于晶体管的电气连接方案和集成电路设计布局,以避免不必要地使得本发明的实施例模糊不清。而且,应当理解,附图中所示的多个实施例是说明性表示,不一定按照比例绘制。
相关领域技术人员应当理解,本公开内容通篇中可以进行变型和变化作为所示和所述的多个部件的替代。在本说明书通篇中对“一个实施例”、“实施例”的提及表示结合该实施例说明的特定的特征、结构、材料或特性包括在本发明的至少一个实施例中,但不一定表示它们出现在每一个实施例中。而且,在实施例中所公开的特定的特征、结构、材料和特性可以以任何适合的方式组合到一个或多个实施例中。在其他实施例中,可以包括多个另外的层和/或结构,并且/或这可以省略所说明的特征。
Claims (25)
1.一种器件,包括:衬底,所述衬底具有表面,其中,所述表面包括具有第一晶格常数的第一外延材料,
沟道区,所述沟道区布置在所述衬底的表面上,所述衬底的表面包括多个第二外延材料的层和多个第三外延材料的层,其中,所述第二外延材料的晶格常数大于所述第一外延材料的晶格常数,其中,所述第三外延材料的晶格常数小于所述第一外延材料的晶格常数,并且其中,以交替方式来布置所述第二外延材料的层和所述第三外延材料的层,以及
栅极区,所述栅极区布置在所述沟道区的两个或三个侧上,其中,所述栅极区包括布置在栅极电极材料与所述沟道区之间的栅极电介质材料。
2.根据权利要求1所述的器件,其中,所述沟道区包括以交替方式来布置的至少三个第三外延材料的层和至少三个第二外延材料的层。
3.根据权利要求1所述的器件,其中,所述第一外延材料包括SiXGe1-X,所述第二外延材料包括SiYGe1-Y,并且所述第三外延材料包括SiZGe1-Z,其中,Y>X、Z<X、1>X≥0且1≥Y>0且1>Z≥0。
4.根据权利要求1所述的器件,其中,所述第一外延材料包括InP,所述第二外延材料包括InXGa1-XAs,其中1≥X>0.53,所述第三外延材料包括InYGa1-YAs,其中0.53>Y≥0,或者,所述第一外延材料包括GaSb,所述第二外延材料包括AlSb,并且所述第三外延材料包括InAs。
5.根据权利要求1所述的器件,其中,所述第一外延材料包括Ge,所述第二外延材料包括SiXGe1-X,其中1≥X>0,并且所述第三外延材料包括InYGa1-YAs,其中1≥Y>0,或者,所述第一外延材料包括GaAs,所述第二外延材料包括GaAsXP1-X,其中1>X≥0,并且所述第三外延材料包括InYGa1-YP,其中1≥Y>0.51。
6.根据权利要求1所述的器件,其中,所述沟道区包括第一端部和第二端部,并且源极区与所述第一端部电耦合,并且漏极区与所述第二端部电耦合。
7.一种器件,包括:
衬底,所述衬底具有表面,其中,所述表面包括具有第一晶格常数的第一外延材料,
沟道区,所述沟道区布置在所述衬底的表面上,其中,所述沟道区包括至少一条纳米线或纳米带,其中,所述沟道区具有端部,
布置在所述沟道区的端部上的至少一个夹层区,其中,所述夹层区包括多个第二外延材料的层和至少一个第三外延材料的层,其中,所述第二外延材料的晶格常数小于所述第一外延材料的晶格常数,其中,所述第三外延材料的晶格常数大于所述第一外延材料的晶格常数,其中,以交替方式来布置所述第二外延材料的层和所述第三外延材料的层,并且其中,所述至少一条纳米线或纳米带包括所述第三外延材料,以及
栅极区,所述栅极区布置在所述至少一条纳米线或纳米带的四个侧上,其中,所述栅极区包括布置在栅极电极材料与所述沟道区之间的栅极电介质材料。
8.根据权利要求7所述的器件,其中,所述第一外延材料包括SiXGe1-X,所述第二外延材料包括SiYGe1-Y,且所述第三外延材料包括SiZGe1-Z,其中,Y>X、Z<X、1>X≥0且1≥Y>0且1>Z≥0。
9.根据权利要求7所述的器件,其中,所述第一外延材料包括InP,所述第二外延材料包括InXGa1-XAs,其中1≥X>0.53,且所述第三外延材料包括InYGa1-YAs,其中0.53>Y≥0,或者,所述第一外延材料包括GaSb,所述第二外延材料包括AlSb,且所述第三外延材料包括InAs。
10.根据权利要求7所述的器件,其中,所述第一外延材料包括Ge,所述第二外延材料包括SiXGe1-X,其中1≥X>0,且所述第三外延材料包括 InYGa1-YAs,其中1≥Y>0,或者,所述第一外延材料包括GaAs,所述第二外延材料包括GaAsXP1-X,其中1>X≥0,且所述第三外延材料包括InYGa1-YP,其中1≥Y>0.51。
11.根据权利要求7所述的器件,其中,所述器件包括第一夹层区和第二夹层区,其中,所述沟道区包括第一端部和第二端部,并且其中,所述第一夹层区布置在所述沟道区的第一端部上,且所述第二夹层区布置在所述沟道区的第二端部上。
12.根据权利要求11所述的器件,其中,源极区与所述第一夹层区电耦合,并且漏极区与所述第二夹层区电耦合。
13.根据权利要求7所述的器件,其中,所述器件包括多条纳米线或纳米带。
14.一种器件,包括:
衬底,所述衬底具有表面,其中,所述表面包括具有第一晶格常数的第一外延材料,
沟道区,所述沟道区布置在所述衬底的表面上,其中,所述沟道区包括至少一条纳米线或纳米带,其中,所述沟道区具有端部,
布置在所述沟道区的端部上的至少一个夹层区,其中,所述夹层区包括多个第二外延材料的层和至少一个第三外延材料的层,其中,所述第二外延材料的晶格常数大于所述第一外延材料的晶格常数,其中,所述第三外延材料的晶格常数小于所述第一外延材料的晶格常数,其中,以交替方式来布置所述第二外延材料的层和所述第三外延材料的层,并且其中,所述至少一条纳米线或纳米带包括所述第三外延材料,以及
栅极区,所述栅极区布置在所述至少一条纳米线或纳米带中的每一条纳米线或纳米带上,其中,所述栅极区包括布置在栅极电极材料与所述沟道区之间的栅极电介质材料。
15.根据权利要求14所述的器件,其中,所述第一外延材料包括SiXGe1-X,所述第二外延材料包括SiYGe1-Y,且所述第三外延材料包括SiZGe1-Z,其中,Y<X、Z>X、1>X≥0且1>Y>0且1>Z≥0。
16.根据权利要求14所述的器件,其中,所述第一外延材料包括Ge,所述第二外延材料包括InYGa1-YAs,其中1≥Y>0,且所述第三外延材料包括SiXGe1-X,其中1≥X>0,或者所述第一外延材料包括GaAs,所述第二外延材料包括InYGa1-YP,其中1≥Y>0.51,且所述第三外延材料包括GaAsXP1-X,其中对于X,1>X≥0。
17.根据权利要求14所述的器件,其中,所述器件包括第一夹层区和第二夹层区,其中,所述沟道区包括第一端部和第二端部,并且其中,所述第一夹层区布置在所述沟道区的所述第一端部上,且所述第二夹层区布置在所述沟道区的所述第二端部上。
18.根据权利要求17所述的器件,其中,源极区与所述第一夹层区电耦合,并且漏极区与所述第二夹层区电耦合。
19.根据权利要求14所述的器件,其中,所述器件包括多条纳米线或纳米带。
20.一种计算设备,包括:
母板;
通信芯片,所述通信芯片被安装在所述母板上;以及
处理器,所述处理器安装在所述母板上,所述处理器包括晶体管,所述晶体管包括沟道区,且所述晶体管包括:
衬底,所述衬底具有表面,其中,所述表面包括具有第一晶格常数的第一外延材料,
沟道区,所述沟道区布置在所述衬底的表面上,所述衬底的表面包括多个第二外延材料的层和多个第三外延材料的层,其中,所述第二外延材 料的晶格常数大于所述第一外延材料的晶格常数,其中,所述第三外延材料的晶格常数小于所述第一外延材料的晶格常数,并且其中,以交替方式来布置所述第二外延材料的 层和所述第三外延材料的 层,以及
栅极区,所述栅极区布置在所述沟道区的两个或三个侧上,其中,所述栅极区包括布置在栅极电极材料与所述沟道区之间的栅极电介质材料。
21.根据权利要求20所述的计算设备,其中,所述沟道区包括至少三个第三外延材料的层。
22.一种计算设备,包括:
母板;
通信芯片,所述通信芯片安装在所述母板上;以及
处理器,所述处理器安装在所述母板上,所述处理器包括晶体管,所述晶体管包括沟道区,且所述晶体管包括:
衬底,所述衬底具有表面,其中,所述表面包括具有第一晶格常数的第一外延材料,
沟道区,所述沟道区布置在所述衬底的表面上,其中,所述沟道区包括至少一条纳米线或纳米带,所述至少一条纳米线或纳米带包括第二外延材料,并且其中,所述沟道区具有端部,
布置在所述沟道区的端部上的至少一个夹层区,其中,所述夹层区包括多个第二外延材料的层和多个第三外延材料的层,其中,所述第二外延材料的晶格常数大于所述第一外延材料的晶格常数,其中,所述第三外延材料的晶格常数小于所述第一外延材料的晶格常数,并且其中,以交替方式来布置所述第二外延材料的 层和所述第三外延材料的 层,以及
栅极区,所述栅极区布置在所述至少一条纳米线或纳米带中的每一条纳米线或纳米带上,其中,所述栅极区包括布置在栅极电极材料与所述沟道区之间的栅极电介质材料。
23.根据权利要求22所述的计算设备,其中,所述沟道区包括多条纳米带或纳米线。
24.一种计算设备,包括:
母板;
通信芯片,所述通信芯片安装在所述母板上;以及
处理器,所述处理器安装在所述母板上,所述处理器包括晶体管,所述晶体管包括沟道区,且所述晶体管包括:
衬底,所述衬底具有表面,其中,所述表面包括具有第一晶格常数的第一外延材料,
沟道区,所述沟道区布置在所述衬底的表面上,其中,所述沟道区包括至少一条纳米线或纳米带,所述至少一条纳米线或纳米带包括第二外延材料,并且其中,所述沟道区具有端部,
布置在所述沟道区的端部上的至少一个夹层区,其中,所述夹层区包括多个第二外延材料的层和多个第三外延材料的层,其中,所述第二外延材料的晶格常数小于所述第一外延材料的晶格常数,其中,所述第三外延材料的晶格常数小于所述第一外延材料的晶格常数,并且其中,以交替方式来布置所述第二外延材料的 层和所述第三外延材料的 层,以及
栅极区,所述栅极区布置在所述至少一条纳米线或纳米带中的每一条纳米线或纳米带上,其中,所述栅极区包括布置在栅极电极材料与所述沟道区之间的栅极电介质材料。
25.根据权利要求24所述的计算设备,其中,所述沟道区包括多条纳米带或纳米线。
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