TW201342602A - 電晶體中的應變補償 - Google Patents

電晶體中的應變補償 Download PDF

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TW201342602A
TW201342602A TW101145439A TW101145439A TW201342602A TW 201342602 A TW201342602 A TW 201342602A TW 101145439 A TW101145439 A TW 101145439A TW 101145439 A TW101145439 A TW 101145439A TW 201342602 A TW201342602 A TW 201342602A
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Taiwan
Prior art keywords
epitaxial material
channel region
epitaxial
region
lattice constant
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TW101145439A
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English (en)
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TWI493714B (zh
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Van H Le
Benjamin Chu-Kung
Harold Hal W Kennel
Willy Rachmady
Ravi Pillarisetty
Jack T Kavalieros
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Intel Corp
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

提供具有通道區的電晶體結構,通道區包括交錯的壓縮及伸展應變磊晶材料層。交錯的磊晶層形成單一及多閘極電晶體結構中的通道區。在替代實施例中,二交錯層中之一被選擇性地蝕刻而由餘留材料形成奈米條紋或奈米佈線。造成的應變奈米條紋或奈米佈線形成電晶體結構的通道區。也提供包括電晶體的計算裝置,所述電晶體包括通道區,所述通道區包括交錯的壓縮及伸展應變磊晶材料層,以及,提供包括電晶體的計算裝置,所述電晶體包括包含應變奈米條紋或奈米佈線的通道區。

Description

電晶體中的應變補償
本發明的實施例大致上關於積體電路裝置,特別關於電晶體、多閘極電晶體、PMOS和NMOS電晶體、以及奈米條紋和奈米佈線電晶體。
朝向更小更高度的積體電路(IC)及其它半導體裝置的推動將對用以構成裝置的技術及材料提出更多要求。一般而言,積體電路晶片也稱為微晶片、矽晶片、或晶片。IC晶片可見於各式各樣的一般裝置中,例如電腦、汽車、電視、遊戲系統、光碟播放器、及行動電話。複數IC晶片典型上建立於矽晶圓上(具有例如300 mm的直徑之薄矽碟),以及,在處理之後,晶圓被切成晶粒以產生各別晶片。具有約90 nm的特徵尺寸之1 cm2的IC晶片包括數以億計的元件。目前的技術正將特徵尺寸推向更小於32 nm。舉例而言,IC晶片的元件包含例如CMOS(互補金屬氧化物半導體)裝置等電晶體、電容結構、電阻結構、及在組件與外部裝置之間提供電子連接的金屬線。舉例而言,其它的半導體裝置包含例如各式的二極體、雷射、光偵測器、及磁場感測器。
隨著電晶體的元件的間距愈來愈小,源極和汲極區體 積縮減以及經由源極和汲極區以提供單軸電晶體通道應變變得愈來愈難。在電晶體的通道區中的應變增進電晶體性能。因此,將應變併入通道區而未依靠源極和汲極區來供應應變的裝置是有用的。本發明的實施例提供設有具有從基底施加的應變之通道結構的電晶體。也設置包括層間壓縮及伸展層的通道結構以及製造這些通道結構的方法。本發明的其它實施例提供在通道區中具有複數應變奈米條紋或奈米佈線的電晶體。有利地,本發明的實施例提供具有應變通道結構的電晶體,應變通道結構具有顯著的高度並在通道結構中維持應變。
圖1A-B顯示具有應變通道區之三閘極電晶體結構。 圖1B代表沿著圖1A的結構之1-1視圖(垂直切入頁面)。所造成的剖面視圖旋轉45°。在圖1A-B中,基底105容納包括相對立的應變磊晶層間層110和115之通道區。相反地應變的磊晶層間層110和115相對於基底105表面上的材料而壓縮地或伸展地應變。舉例而言,層110伸展地應變,以及,層115壓縮地應變,或者,相反地,層110壓縮地應變,以及,層115伸展地應變。經由相對於基底105表面(「基底」)上的材料層或是基底105材料的晶格而晶格失配,以產生相反地應變的磊晶層間層110和115。舉例而言,任何包括來自週期表的III、IV、及/或V族的元素、或是其組合之材料可為被選取用於基底105的材料。然後,在基底105上,以磊晶沉積製程,生長具有更大(更小)的晶格常數之第一層110。第一層 110生長至其關鍵層厚度之下,以確保在第一層110中保存完全壓縮(伸展)應力。接著,在第一層100的頂部上,以磊晶沉積製程,生長相對於基底105具有較小的(較大的)晶格常數之第二層115。第二層115生長至其關鍵層厚度之下,以確保完全伸展(壓縮)應力。在本發明的實施例中,具有交替的壓縮及伸展應變的樣式之增加的連續層110和115生長至相當高的高度,具有最小至沒有應變釋放。一般而言,層間層包括純元素及/或例如Si和Ge等元素的混合、以及III-V半導體材料(包括週期表的行III和V中的元素之材料)。在本發明的實施例中,通道結構包括量子井,其中,薄裝置層相鄰於或夾於比通道材料具有更大的能帶隙的層之間。在本發明的實施例中,基底105包括SiXGe1-X,層110(或層115)包括SiYGe1-Y,其中,Y>X,以及,層115(或層110)包括SiZGe1-Z,其中,Z<X、1>X≧0,以及1≧Y>0、且1>Z≧0。在其它實施例中,基底105包括InP,層110(或層115)包括InXGa1-XAs,其中,1≧X>0.53,以及,層115(或層110)包括InYGa1-YAs,其中,0.53>Y≧0。在另外的實施例中,基底105包括GaSb,層110(或層115)包括AlSb,以及,層115(或層110)包括InAs。在又另外的實施例中,基底105包括Ge,層110(或層115)包括SiXGe1-X,以及,層115(或層110)包括InYGa1-YAs,其中,1≧X>0以及1≧Y>0。在又其它實施例中,基底105是GaAs,層110(或層115)是GaAsXP1-X,其中,X 是在1與0之間的數,以及,層115(或層110)是InYGa1-YP,其中,1≧Y>0.51。已發現藉由使用包括交錯的壓縮及伸展應變磊晶材料層之磊晶層間層結構,能夠建立在層中保留應變的通道結構,並比在電晶體的通道區中產生應變的習知方法具有更大的高度。在本發明的實施例中,電晶體的通道區具有高度h1,範圍在10 nm與100 nm之間或是在25 nm與85 nm之間,但是,其它高度也是可能的。雖然在圖1中顯示十二層相反應變的磊晶層間層110和115,但是,也能夠具有其它數目的層115和110,舉例而言,例如包含及在3與25層之間或是在5與25層之間,但是,其它數目也是可能的。
在圖1A中,源極及汲極區120和125緊靠通道區110和115。在本發明的實施例中,相對於基底的通道應變維持在通道區中,且不要求使用在通道中產生應變的源極/汲極材料。電晶體結構增加地包括閘極介電質135和閘極電極140。如同圖1B中所見般,閘極介電質135配置在通道區的三側上:二側是橫跨第三側。閘極電極140配置在閘極介電質135上。選擇性地,絕緣間隔器145及146(圖1A)緊鄰閘極介電質135和閘極電極140。電晶體結構典型地遮蓋於絕緣介電層中,其被部份地顯示為絕緣區150和151(圖1A)。
圖2A-B顯示具有應變通道區的雙閘極電晶體結構。圖2B代表沿著圖2A的結構的2-2(垂直切入頁面中)之視圖。所造成的剖面視圖旋轉45°。在圖2A-B中,基底 205容納包括相反地應變的磊晶層間層210和215之通道區。相對立的應變磊晶層間層210和215相對於基底205表面上的材料為壓縮地或伸展地應變。舉例而言,層210伸展地應變,以及,層215壓縮地應變,或者,相反地,層210壓縮地應變,以及,層215伸展地應變。經由相對於基底205表面(「基底」)上的材料層或是基底205材料的晶格而晶格失配,以產生相反地應變的磊晶層間層210和215。舉例而言,包括來自週期表的III、IV、及/或V族的元素、或是其組合之任何材料可為被選取用於基底205的材料。然後,在基底205上,以磊晶沉積製程,生長具有更大(更小)的晶格常數之第一層210。第一層210生長至其關鍵層厚度之下,以確保在第一層210中保存完全壓縮(伸展)應力。接著,在第一層200的頂部上,以磊晶沉積製程,生長相對於基底205具有較小的(較大的)晶格常數之第二層215。第二層215生長至其關鍵層厚度之下,以確保完全伸展(壓縮)應力。在本發明的實施例中,具有交替的壓縮及伸展應變的樣式之增加的連續層210和215生長至相當高的高度,具有最小至沒有應變釋放。一般而言,層間層包括純元素及/或例如Si和Ge等元素的混合、以及III-V半導體材料(包括週期表的行III和V中的元素之材料)。在本發明的實施例中,通道結構包括量子井,其中,薄裝置層相鄰於或夾於比通道材料具有更大的能帶隙的層之間。在本發明的實施例中,基底205包括SiXGe1-X,層210(或層215)包括 SiYGe1-Y,其中,Y>X,以及,層215(或層210)包括SiZGe1-Z,其中,Z<X、1>X≧0,1≧Y>0、以及1>Z≧0。在其它實施例中,基底205包括InP,層210(或層215)包括InXGa1-XAs,其中,1≧X>0.53,以及,層215(或層210)包括InYGa1-YAs,其中,0.53>Y≧0。在另外的實施例中,基底205包括GaSb,層210(或層215)包括AlSb,以及,層215(或層210)包括InAs。在又另外的實施例中,基底205包括Ge,層210(或層215)包括SiXGe1-X,以及,層215(或層210)包括InYGa1-YAs,其中,1≧X>0以及1≧Y>0。在又其它實施例中,基底205是GaAs,層210(或層215)是GaAsXP1-X,其中,1>X≧0是在1與0之間的數,以及,層215(或層210)是InYGa1-YP,其中,1≧Y>0.51。已發現藉由使用包括交錯的壓縮及伸展應變磊晶材料層之磊晶層間層結構,能夠建立在層中保留應變的通道結構,並比在電晶體的通道區中產生應變的習知方法具有更大的高度。在本發明的實施例中,電晶體的通道區具有高度h1,範圍在10 nm與100 nm之間或是在25 nm與85 nm之間,但是,其它高度是可能的。雖然在圖2中顯示十二層相反應變的磊晶層間層210和215,但是,也能夠具有其它數目的層215和210,舉例而言,例如包含及在3與25層之間或是在5與25層之間。
在圖2A中,源極和汲極區220和225緊靠通道區210和215的端部。在本發明的實施例中,相對於基底的 通道應變維持在通道區中,且不要求使用源極/汲極應力器。另外的絕緣區252配置在通道區210與215的側邊上。在圖2B中,電晶體結構增加地包括閘極介電質235和閘極電極240。閘極介電質235配置在通道區的二相對立側上。閘極電極240配置在閘極介電質235上。選擇性地,絕緣間隔器245及246(圖2A)緊鄰閘極介電質235和閘極電極240。電晶體結構典型地遮蓋於絕緣介電層中,其被部份地顯示為絕緣區250和251(圖2A)。
圖3A-B顯示具有應變奈米條紋或奈米佈線通道區的電晶體結構。一般而言,奈米佈線被視為具有幾乎相等的寬度及高度,以及,奈米條紋被視為具有的寬度大於高度(長度維度是沿著佈線或條紋的長度之維度)。圖3A-B的結構類似於圖1-2(A-B)的結構,但是,在實施例中,伸展層被蝕刻掉以產生PMOS奈米佈線或是奈米條紋通道區,或者,相反地,壓縮層被蝕刻掉以產生NMOS奈米佈線或是奈米條紋通道區。圖3B代表代表沿著圖3A的結構的3-3(垂直切入頁面中)之視圖。所造成的剖面視圖旋轉45°。在圖3A-B中,基底305容納包括奈米條紋或奈米佈線310之通道區。奈米條紋或奈米佈線310相對於基底應變。在本發明的實施例中,奈米佈線或奈米條紋310在PMOS通道中壓縮地應變以及在NMOS通道中伸展地應變。選擇性地,磊晶層間區315和316在源極和汲極320和325與奈米條紋或奈米佈線310之間位於電晶體結構中。選擇性的磊晶層間區315和316包括呈現交替的壓 縮及伸展(或者,反之亦然)應變層之層。一般而言,層間層包括純元素及/或例如Si和Ge等元素的混合、以及III-V半導體材料(包括週期表的行III和V中的元素之材料)。在本發明的實施例中,具有壓縮應變的奈米佈線或奈米條紋的電晶體具有包括SiXGe1-X之基底305表面材料、包括SiYGe1-Y的第二磊晶材料、以及包括SiZGe1-Z的第三磊晶材料,其中,Y>X,Z<X、1>X≧0、及1≧Y>0、以及1>Z≧0。在具有壓縮應變的奈米佈線或奈米條紋的替代實施例中,基底305包括InP,第二磊晶材料包括InXGa1-XAs,其中,1≧X>0.53,以及,第三磊晶材料包括InYGa1-YAs,其中,0.53>Y≧0,或者,基底305包括GaSb,第二磊晶材料包括AlSb,以及,第三磊晶材料包括InAs。在具有壓縮應變的奈米佈線或奈米條紋的另外實施例中,基底305包括Ge,第二磊晶材料包括SiXGe1-X,其中,1≧X>0,以及,第三磊晶材料包括InYGa1-YAs,其中,1≧Y>0。或者,基底305包括GaAs,第二磊晶材料包括GaAsXP1-X,其中,1>X≧0,以及,第三磊晶材料包括InYGa1-YP,其中,1≧Y>0.51。在具有伸展應變的奈米佈線或奈米條紋的實施例中,基底305包括SixGe1-x,第二磊晶材料包括SiYGe1-Y、以及,第三磊晶材料包括SiZGe1-Z的,其中,Y<X,Z>X、1>X≧0、及1>Y>0、以及1>Z≧0。在具有伸展應變的奈米佈線或奈米條紋的另外實施例中,基底305包括Ge,第二磊晶材料包括InYGa1-YAs,其中,1≧Y>0,以及,第三磊晶材料包 括SiXGe1-X,其中,1≧X>0,或者,基底305包括GaAs,第二磊晶材料包括InYGa1-YP,其中,1≧Y>0.51,以及,第三磊晶材料包括GaAsXP1-X,其中,1>X≧0。在後續的處理事件中,第二磊晶材料被蝕刻掉(或是部份地,留下磊晶層間區315和316,或是完全地,未留下磊晶層間區315和316)以產生包括第三磊晶材料的奈米佈線或奈米條紋310。在本發明的實施例中,奈米佈線310包括例如Ge、SiXGe1-X、或者包括來自週期表的III、IV、及V族的一或更多元素之材料。雖然圖3A-B中顯示四個奈米條紋或奈米佈線310,但是,其它數目的奈米條紋或奈米佈線310是可能的,例如,在電晶體中,包含及在1與10之間,在2與10之間,以及在3與10個奈米條紋或奈米佈線之間,但是,其它數目也是可能的。
在圖3A中,源極和汲極區320和325緊靠選擇性的磊晶層間區315和316或是緊靠奈米條紋或奈米佈線310的端部(未顯示)。在本發明的實施例中,相對於基底的通道應變維持在通道區中,且不要求使用源極/汲極應力器。在實施例中,磊晶層間區315和316未存在且奈米佈線或奈米條紋310接觸源極和汲極區320和325。絕緣層330配置在奈米條紋或奈米佈線310與基底305之間,以及,能夠作為閘極與基底305之間的底部閘極隔離。在圖3A-B中,電晶體結構增加地包括閘極介電質335和閘極電極340。閘極介電質335配置在奈米條紋或奈米佈線310上。閘極電極340配置在閘極介電質335上。選擇性 地,絕緣間隔器345及346緊鄰閘極介電質335和閘極電極340。電晶體結構典型地遮蓋於絕緣介電層中,其被部份地顯示為絕緣區350和351。
圖4顯示具有應變通道區的單閘極電晶體結構。其它結構也能夠用於單閘極電晶體,例如彼此具有不同定向的特點之一結構,以及,具有不同形狀及/或尺寸的特點之結構。舉例而言,具有未相對於通道區凹陷的源極和汲極區之單閘極電晶體結構也是可能的。在圖4中,基底層405以選擇性的隔離溝槽407為邊界以及容納包括相反應變的磊晶層間層410和415之通道區。相反地應變的磊晶層間層410和415相對於基底而壓縮地或伸展地應變。舉例而言,層410伸展地應變,以及,層415壓縮地應變,或者,相反地,層410壓縮地應變,以及,層415伸展地應變。經由相對於基底晶格而晶格失配,以產生相反地應變的磊晶層間層410和415。舉例而言,任何包括來自週期表的III、IV、及/或V族的元素、或是其組合之材料可為被選取用於基底405的材料。一般而言,磊晶層間層410和415包括純元素及/或例如Si和Ge等元素的混合、以及III-V半導體材料(包括週期表的行III和V中的元素之材料)。基底405以及磊晶層間層410和415包括參考圖1-2(A-B)而說明的用於基底及磊晶層間層的材料。選擇性的隔離溝槽407包括絕緣材料以及電隔離電晶體結構與構成半導體晶片的其它裝置。源極和汲極區420和425顯示為相對於通道區凹陷。閘極電極區430是在通 道區的一側上且以閘極介電區435與通道區相分離。在裝置製造期間形成選擇性的絕緣間隔器440以便於製造,以及,絕緣間隔器440用以電隔離電晶體閘極區。雖然在圖4中顯示六層相反應變的磊晶層間層410和415,但是,也能夠具有其它數目的層415和410,舉例而言,例如包含及在3與25層之間或是包含及在5與25層之間,但是,其它數目也是可能的。
圖5是說明用於製造三閘極或雙閘極電晶體結構的應變磊晶層通道區之方法。在圖5中,設置基底,基底在其表面上設有具有第一晶格常數的第一磊晶材料。第一磊晶材料為磊晶材料層。第二磊晶材料沉積於基底表面上,第二磊晶材料具有大於(壓縮膜)或小於(伸展膜)第一磊晶材料的晶格常數之第二晶格常數。然後,第三磊晶材料沉積於第二磊晶材料上,第三磊晶材料具有比基底的晶格常數更大的晶格常數(壓縮)或更小的晶格常數(伸展)。假使沉積第二層作為壓縮層,則第三層將沉積作為伸展層,以及,第二和第三膜形成應變補償堆疊。相反地,假使沉積第二層作為伸展層,則第三層沉積作為壓縮層。舉例而言,藉由超高真空化學汽相沉積(UHV-CVD)、快速熱化學汽相沉積(RTCVD)、或是分子束磊晶(MBE),沉積磊晶材料。交錯的磊晶伸展及壓縮應變材料層(相對於基底,分別具有較小及較大的晶格常數之材料)沉積至基底上以產生呈現雙軸應變的層堆疊。相信在電晶體的通道區製造期間,由於形成為鬆弛一層的錯位 將在另一層中增加應變,所以,伸展及壓縮層間層(在相反方向上應變且彼此相鄰的層)更穩定地抗鬆弛。由於平衡的堆疊系統的鬆弛需求是相反的,所以,產生用於通道區的較大總關鍵厚度。一般而言,未形成用於大於1.3%的晶格不匹配之50 nm以外的鬆弛或缺陷,無法生長未使用應變補償的單一膜堆疊。在本發明的實施例中,層疊堆具有3至25層或是5至25層以及/或具有10 nm與100 nm之間的高度或是25 nm與85 nm之間的高度。用於磊晶層的舉例說明的材料可為參考圖1A-B及2A-B所述的材料。包括相反應變層間層的結構圖型化成電晶體通道尺寸(舉例而言,成為用於鰭場效電晶體結構的鰭部),將基底雙軸應變轉換成基底單軸應變。然後,在層電晶體通道區的一、二、或三側上,沉積閘極介電材料(舉例而言,如同參考圖1A-B、2A-B、及4所示般)。閘極電極材料接著沉積於閘極介電材料上。
圖6說明用於製造包括應變奈米條紋或奈米佈線之電晶體的通道區之方法。在圖6中,設置基底,基底在其表面上設有具有第一晶格常數的第一磊晶材料。第一磊晶材料為磊晶材料層。第二磊晶材料沉積於基底表面上,第二磊晶材料具有大於(壓縮膜)或小於(伸展膜)第一磊晶材料的晶格常數之第二晶格常數。然後,第三磊晶材料沉積於第二磊晶材料上,第三磊晶材料具有比基底的晶格常數更大的晶格常數(壓縮)或更小的晶格常數(伸展)。假使沉積第二層作為壓縮層,則第三層將沉積作為伸展 層,以及,第二和第三膜形成應變補償堆疊。相反地,假使沉積第二層作為伸展層,則第三層沉積作為壓縮層。舉例而言,藉由UHV-CVD、RTCVD、或MBE,沉積磊晶材料。交錯的磊晶伸展及壓縮應變材料層(相對於基底,分別具有較小及較大的晶格常數之材料)沉積至基底上,產生呈現雙軸應變的層堆疊。相信在電晶體的通道區製造期間,由於形成為鬆弛一層的錯位將在另一層中增加應變,所以,伸展及壓縮層間層(在相反方向上應變且彼此相鄰的層)更穩定地抗鬆弛。由於製造期間平衡的堆疊系統的鬆弛需求是相反的,所以,產生用於應變通道區的較大總關鍵厚度。一般而言,未形成用於大於1.3%的晶格不匹配之50 nm以外的鬆弛或缺陷,無法生長未使用應變補償的單一膜堆疊。用於磊晶層的舉例說明的材料可為參考圖3A-B所述的材料。
包括相反應變層的結構圖型化成電晶體奈米佈線或是奈米條紋通道尺寸(舉例而言,成為鰭部),將基底雙軸應變轉換成基底單軸應變。圍繞圖型化的通道區以及形成在通道區的端部之源極/汲極區,形成假閘極。選擇性地,假閘極區由二側上的間隔為邊界。移除假閘極材料以及執行選擇性蝕刻,以移除壓縮應變磊晶層或是伸張應變磊晶層,產生餘留材料的奈米佈線或奈米條紋。奈米佈線或奈米條紋懸垂於源極和汲極區之間。在本發明的實施例中,在選擇性蝕刻之後,伸展及壓縮層間層的區域維持在奈米佈線或奈米條紋之端部。這些層間區在奈米佈線或奈 米條紋的端部與源極/汲極區之間。在其它實施例中,在選擇性蝕刻之後,未餘留伸展及壓縮的層間層的區域。閘極介電材料沉積於暴露之奈米條紋或奈米佈線的四側(環繞)。舉例而言,根據圖3A-B,閘極電極材料接著沉積至閘極介電質遮蓋奈米條紋或奈米佈線的四側上的閘極介電材料上,產生通道區結構。
舉例而言,閘極介電材料包含絕緣材料,例如二氧化矽(SiO2)、氧氮化矽、氮化矽、及/或高k介電材料。一般而言,高k介電質是介電常數比SiO2的介電常數大的介電材料。舉例說明的高k介電材料包含二氧化鉿(HfO2)、鉿矽氧化物、氧化鑭、鑭鋁氧化物、二氧化鋯(ZrO2)、鋯矽氧化物、二氧化鈦(TiO2)、五氧化鉭(Ta2O5)、鋇鍶鈦氧化物、鋇鈦氧化物、鍶鈦氧化物、氧化釕釔、氧化鋁、鉛鈧鉭氧化物、鉛鋅鈮酸鹽、及其它半導體領域中熟知的材料。舉例而言,閘極電極材料包含例如Ti、W、Ta、Al、及其合金、以及與例如鉺、鏑等稀土金屬或是例如Pt等貴重金屬的合金、以及例如TaN、和TiN等氮化物等等材料。舉例而言,用於源極及/或汲極的材料包含用於NMOS的矽、摻雜碳的矽、及摻雜磷的矽、以及用於PMOS的摻雜硼的SiXGe1-X、摻雜硼的Ge、摻雜硼的GeXSn1-X、以及摻雜磷的III-V化合物。
用於介電層、特徵、及/或層間介電質(ILD)的典型介電材料包含二氧化矽及低k介電材料。可以使用的其它介電材料包含摻雜碳的氧化物(CDO)、氮化矽、氧氮化 矽、碳化矽、例如八氟環丁烷或聚四氟乙烯等有機聚合物、氟矽玻璃(FSG)、及/或例如倍半矽氧烷、矽氧烷、或有機矽酸鹽玻璃等有機矽酸鹽。介電層包含毛細孔以進一步降低介電常數。
此處所示的裝置包括其它結構,例如絕緣層包封裝置、增加的基底層、連接源極和汲極至IC裝置的其它組件之通孔及金屬溝槽、其它增加層及/或裝置。為了簡明起見而顯示為一層的組件可以視構成裝置時使用的製程及所需的裝置特性而包括具有相同或不同材料的複數層。
本發明的實施設置於例如半導體晶圓等基底上。根據本發明的實施例之電晶體結構形成於基底表面上,舉例而言,基底表面包含H終端矽、二氧化矽、矽、矽鍺、III-V族(或其它週期表行數設計中的13-14族)化合物半導體、主族氧化物、金屬、及/或二進位或混合的金屬氧化物。層及包括裝置的層也說明成基底或是基底的一部份,本發明的實施例製於所述基底或是基底的一部份上。半導體裝置建於基部基底上,基部基底典型上是半導體晶圓,半導體晶圓被切割分開,以產生各別的IC晶片。晶片建於基部基底上,基部基底典型上是矽晶圓,但是,本發明的實施例不取決於所使用的基底的型式。基底也包括鍺、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵、銻化鎵、及/或其它單獨的或是與矽或二氧化矽或其它絕緣材料相結合之分類為III-V族材料。
圖7顯示根據本發明的實施之計算裝置1000。計算裝 置1000容納主機板1002。主機板1002包含多個組件,多個組件包括但不限於處理器1004及至少一通訊晶片1006。處理器1004實體地及電耦合至主機板1002。在某些實施中,至少一通訊晶片1006也實體地及電耦合至主機板1002。
取決於其應用,計算裝置1000包含可以或不可以實體地及電耦合至主機板1002的其它組件。這些其它組件包含但不限於依電性記憶體(例如,DRAM)、非依電性記憶體(例如,ROM)、圖形處理器、數位訊號處理器、密碼處理器、晶片組、天線、顯示器、觸控幕顯示器、觸控幕控制器、電池、音頻編解碼、視頻編解碼、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、陀螺儀、揚音器、相機、及大量儲存裝置(例如硬碟機、光碟(CD)、數位多樣式光碟(DVD)、等等)。
通訊晶片1006能夠無線通訊以用於對計算裝置1000傳輸資料。「無線」一詞及其衍生詞用以說明經由使用通過非固體介質之調變的電磁輻射來傳輸資料的電路、裝置、系統、方法、技術、通訊通道、等等。此詞並非意指相關連裝置未含有任何接線,但是,在某些實施例中,它們可能未含任何接線。通訊晶片1006可以實施任何無線標準或是通信協定,包含但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其 衍生、以及以3G、4G、5G、及更新的世代來標示的任何其它無線通信協定。計算裝置1000包含複數通訊晶片1006。舉例而言,第一通訊晶片1006可以專用於較短範圍的無線通訊,例如Wi-Fi及藍芽,而第二通訊晶片1006可以專用於較長範圍的無線通訊,例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、等等。
計算裝置1000的處理器1004包含封裝在處理器1004之內的積體電路晶粒。在本發明的某些實施中,處理器的積體電路晶粒包含一或更多裝置,例如根據本發明的實施形成之電晶體。「處理器」一詞意指處理來自暫存器及/或記憶體的電子資料以將電子資料轉換成儲存在暫存器及/或記憶體中的其它電子資料之任何裝置或裝置的一部份。
通訊晶片1006也包含封裝於通訊晶片1006之內的積體電路晶粒。根據本發明的另一實施,通訊晶片的積體電路晶粒包含一或更多裝置,例如根據本發明的實施形成之電晶體。
在其它實施中,容納於計算裝置1000之內的另一組件含有積體電路晶粒,積體電路晶粒包含一或更多裝置,例如根據本發明的實施形成之電晶體。
在各式各樣的實施中,計算裝置1000可以是膝上型電腦、小筆電、筆記型電腦、智慧型手機、平板電腦、個人數位助理(PDA)、及超薄行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂 控制單元、數位相機、可攜式音樂播放器、或是數位攝影機。在又其它實施中,計算裝置1000可為包含處理資料的任何其它電子裝置。
在先前的說明中,揭示複數特定細節,例如用於電晶體及材料體系的佈局,以提供完整瞭解本發明的實施例。習於此技藝者將清楚,沒有這些特定細節,仍然可以實施本發明的實施例。在其它情形中,未詳細地說明例如用於電晶體及積體電路設計的電連接設計等熟知的特點,以免模糊本發明的實施例。此外,要瞭解,圖式中所示的各種實施例是說明性的表示而不一定依比例繪製。
習於相關技術者將瞭解,在揭示中的各處中,修改及變化是可能的,可作為所示及所述的各種組件的替代。在本說明書各處中述及「一實施例」或是「實施例」意指配合實施例所述的特定特點、結構、材料、或特徵包含在本發明的至少一實施例中,但不一定代表它們出現在每一實施例中。此外,在實施例中揭示的特定特點、結構、材料、及特徵可以在一或更多實施例中以任何適當方式相結合。在其它實施例中,可以包含各式各樣的其它層及/或結構以及/或省略所述的特點。
105‧‧‧基底
110‧‧‧磊晶層間層
115‧‧‧磊晶層間層
120‧‧‧源極區
125‧‧‧汲極區
135‧‧‧閘極介電質
140‧‧‧閘極電極
145‧‧‧絕緣間隔器
146‧‧‧絕緣間隔器
150‧‧‧絕緣區
151‧‧‧絕緣區
205‧‧‧基底
210‧‧‧磊晶層間層
215‧‧‧磊晶層間層
220‧‧‧源極區
225‧‧‧汲極區
235‧‧‧閘極介電質
240‧‧‧閘極電極
245‧‧‧絕緣間隔器
246‧‧‧絕緣間隔器
250‧‧‧絕緣區
251‧‧‧絕緣區
252‧‧‧絕緣區
305‧‧‧基底
310‧‧‧奈米條紋或奈米佈線
315‧‧‧磊晶層間區
316‧‧‧磊晶層間區
320‧‧‧源極區
325‧‧‧汲極區
330‧‧‧閘極介電質
335‧‧‧閘極介電質
340‧‧‧閘極電極
345‧‧‧絕緣間隔器
346‧‧‧絕緣間隔器
350‧‧‧絕緣區
351‧‧‧絕緣區
405‧‧‧基底
407‧‧‧隔離溝槽
410‧‧‧磊晶層間層
415‧‧‧磊晶層間層
420‧‧‧源極區
425‧‧‧汲極區
430‧‧‧閘極電極區
435‧‧‧閘極介電質區
440‧‧‧絕緣間隔器
1000‧‧‧計算裝置
1002‧‧‧主機板
1004‧‧‧處理器
1006‧‧‧通訊晶片
圖1A-B顯示三閘極電晶體結構的剖面視圖。
圖2A-B顯示雙閘極電晶體結構的剖面視圖。
圖3A-B顯示在通道區中包括奈米佈線或奈米條紋的 電晶體結構的剖面視圖。
圖4顯示單閘極電晶體結構的剖面視圖。
圖5是流程圖,說明用於製造電晶體的通道區之方法。
圖6是流程圖,說明用於製造電晶體的通道區之其它方法。
圖7是根據本發明的實施而建造的計算裝置。
105‧‧‧基底
110‧‧‧磊晶層間層
115‧‧‧磊晶層間層
120‧‧‧源極區
125‧‧‧汲極區
135‧‧‧閘極介電質
140‧‧‧閘極電極
145‧‧‧絕緣間隔器
146‧‧‧絕緣間隔器
150‧‧‧絕緣區
151‧‧‧絕緣區

Claims (30)

  1. 一種裝置,包括:具有表面的基底,其中,該表面包括具有第一晶格常數的第一磊晶材料,通道區,配置在該基底表面上,包括複數第二磊晶材料層以及複數第三磊晶材料層,其中,該第二磊晶材料的晶格常數大於該第一磊晶材料的晶格常數,其中,該第三磊晶材料的晶格常數小於該第一磊晶材料的晶格常數,以及,其中,該第二磊晶層及該第三磊晶層以交錯樣式配置,以及,閘極區,配置在該通道區的二或三側上,其中,該閘極區包括配置在閘極電極材料與該通道區之間的閘極介電材料。
  2. 如申請專利範圍第1項之裝置,其中,該通道區包括以交錯樣式配置之至少三層的第三磊晶材料層以及至少三層的第二磊晶材料層。
  3. 如申請專利範圍第1項之裝置,其中,該第一磊晶材料包括SiXGe1-X,該第二磊晶材料包括SiYGe1-Y,以及,該第三磊晶材料包括SiZGe1-Z,其中,Y>X、Z<X、1>X≧0,以及1≧Y>0、且1>Z≧0。
  4. 如申請專利範圍第1項之裝置,其中,該第一磊晶材料包括InP,該第二磊晶材料包括InXGa1-XAs,其中,1≧X>0.53,以及,該第三磊晶材料包括InYGa1-YAs,其中,0.53>Y≧0,或者,該第一磊晶材料包括GaSb,該 第二磊晶材料包括AlSb,以及,該第三磊晶材料包括InAs。
  5. 如申請專利範圍第1項之裝置,其中,該第一磊晶材料包括Ge,該第二磊晶材料包括SiXGe1-X,其中,1≧X>0,以及,該第三磊晶材料包括InYGa1-YAs,其中,1≧Y>0,或者,該第一磊晶材料包括GaAs,該第二磊晶材料層包括GaAsXP1-X,其中,1>X≧0,以及,該第三磊晶材料包括InYGa1-YP,其中,1≧Y>0.51。
  6. 如申請專利範圍第1項之裝置,其中,該通道區包括端部,以及源極區電耦合至第一端部且汲極區電耦合至第二端部。
  7. 一種裝置,包括:具有表面的基底,其中,該表面包括具有第一晶格常數的第一磊晶材料,通道區,配置在該基底表面上,其中,該通道區包括至少一奈米佈線或奈米條紋,其中,該通道區具有端部,至少一層間區,配置在該通道區的端部上,其中,該層間區包括複數第二磊晶材料層以及至少一層第三磊晶材料層,其中,該第二磊晶材料的晶格常數小於該第一磊晶材料的晶格常數,其中,該第三磊晶材料的晶格常數大於該第一磊晶材料的晶格常數,其中,該第二磊晶層及該第三磊晶層以交錯樣式配置,以及,其中,該至少一奈米佈線或奈米條紋包括該第三磊晶材料,以及,閘極區,配置在該至少一奈米佈線或奈米條紋的四側 上,其中,該閘極區包括配置在閘極電極材料與該通道區之間的閘極介電材料。
  8. 如申請專利範圍第7項之裝置,其中,該第一磊晶材料包括SixGe1-x,該第二磊晶材料包括SiYGe1-Y,以及,該第三磊晶材料包括SiZGe1-Z,其中,Y>X、Z<X、1>X≧0,以及1≧Y>0、且1>Z≧0。
  9. 如申請專利範圍第7項之裝置,其中,該第一磊晶材料包括InP,該第二磊晶材料包括InXGa1-XAs,其中,1≧X>0.53,以及,該第三磊晶材料包括InYGa1-YAs,其中,0.53>Y≧0,或者,該第一磊晶材料包括GaSb,該第二磊晶材料包括AlSb,以及,該第三磊晶材料包括InAs。
  10. 如申請專利範圍第7項之裝置,其中,該第一磊晶材料包括Ge,該第二磊晶材料包括SiXGe1-X,其中,1≧X>0,以及,該第三磊晶材料包括InYGa1-YAs,其中,1≧Y>0,或者,該第一磊晶材料包括GaAs,該第二磊晶材料層包括GaAsXP1-X,其中,1>X≧0,以及,該第三磊晶材料包括InYGa1-YP,其中,1≧Y>0.51。
  11. 如申請專利範圍第7項之裝置,其中,該裝置包括第一及第二層間區,其中,該通道區包括第一及第二端部,以及,其中,該第一層間區配置在該通道區的該第一端部上及該第二層間區配置在該通道區的該第二端部上。
  12. 如申請專利範圍第11項之裝置,其中,源極區電耦合至該第一層間區,以及,汲極區電耦合至該第二層 間區。
  13. 如申請專利範圍第7項之裝置,其中,該裝置包括複數奈米佈線或是奈米條紋。
  14. 一種裝置,包括:具有表面的基底,其中,該表面包括具有第一晶格常數的第一磊晶材料,通道區,配置在該基底表面上,其中,該通道區包括至少一奈米佈線或奈米條紋,其中,該通道區具有端部,至少一層間區,配置在該通道區的端部上,其中,該層間區包括複數第二磊晶材料層以及至少一層第三磊晶材料層,其中,該第二磊晶材料的晶格常數大於該第一磊晶材料的晶格常數,其中,該第三磊晶材料的晶格常數小於該第一磊晶材料的晶格常數,其中,該第二磊晶層及該第三磊晶層以交錯樣式配置,以及,其中,該至少一奈米佈線或奈米條紋包括該第三磊晶材料,以及,閘極區,配置在該複數奈米佈線或奈米條紋中的各奈米佈線或奈米條紋上,其中,該閘極區包括配置在閘極電極材料與該通道區之間的閘極介電材料。
  15. 如申請專利範圍第14項之裝置,其中,該第一磊晶材料包括SiXGe1-X,該第二磊晶材料包括SiYGe1-Y,以及,該第三磊晶材料包括SiZGe1-Z,其中,Y<X、Z>X、1>X≧0,以及1>Y>0、且1>Z≧0。
  16. 如申請專利範圍第14項之裝置,其中,該第一磊晶材料包括Ge,該第二磊晶材料包括InYGa1-YAs,其 中,1≧Y>0,以及,該第三磊晶材料包括SixGe1-x,其中,1≧X>0,或者,該第一磊晶材料包括GaAs,該第二磊晶材料包括InYGa1-YP,其中,1≧Y>0.51,以及,該第三磊晶材料包括GaAsXP1-X,其中,1>X≧0。
  17. 如申請專利範圍第14項之裝置,其中,該裝置包括第一層間區及第二層間區,其中,該通道區包括第一端部及第二端部,以及,其中,該第一層間區配置在該通道區的該第一端部上及該第二層間區配置在該通道區的該第二端部上。
  18. 如申請專利範圍第18項之裝置,其中,源極區電耦合至該第一層間區,以及,汲極區電耦合至該第二層間區。
  19. 如申請專利範圍第14項之裝置,其中,該裝置包括複數奈米佈線或是奈米條紋。
  20. 一種形成電晶體的通道區之方法,包括:設置基底,該基底具有表面,其中,該表面包括具有第一晶格常數的第一磊晶材料,以交錯方式,沉積a)及b),而在該基底表面上形成包括複數交錯層的a)及b)之層間區,其中,a)是第二磊晶材料,具有的晶格常數大於該第一磊晶材料的晶格常數,以及,b)是第三磊晶材料,具有的晶格常數小於該第一磊晶材料的晶格常數,將該層間區圖型化成通道區尺寸,在該通道區的端部形成源極和汲極區, 在該通道區的至少二側上沉積閘極介電質,以及沉積閘極電極至該閘極介電質上。
  21. 如申請專利範圍第20項之方法,其中,該通道區包括至少三層該第三磊晶材料。
  22. 如申請專利範圍第20項之方法,其中,該通道區包括至少三層該第二磊晶材料。
  23. 一種形成電晶體的通道區之方法,包括:設置基底,該基底具有表面,其中,該表面包括具有第一晶格常數的第一磊晶材料,以交錯方式,沉積a)及b),而在該基底表面上形成包括複數交錯層的a)及b)之層間區,其中,a)是第二磊晶材料,具有的晶格常數大於該第一磊晶材料的晶格常數,以及,b)是第三磊晶材料,具有的晶格常數小於該第一磊晶材料的晶格常數,將該層間區圖型化成通道區尺寸,在該通道區的端部形成源極及汲極區,選擇性地蝕刻掉該第三磊晶材料,形成包括該第一磊晶材料的奈米佈線或奈米條紋,在該奈米佈線或奈米條紋上沉積閘極介電質,以及,將閘極電極沉積至該閘極介電質上。
  24. 如申請專利範圍第23項之方法,其中,該通道區包括複數奈米條紋或奈米佈線。
  25. 一種計算裝置,包括:主機板; 通訊晶片,安裝於該主機板上;以及處理器,安裝於該主機板上,該處理器包括電晶體,該電晶體包括通道區,該通道區包括:具有表面的基底,其中,該表面包括具有第一晶格常數的第一磊晶材料,通道區,配置在該基底表面上,包括複數第二磊晶材料層以及複數第三磊晶材料層,其中,該第二磊晶材料的晶格常數大於該第一磊晶材料的晶格常數,其中,該第三磊晶材料的晶格常數小於該第一磊晶材料的晶格常數,以及,其中,該第二磊晶層及該第三磊晶層以交錯樣式配置,以及,閘極區,配置在該通道區的二或三側上,其中,該閘極區包括配置在閘極電極材料與該通道區之間的閘極介電材料。
  26. 如申請專利範圍第25項之裝置,其中,該通道區包括至少三層的第三磊晶材料。
  27. 一種計算裝置,包括:主機板;通訊晶片,安裝於該主機板上;以及處理器,安裝於該主機板上,該處理器包括電晶體,該電晶體包括通道區,該通道區包括:具有表面的基底,其中,該表面包括具有第一晶 格常數的第一磊晶材料,通道區,配置在該基底表面上,其中,該通道區包括包含第二磊晶材料的至少一奈米佈線或奈米條紋,其中,該通道區具有端部,至少一層間區,配置在該通道區的端部上,其中,該層間區包括複數第二磊晶材料層以及複數第三磊晶材料層,其中,該第二磊晶材料的晶格常數大於該第一磊晶材料的晶格常數,其中,該第三磊晶材料的晶格常數小於該第一磊晶材料的晶格常數,其中,該第二層及該第三層以交錯樣式配置,以及,閘極區,配置在該複數奈米佈線或奈米條紋的各奈米佈線或奈米條紋上,其中,該閘極區包括配置在閘極電極材料與該通道區之間的閘極介電材料。
  28. 如申請專利範圍第27項之計算裝置,其中,該通道區包括複數奈米條紋或奈米佈線。
  29. 一種計算裝置,包括:主機板;通訊晶片,安裝於該主機板上;以及處理器,安裝於該主機板上,該處理器包括電晶體,該電晶體包括通道區,該通道區包括:具有表面的基底,其中,該表面包括具有第一晶格常數的第一磊晶材料,通道區,配置在該基底表面上,其中,該通道區 包括包含第二磊晶材料的至少一奈米佈線或奈米條紋,其中,該通道區具有端部,至少一層間區,配置在該通道區的端部上,其中,該層間區包括複數第二磊晶材料層以及複數第三磊晶材料層,其中,該第二磊晶材料的晶格常數小於該第一磊晶材料的晶格常數,其中,該第三磊晶材料的晶格常數小於該第一磊晶材料的晶格常數,其中,該第二磊晶層及該第三磊晶層以交錯樣式配置,以及,閘極區,配置在該複數奈米佈線或奈米條紋的各奈米佈線或奈米條紋上,其中,該閘極區包括配置在閘極電極材料與該通道區之間的閘極介電材料。
  30. 如申請專利範圍第29項之計算裝置,其中,該通道區包括複數奈米條紋或奈米佈線。
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