TWI226679B - Method for fabricating strained multi-layer structure - Google Patents

Abstract

A method for fabricating a strained multi-layer structure. First, a step-graded silicon germanium (Si1-xGex) buffer layer is deposited overlying a substrate. Subsequently, a silicon germanium capping layer is deposited on the step-graded silicon germanium buffer layer. Finally, a single crystalline silicon layer is deposited on the silicon germanium capping layer to form a strained layer. The step-graded silicon germanium layer, the silicon germanium buffer layer, and the single crystal silicon layer are formed by reduced pressure chemical vapor deposition (RPCVD) using disilane or trisilane as a process precursor. A field effect transistor (FET) having a strained layer is also disclosed.

Description

1226679 V. Description of the invention (1) '" --- Field of invention The present invention relates to a method for manufacturing a semiconductor device, in particular, f relates to a method for manufacturing a multilayer structure with strain and a field-effect electric field with a strain layer. Sun body method. The prior art: "The size of the conductor element must be continuously reduced to increase the integration of the integrated circuit to improve the performance of the device. However, for example, the two 'are used in semiconductor devices commonly used in two-body circuits, such as the metal-oxygen half field. It is very difficult for it to have a high drive motor and high efficiency at low operating voltage. Therefore, many people are working hard to improve the performance of metal-oxide-semiconductor half-field-effect transistor devices. At present, it has been proposed to increase the mobility of carriers by using the band structure modification caused by stress to increase the driving current of the field effect transistor, which can improve the performance of the field effect transistor element, and this method has been applied to Among the various elements, the Shi Xi channels of these elements are in a strained condition. Traditionally, the Si Xi channel layers are grown by stupid crystals on a relaxed Si Ge layer or substrate to prepare strained Shi Xi layer. Before growing a strained silicon channel layer, it is usually necessary to grow a SUex layer with a gradually deformed lattice on the silicon substrate, where the ratio X of the error is gradually increased from 0 to 0.2, here It is called a step-graded stone germanium buffer layer. Then a layer of loose silicon germanium (SiG7Ge (). 3) cap is grown on the step-graded silicon germanium buffer layer. Prepared by epitaxy method, of which the low pressure chemical vapor deposition method is the most common.

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In terms of the reaction gases (process precursors) used are SiCl4, SiH2Cl2, SiHcf (S1 Η *), etc. The growth mechanism can be determined by the growth rate. The curve of temperature and temperature 3 was obtained. Generally, the relationship curve of the four gases (above 80 (TC) or higher) is small, but it is larger in the low temperature region, with a point of -π spine 1 in the region. In the region with a small slope The growth rate is less affected by temperature. The mass transfer rate from the main reaction gas to the substrate is directly proportional. This area is called the ^ mass transfer controlled region. On the other hand, the growth is in the area with a large slope and grows. The rate is related to the surface reaction rate, and it has an exponential relationship with the temperature production. This region is called the surface reaction control region (reaction controlled region). The uniformity of the crystalline film formed in the mass transfer control region (at high temperature) is better than Surface reaction controlled region (surface reaction controlled region), but the high growth temperature required for the reaction gas used is not conducive to the integration of the strained film into the semiconductor process, so in the current semiconductor process, the epitaxial growth is more than the surface The reaction control zone is performed. If ultra-high vacuum CVD (UHVCVD) is used, each wafer will take at least ten hours or more. That is, the production capacity will be seriously affected due to the excessively long manufacturing time. However, the preparation of stupid thin films at low temperatures (eg, below 700 ° C) is time consuming, especially when using the above-mentioned reaction gases. For example, & Deposition (iow pressure CVj), LPCVD) epitaxial growth and the use of silane as a process precursor, each wafer in the production of strained multilayer structure, it takes at least one hour or more.

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V. Description of the invention (3) US Patent No. 5,951,757 discloses a half of a silicon germanium sound, A is formed by passivation of a sapphire substrate surface with hydrogen, a / ', as a precursor of the process to form a stone layer. . 4, ： = burned and misfired US6, 410, 371 discloses a manufacturing method with a silicon / silicon-germanium S main insulating layer (SOI), its saxi: the stone of the moving layer == one with the dioxide & quot After the stone and silicon substrate of the stone and germanium layer, the silicon dioxide layer of the two silicon substrates is bonded by high temperature bonding technology to form a silicon insulation with a silicon / silicon germanium / silicon layer active layer. Layer substrate. Furthermore, U.S. Patent No. 6,5 1 5, 335 discloses a method for fabricating a relaxed silicon germanium layer on a silicon insulating layer substrate, which first forms a wetting layer (wetting laye; r) on a silicon insulating layer base. ), Followed by molecular beam epitaxy (MBEJ) or CVD in order to form silicon germanium islands and a silicon germanium cap layer covering the islands in order, and then through a tempering process to make the wet layer, silicon germanium islands, The top cover layer of Shi Xicu interacts with each other to form a single crystal silicon germanium layer, and finally a strained epitaxial silicon layer is formed thereon. In these methods, either silane is still used as the precursor of the process or the process is too complicated to effectively increase the production capacity of components. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a method for manufacturing a multilayer structure having a strain and a field effect transistor having a strain layer. It uses Ershixue Yigan or Sanshixue Yuanyuan as precursors of the chemical vapor deposition process to replace traditional methane or two-gas silane precursors, thereby greatly increasing the deposition rate.

1226679 V. Description of the invention (4) The rate will further increase the production capacity of components. The lack of structure is described in the present invention, which provides a substrate with multiple strains. A substrate is provided, and then deposited on the substrate.-: Λ π i / IT ex) buffer layer, where χ is thickened with the progressive silicon germanium buffer layer = 〇, increased to 0.3. Subsequently, in the progressive dream error buffer; degree two :, deposited on the Shi Xi germanium overlying layer-single crystal Shi Xi layer V! Shi Xi germanium overlying layer and single crystal silicon and further includes a silicon buffer layer with a thickness of 0.1 to The 0.99 micro-Z, Zn, and Zn are formed by using disiloxane / trisilane propane as the process driver, and the total silicon buffer layer is formed by Zuo Zongnong 4, ~, tq schedule. In addition, the above substrate may be a silicon substrate formed in a range of a meter between the substrate and the progressive silicon germanium buffer layer. The thickness of the germanium buffer layer is in the range of 2 to 5 microns. Shi Xi The degree of germanium interest layer ranges from 0.5 to 1 micron. Single crystals are in the range of 100 to 300 Angstroms. On weekdays, the silicon layer, the progressive silicon germanium buffer layer, the silicon germanium cap layer, and the single crystal silicon layer can be formed by reduced pressure chemical vapor deposition (RPCVD). Among them, the range is from 50 Torr to 760 TOrr ·. According to the above-mentioned object, the present invention provides a method for manufacturing an effective transistor with a strained sound. First of all, mention _ 一 Qi Qi Bu ,, 7 Γ, and a roll of W. · Xi substrate, and then buffer # in the silicon substrate, the sound layer (Sll.xGex) buffer layer, in which χ with progressive Shi Xi germanium, washed The population increases from G to 0.3. Subsequently, the layer was deposited on top of the layer—Shi Xico. Then, cover the cover layer in Shixicuo ::

Page 10 1226679 V. Description of the invention (5) The spar layer is used as a sturdy rain-gate structure and at the end of the second degree, a square source / drain region on the strained channel layer. A precursor is formed in the strain channel layer on the outside of the structure in Nongzhong, with the disilane / trisilane propane as the crystalline fragmentation layer. In addition, between the punching layers, y into the silicon germanium buffer layer, silicon germanium cap layer and single = package a — the silicon buffer layer is formed on the silicon substrate and the progressive silicon germanium buffer [, thickness of 0. 1 to 0. 9 Micrometer range. , ^. ^ S, the thickness of the SiGe buffer layer is in the range of 2 to 5 microns. Shi Xi

The thickness of the layer is in the range of 0.5 to 1 micron. The thickness of the monocrystalline stone layer ranges from 100 to 300 Angstroms. For dry goods, the progressive silicon germanium buffer layer, silicon germanium cap layer, and single crystal silicon layer can be formed by f-pressure chemical vapor deposition (rpcvd). Among them, the process temperature of the decompression chemical lice phase deposition ranges from 601 to 801, and the process pressure ranges from 50 Torr to 760 Torr. Furthermore, the gate structure includes a gate dielectric layer, a gate electrode, and a gate spacer. The gate dielectric layer is disposed above the strained channel layer. The idle electrode is disposed above the gate dielectric layer, and the gate gap wall is disposed on the side wall of the gate electrode. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: The embodiments are described below in conjunction with Figures 1A to 1C and Figure 2 Figure illustrates the system of the embodiment of the present invention

1226679 V. Description of the invention (6) Method for making field effect transistor with strain layer. First, referring to FIG. 1A, a substrate 10 is provided. The substrate 10 is a single crystal substrate, a silicon substrate (siliconon in; u ^ 2 is so I), or another semiconductor substrate. Here, a single crystal evening crystalline substrate with a crystal orientation of ^ 00 is used as an example. Above the substrate 10, a stone evening buffer layer 12 may be included, which is used as a seed layer (seed 1 ay er) for the subsequent deposition of the silicon germanium buffer layer. In this embodiment, the Shixi buffer layer 12 may be formed on the substrate 10 by epitaxial method. For example, a silicon-containing compound is used as a reaction gas to perform chemical vapor deposition (CVD). The thickness of the formed silicon buffer layer 12 is in the range of 0. 1 to 0. 9 micrometers (# m), and the preferred thickness is about 0. 5 // m 0 ′. Next, a silicon germanium is deposited on the silicon buffer layer 12 Floor. In this embodiment, the silicon germanium layer includes upper and lower portions. The lower part is a setp-graded silicon germanium (SiixGex) buffer layer 14 and the upper part is a relaxed silicon germanium cap layer 16 (as shown in Figure 1β): In the progressive silicon germanium buffer layer 1 In 4, the atomic ratio of germanium is gradually increased from 0 to 0.3 as the thickness of the progressive silicon germanium layer 14 increases, and the rate of increase is in the range of 0.1 to 0.15 / m. That is, the content of germanium at the interface between the progressive silicon germanium buffer layer 4 and silicon buffer = 12 is about 0, and the content of germanium at the top θ portion of the progressive silicon germanium buffer layer 14 is about 0.3. In this embodiment, the progressive silicon germanium buffer layer 14 can be formed by an epitaxial method. The method can be as follows: using disilane (Si ^ ^ trisilane, Si ^) as the silicon source process region 3, and using germane (GeH4) as the precursor of the process of germanium source

1226679 V. Description of the invention (7) Reduced pressure chemical vapor deposition (CVD). Among them, the deposition process temperature ranges from 600 ° C to 80 0 ° C. Moreover, the process pressure ranges from 50 Torr to 76 0 Torr. The thickness of the formed silicon-germanium buffer layer 14 is in the range of 2 to 5 / zm, and the preferred thickness is about 2.1 #m. Next, Fuling according to FIG. 丨 B, similarly, the SiiyGey cap layer deposited on the wrong-cut buffer layer 14 by epitaxial method is in the ratio of two: Shijin Shixi: buffer layer 14, silicon Among the germanium atoms in the germanium cap layer 16, Shi Xilu is in the range of 0.25 to 0.3. In this embodiment, similarly, using disilane or trisilpropane as the process precursor of the L source and using the misfire as the source of germanium before the process :: to mt. Moreover, Ershi Xi ...; Shi == Wai. Furthermore, the range of shoe making Λ, 1 is in the range of 50 to 200 sccm = the thickness of the upper cover layer 16 is in 0.5, and the range of η_ is about 0 · 9 // m. Here, the silicon button drawer is best from the heart w; the degree of convergence and the reduction of 1 stomach, the stomach n θ, the progressive silicon germanium buffer layer 14 are used for two votes and H, middle and small lattice defects_ Differential row (for this purpose. Cat ion) @SiGe cap layer 16 provides the subsequent formation of a strain layer on the "SiGe buffer layer" and the SiGe cap layer a on the eight > monocrystalline silicon layer 丨8. In order to form a follow-up transistor, the S # a ~ change evening layer 'is used as a strain channel layer made by silly electric day and night. In this embodiment, 18 is also formed by an epitaxial method. Every day and night, I use mono- or tri-silicon. Page 13 0503-9762twF (nl); tsmc2002-1390; Spin.ptd 1226679 V. Description of the invention (8) Burning as a precursor to the process of Shixi source, Decompression chemical vapor deposition was performed. Among them, the deposition process temperature is in the range of 60 (pc to 800). Furthermore, the process pressure is in the range of 50 Torr to 760 Torr. The thickness of the formed single crystal silicon layer 18 is in the range of 100 to 300 Angstroms (A), and The preferred thickness is about 135 A. In this way, the strained multilayer structure of the present invention is completed. Finally, please refer to FIG. 丨 c, and form a pole structure 25 above the strained silicon layer 丨 8. It includes a The gate dielectric layer 20, a gate electrode 22, and a gate electrode 2 4 The gate dielectric layer 20 is disposed above the strained silicon layer 18 as a channel layer, and then the gate electrode 2 2 It is arranged above the gate dielectric layer 20. In addition, the gate gap wall 24 is arranged on the side wall of the gate electrode. -Yu Ϊ * The method of forming the gate structure 25 is as follows: First, the rheological layer 18 A monolithic oxide layer (not shown) is formed above it; == 糸 is less than 80 (rc. Then, 'the conventional deposition technique can be used, b) m to form a polymorphite layer over the silicon oxide layer ( The house is composed of μr lithography and rice carving, which defines the oxide layer 22. The virtue of the gate electrode is composed of a polycrystalline silicon layer. The sidewall of the interelectrode and: = = deposited on the surface of the strained stone layer 18 and using anisotropy _ delamination (not shown),… ,, RIE), hafnium nitride: off == = ve ion lower part Layer 24 of nitrided stone, which is used for: p / on the side wall of the gate electrode 22 to complete the gate structure 25 to make the closed-cell gap wall. Structure 2 5 outside strain channel layer 〖8 2 can be hunted Ion implanted in the gate junction for source / drain region: doped region 26 is formed in the upper f-layer 16. Thus, the strained layer 0503-9762twF (nl); tsmc2002.i390; Spin. ptd Page 14 1226679 V. Description of the invention (9) Fabrication of metal-oxide-semiconductor field-effect transistor (MOSFET) It should be noted that 'Although the present invention is based on a multilayer structure with strain as an example, it is familiar with this The artist can integrate the present invention into the production of other semiconductor devices, such as CMOS transistors, according to the needs of the design of circuit components. Next, referring to FIG. 2, it shows the logarithmic deposition rates of precursors of different processes (" m / min) Shaw reaction temperature (t) curve three = previously described, each in the figure The slopes of the curves A, B, c, D, and E are smaller at the local temperature, but at a low temperature, there is a turning point. The area with a small slope is the mass transfer control area, and the area with a large slope, That is the surface fj control, area. In addition, the A curve indicates that the methylene chloride curve (si C 丨 4) is used as the m'B curve table, and the chloroform (siHci3) is used as the precursor of the manufacturing process. This C_ curve table is not based on Dichlorosilane (SiH2C12) is the precursor of the process, and 卩 曲 二 r J Γ 院 院 (S14) is the precursor of the process, and the E curve shows that it is the precursor of the Ershixi B: material process. Obviously, before using conventional processes

Hi, C, D), if the reaction temperature of the sink 2 in the mass transfer control zone is too high (more than ⑻) or higher), it is not suitable for 7; iL layer, but 'if it is the precursor of the process used in the present invention (P curve E), the reaction temperature can be reduced below 800 t. _ #In addition, in view of the current low temperature (eg below 700 ° C) epitaxy: eFw

The product rate is also based on the conventional technology (curves A, β, c, and D i increase the deposition rate and effectively shorten the process time, which in turn increases the production capacity of the component and reduces the production cost.

1226679 V. Description of the Invention (ίο) Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make the invention without departing from the spirit and scope of the present invention. Changes and retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.

0503-9762twF (nl); tsmc2002-1390; Spin.ptd Page 16 1226679 Brief description of the diagrams 1 A to 1 C are diagrams showing the process of manufacturing a field effect transistor with a strained layer according to an embodiment of the present invention Schematic cross-section. Figure 2 is a graph showing the relationship between the logarithmic deposition rate of precursors in different processes and the reaction temperature. Explanation of symbols 1 2 ~ with buffer layer; 16 ~ silicon germanium cap layer; 20 ~ gate dielectric layer; 24 gate spacer; 2 ~ source / non-electrode area. 1 0 ~ substrate; 1 4 ~ progressive > 5x germanium buffer layer 18 ~ single crystal silicon layer; 2 2 ~ gate electrode; 2 5 ~ gate structure;

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Claims (1)

1226679 I 'Application for patent application ^ "' " ---- «· " -— 1 · A method for manufacturing a strained multilayer structure, including the following steps: · Provide a substrate; A progressive silicon germanium (Sii-xGex) buffer layer, wherein X ^ the progressive silicon germanium buffer layer increases in thickness from 0 to 0.3; a silicon germanium cap layer is deposited on the progressive silicon germanium buffer layer; and A monocrystalline silicon layer is deposited on the Shixi germanium cap layer to form a strained layer. The progressive silicon germanium buffer layer, the silicon germanium are sequentially formed by using the two stone sintering / three stone sintering as the process precursor. A cap layer and the single crystal silicon layer. 2. The method for manufacturing a strained multilayer structure as described in item 1 of the scope of patent application, wherein the substrate is a silicon substrate. 3. The method of manufacturing a strained multilayer structure as described in item 2 of the scope of the patent application, further comprising forming a silicon buffer layer between the substrate and the progressive silicon buffer layer. 4. The method for manufacturing a strained multilayer structure as described in item 3 of the scope of the patent application, wherein the thickness of the silicon buffer sound is in the range of 0.1 to 0.9 microns. 95. The method of manufacturing a strained multilayer structure as described in item 1 of the scope of the patent application, wherein the thickness of the progressive silicon germanium retardation layer is in the range of 2 to 5 microns. 6. The method for manufacturing a strained multilayer structure as described in item 1 of the scope of the patent application, wherein the thickness of the cap layer on the Shi Xicuo is in the range of 0.5 to 1 micrometer. 7. Manufacture a strained multilayer junction as described in item 1 of the scope of patent application 0503-9762twF (nl); tsmc2002-1390; Spin.ptd page 18 1226679 6. Method of patent application structure, wherein the purity of the single crystal silicon layer is in the range of 100 to 300 angstroms. 8. The method for manufacturing a strained multilayer structure as described in item 1 of the scope of the patent application, wherein the progressive silicon germanium buffer layer, the silicon germanium cap and the single crystal are formed by reduced pressure chemical fluorine phase deposition (RPCVD). Silicon layer. 9. The method for manufacturing a strained multilayer structure as described in item 8 of the scope of the patent application, wherein the process temperature of the vacuum chemical vapor deposition is in the range of 600 ° C to 800 ° C. 〃 10 · The method for manufacturing a strained multilayer structure as described in item 8 of the scope of the patent application, wherein the process pressure of the reduced pressure chemical vapor deposition is in a range of 50 Torr to 760 Torr. 11. A method for manufacturing a field effect transistor with a strained layer, comprising the following steps: providing a silicon substrate; depositing a progressive silicon germanium (Sii_xGex) buffer layer on the broken substrate, wherein X varies with the thickness of the progressive silicon germanium buffer layer Increase from 0 to 0.3; deposit a silicon germanium cap layer on the progressive silicon germanium buffer layer; deposit a single crystal silicon layer on the silicon germanium cap layer as a strain channel layer; on the A gate structure is formed above the strained channel layer; and a source / drain region is formed in the strained channel layer outside the gate structure, wherein disiloxane / trisilane is used as a process precursor to The progressive SiGe buffer layer, the SiGe cap layer and the single crystal Si layer are sequentially formed. 0503-9762twF (nl); tsmc2002-1390; Spin.ptd Page 19 1226679 VI. Patent Application Fanyuan-12. Method of manufacturing a% -effect electrical body with a strain layer as described in item 11 of the scope of patent application Furthermore, a Shixi buffer layer is formed between the Shixi substrate and the progressive SiGe buffer layer. 13. The method of manufacturing a field effect transistor having a strained layer as described in item 12 of the scope of patent application, wherein the employment of the silicon buffer layer is in the range of 0.1 to 0.9 micrometers. 14. The method for forming a field effect transistor with a strained layer as described in item 11 of the scope of the patent application, wherein the thickness of the progressive silicon germanium retardation layer is in the range of 2 to 5 microns. '15. The method for manufacturing a field effect transistor having a strained layer as described in item 11 of the scope of the patent application, wherein the thickness of the silicon germanium cap layer is in the range of 0.5 to 1 micrometer. 16. The method for manufacturing a field effect transistor having a strained layer as described in item 11 of the scope of the patent application, wherein the thickness of the single crystal silicon layer is in a range of 100 to 300 Angstroms. 17. The method for manufacturing a field effect transistor having a strained layer as described in item u of the scope of the patent application, wherein the progressive silicon germanium buffer layer, the silicon germanium cap layer and the silicon germanium cap layer are formed by reduced pressure chemical fluorine phase deposition (RPCVD). The strained silicon layer. 18. The method for manufacturing a field effect transistor having a strained layer as described in item 17 of the scope of the patent application, wherein the process temperature of the vacuum chemical vapor deposition is in a range of 600 ° C. to 800 ° C. 19. The method for manufacturing a field effect transistor with a strained layer as described in item 17 of the scope of the patent application, wherein the process pressure of the vacuum chemical vapor deposition is in a range of 50 Torr to 760 Torr. 0503-9762twF (nl); tsmc2002-1390; Spin.ptd page 20 1226679 6. Application for patent scope 2 0. Method for manufacturing field effect transistor with strained layer as described in item 11 of the scope of patent application 'where the The gate structure further includes: a gate dielectric layer disposed above the strain channel layer; a gate electrode disposed above the gate dielectric layer; and a gate gap wall disposed on a side wall of the gate electrode . 0503-9762twF (nl); tsmc2002-1390; Spin.ptd p. 21