TW200514200A - Method for fabricating strained multi-layer structure - Google Patents
Method for fabricating strained multi-layer structureInfo
- Publication number
- TW200514200A TW200514200A TW092128512A TW92128512A TW200514200A TW 200514200 A TW200514200 A TW 200514200A TW 092128512 A TW092128512 A TW 092128512A TW 92128512 A TW92128512 A TW 92128512A TW 200514200 A TW200514200 A TW 200514200A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- silicon germanium
- deposited
- strained
- graded
- Prior art date
Links
Abstract
A method for fabricating a strained multi-layer structure. First, a step-graded silicon germanium (Si1-xGex) buffer layer is deposited overlying a substrate. Subsequently, a silicon germanium capping layer is deposited on the step-graded silicon germanium buffer layer. Finally, a single crystalline silicon layer is deposited on the silicon germanium capping layer to form a strained layer. The step-graded silicon germanium layer, the silicon germanium buffer layer, and the single crystal silicon layer are formed by reduced pressure chemical vapor deposition (RPCVD) using disilane or trisilane as a process precursor. A field effect transistor (FET) having a strained layer is also disclosed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW92128512A TWI226679B (en) | 2003-10-15 | 2003-10-15 | Method for fabricating strained multi-layer structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW92128512A TWI226679B (en) | 2003-10-15 | 2003-10-15 | Method for fabricating strained multi-layer structure |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI226679B TWI226679B (en) | 2005-01-11 |
TW200514200A true TW200514200A (en) | 2005-04-16 |
Family
ID=35634286
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW92128512A TWI226679B (en) | 2003-10-15 | 2003-10-15 | Method for fabricating strained multi-layer structure |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI226679B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI493714B (en) * | 2011-12-09 | 2015-07-21 | Intel Corp | Method for forming channel region of transistor, transistor and computing device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111549440B (en) * | 2020-05-20 | 2021-05-07 | 泉州市鼎丰针织机械有限公司 | Needle pressing triangle of double-faced rib knitting machine |
-
2003
- 2003-10-15 TW TW92128512A patent/TWI226679B/en not_active IP Right Cessation
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI493714B (en) * | 2011-12-09 | 2015-07-21 | Intel Corp | Method for forming channel region of transistor, transistor and computing device |
US9159823B2 (en) | 2011-12-09 | 2015-10-13 | Intel Corporation | Strain compensation in transistors |
US9306068B2 (en) | 2011-12-09 | 2016-04-05 | Intel Corporation | Stain compensation in transistors |
US9614093B2 (en) | 2011-12-09 | 2017-04-04 | Intel Corporation | Strain compensation in transistors |
US9911807B2 (en) | 2011-12-09 | 2018-03-06 | Intel Corporation | Strain compensation in transistors |
US10224399B2 (en) | 2011-12-09 | 2019-03-05 | Intel Corporation | Strain compensation in transistors |
US10388733B2 (en) | 2011-12-09 | 2019-08-20 | Intel Corporation | Strain compensation in transistors |
US10748993B2 (en) | 2011-12-09 | 2020-08-18 | Intel Corporation | Strain compensation in transistors |
Also Published As
Publication number | Publication date |
---|---|
TWI226679B (en) | 2005-01-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |