WO2007046150A1 - Fin type semiconductor device and method for manufacturing same - Google Patents

Fin type semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2007046150A1
WO2007046150A1 PCT/JP2005/019388 JP2005019388W WO2007046150A1 WO 2007046150 A1 WO2007046150 A1 WO 2007046150A1 JP 2005019388 W JP2005019388 W JP 2005019388W WO 2007046150 A1 WO2007046150 A1 WO 2007046150A1
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WO
WIPO (PCT)
Prior art keywords
fin
semiconductor film
core member
semiconductor device
channel structure
Prior art date
Application number
PCT/JP2005/019388
Other languages
French (fr)
Japanese (ja)
Inventor
Takashi Mimura
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Fujitsu Limited
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Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2005/019388 priority Critical patent/WO2007046150A1/en
Priority to JP2007540867A priority patent/JP5167816B2/en
Publication of WO2007046150A1 publication Critical patent/WO2007046150A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Definitions

  • the present invention relates to a fin-type semiconductor device and a method for manufacturing the same, and more particularly to a fin-type semiconductor device in which a gate electrode is disposed so as to sandwich a fin-shaped portion and a method for manufacturing the same.
  • Non-Patent Documents 1 and 2 below disclose fin-type MOSFETs.
  • a fin-type MOS FET a fin-type semiconductor portion protruding almost vertically from the substrate surface is used as a channel, and gate electrodes are arranged on both sides thereof. Since the channel potential is controlled from both sides, the short channel effect can be reduced.
  • Patent Document 1 discloses a fin-type MOSFET in which a strained channel layer is formed on the surface of a seed fin that has no strain and also has a semiconductor material force. Carrier mobility can be increased by imparting strain to the channel layer.
  • Patent Document 1 JP 2005-19970
  • Non-Patent Literature 1 Sang- YunKim et ai., Hot Carrier-Induced Degradation in BulkFinFE Ts ", IEEE Electron Device Letters, Vol. 26, No.8, p.566—p.568 (2005)
  • Non-Patent Document 2 Ta et SuPark et al., "Characteristics of Body-Tied Triple-GatepMOSF ETs", IEEE Electron Device Letters, Vol.25, No.12, p.798—p.800 (2004)
  • An object of the present invention is to provide a fin-type semiconductor device capable of increasing the operating speed and a method for manufacturing the same.
  • a fin-shaped core member is formed on a support substrate in a posture in which the thickness direction is parallel to the surface of the support substrate and is formed of a semiconductor material, and the core member A semiconductor material force different from that of the first semiconductor film covering the two side surfaces of the core member.
  • Disposed on both sides of the channel structure and a part of the channel structure, facing the side surface of the channel structure, or facing the side surface of the channel structure through a gate insulating film A source electrode and a drain region formed on both sides of a region sandwiched between the gate electrodes of the channel structure, and the core member in the region sandwiched between the gate electrodes has a strain.
  • a fin-type semiconductor device is provided.
  • an underlying structure having a fin-like member having a semiconductor material force disposed on a surface of a support substrate in a posture in which a thickness direction is parallel to the surface of the support substrate.
  • a step of preparing a step of forming an insulating film so as to embed the fin-shaped member on the base structure, and a recess formed in the insulating film so that a part of the upper end of the fin-shaped member appears.
  • the core member Since the core member is distorted, the mobility of carriers accumulated at the interface between the core member and the first semiconductor film can be increased.
  • a channel is formed at the interface between the core member and the first semiconductor film, it is not affected by the roughness or interface state of the interface between the semiconductor and the gate insulating film. Thereby, the mobility of a carrier can be raised.
  • the characteristics of the semiconductor device can be improved by thinning a part of the fin-like member appearing in the recess.
  • FIG. 1 is a perspective view of a fin-type MOSFET according to a first embodiment.
  • FIGS. 2A and 2B are cross-sectional views of an apparatus in the course of manufacturing a fin-type MOSFET according to the first embodiment.
  • FIGS. 2C and 2D are cross-sectional views of the apparatus in the course of manufacturing the fin-type MOSFET according to the first embodiment.
  • FIGS. 2E and 2F are cross-sectional views of the apparatus in the course of manufacturing the fin-type MOSFET according to the first embodiment.
  • FIGS. 2G and 2H are cross-sectional views of the device in the process of manufacturing the fin-type MOSFET according to the first embodiment.
  • FIG. 21 is a cross-sectional view of the device in the middle of manufacturing the fin-type MOSFET according to the first embodiment.
  • FIGS. 3A and 3B are cross-sectional views of a device in the process of manufacturing a fin-type MOSFET according to the first embodiment.
  • FIGS. 3C and 3D are cross-sectional views of the device in the process of manufacturing the fin-type MOSFET according to the first embodiment.
  • FIG. 4 is an energy band diagram of the fin-type MOSFET according to the first embodiment.
  • FIG. 5A is a cross-sectional view of a fin-type MOSFET according to a second embodiment, and FIG. 5B is its energy band diagram.
  • FIG. 6A is a cross-sectional view of a fin-shaped portion of a fin-type MOSFET according to a third embodiment, and FIG. 6B is an energy band diagram.
  • FIG. 1 shows a perspective view of a fin-type MOSFET according to the first embodiment.
  • a fin-like base member 2B protrudes from the surface of the support substrate 1 in a substantially vertical direction.
  • Define an XYZ Cartesian coordinate system in which the surface of the support substrate 1 is the XY plane and the plane parallel to the side surface of the base member 2B is the ZX plane.
  • the length direction of the base member 2B is parallel to the X axis, and the thickness direction of the base member 2B is parallel to the Y axis.
  • the fin-shaped core member 2A protrudes in the Z-axis direction from the upper surface of the base member 2B.
  • the side surface of the core member 2A is also parallel to the ZX plane, and the thickness of the core member 2A is thinner than that of the base member 2B.
  • the support substrate 1, the base member 2B, and the core member 2A are formed of silicon (Si) single crystal.
  • the base member 2B has a thickness of 40 nm and a height of 260 nm.
  • the core member 2A has a thickness of 5 nm and a height of 130 nm.
  • the first insulating film 3 also having an oxide silicon force covers the upper surface of the support substrate 1 and the side surface of the base member 2B so as to be along the base surface.
  • the thickness of the first insulating film 3 is, for example, 10 nm.
  • Nitro The second insulating film 4 that also has siliconizing power covers the surface of the first insulating film 3 along the base surface.
  • the thickness of the second insulating film 4 is, for example, 50 nm.
  • a third insulating film 5 having an oxide silicon force is disposed on the flat surface of the second insulating film 4.
  • the upper end surfaces of the first and second insulating films 3 and 4 on the side surface of the base member 2B are not covered with the third insulating film 5.
  • the upper surface of the third insulating film 5 is positioned higher than the upper end surfaces of the first and second insulating films 3 and 4, and is positioned slightly higher than the upper surface of the core member 2A. For this reason, the upper end surfaces of the first and second insulating films 3 and 4 are defined as a part of the bottom surface, and a recess 8 in which the third insulating film 5 is exposed on the side surface is defined. The bottom force of the recess 8 The core member 2A protrudes upward.
  • the side surface and the upper end surface of the core member 2A are covered with a first semiconductor film 10 made of SiGe.
  • the first semiconductor film 10 is epitaxially grown on the surface of the core member 2A, and the thickness thereof is, for example, 5 to: LOnm. Due to the difference in lattice constant between Si and SiGe, a tensile strain is generated in the core member 2A immediately after the first semiconductor film 10 is formed, and a compressive strain is generated in the first semiconductor film 10.
  • a fin-like structure including the core member 2A and the first semiconductor film 10 is referred to as a channel structure 11.
  • the surface force of the channel structure 11 is covered with a gate insulating film 15 made of silicon oxide.
  • the thickness of the gate insulating film 15 is, for example, lnm
  • a gate electrode 18 that is long in the Y-axis direction is formed on the third insulating film 5 so as to cross the channel structure 11 that is long in the X-axis direction.
  • the gate electrode 18 is made of, for example, polysilicon.
  • the gate electrode 18 reaches the bottom surface of the recess 8 in a region overlapping with the recess 8, and faces the upper surface and side surface of the channel structure 11 through the gate insulating film 15.
  • a silicon nitride is formed so as to cover a region continuing to the side surface of the gate electrode 18 and the surface of the gate electrode 18.
  • a stressor 25 made of (SiN) is formed.
  • 2A to 21 correspond to a cross section parallel to the YZ plane passing through the intersection of the gate electrode 18 and the core member 2A in the perspective view shown in FIG. 3D corresponds to a cross section parallel to the ZX plane.
  • a base structure in which the fin-like member 2 protrudes in a substantially vertical direction from the surface of the support substrate 1 is prepared.
  • the thickness direction (Y-axis direction) of the fin-like member 2 is parallel to the surface of the support substrate 1.
  • Both the support substrate 1 and the fin-like member 2 are formed of silicon single crystal.
  • the fin-like member 2 extends in a direction perpendicular to the paper surface (X-axis direction).
  • the fin-like member 2 has a thickness of about 40 nm and a height of about 400 nm.
  • the first insulating film 3 having a thickness of about lOnm is formed by thermally oxidizing the surfaces of the base substrate 1 and the fin-like member 2.
  • Silicon nitride (SiN) is deposited on the surface of the first insulating film 3 by chemical vapor deposition (CVD) to form a second insulating film 4 having a thickness of about 50 nm.
  • CVD chemical vapor deposition
  • a third insulating film 5 is formed on the second insulating film 4 by depositing silicon oxide by CVD.
  • the thickness of the third insulating film 5 is such that the upper surface of the third insulating film 5 is higher than the upper surface of the second insulating film 4 above the fin-like member 2 on the flat surface of the support substrate 1. It will be higher.
  • the surface layer portion of the third insulating film 5 is subjected to chemical mechanical polishing until the second insulating film 4 is exposed above the fin-like member 2.
  • the second insulating film 4 covering a part of the upper end side of the fin-like member 2 is etched using phosphoric acid. By this etching, a recess 8 is formed. A part on the upper end side of the fin-like member 2 protrudes from the bottom surface of the recess 8. This protruding portion is covered with the first insulating film 3.
  • the first insulating film 3 covering the protrusions of the fin-like member 2 is removed using a dilute hydrofluoric acid solution.
  • the surface layer portion of the third insulating film 5 is also thinly etched. As a result, a part of the upper end side of the fin-like member 2 is exposed in the recess 8.
  • the exposed surface layer of the fin-like member 2 is oxidized and oxidized.
  • a part of the upper end side of the fin-like member 2 is thinned to a thickness of, for example, 5 nm.
  • the thinned portion is referred to as a core member 2A
  • the non-thinned portion is referred to as a base member 2B.
  • SiGe is selectively epitaxially exposed on the silicon surface exposed in the recess 8, that is, on the side and upper end surfaces of the core member 2A and the upper surface of the base member 2B.
  • a first semiconductor film 10 having a thickness of 5 to: LOnm is formed.
  • the first semiconductor film 10 can be formed, for example, by thermal CVD using silane (SiH4) and germane (GeH4). Due to the difference in lattice constant between Si and SiGe, tensile strain is generated in the core member 2A made of Si, and compressive strain is generated in the first semiconductor film 10 made of SiGe.
  • the surface insulating layer 15 of the first semiconductor film 10 is thermally oxidized to form a gate insulating film 15 having a thickness of 1 nm.
  • the gate insulating film 15 is substantially formed of silicon oxide.
  • the core member 2A and the first semiconductor film 10 constitute a fin-like channel structure 11.
  • a polysilicon film 18A is deposited on the entire surface by CVD.
  • the polysilicon film 18 is filled in the recess 8.
  • FIG. 3A is a cross-sectional view taken along one-dot chain line A3-A3 in FIG.
  • a first semiconductor film 10, a gate insulating film 15, and a polysilicon film 18A are stacked on the upper surface of the core member 2A.
  • the gate electrode 18 made of polysilicon is formed.
  • the gate electrode 18 extends in the Y-axis direction.
  • a source region 20 and a drain region 21 are formed by ion-implanting a donor into the channel structure 11 on both sides thereof.
  • a stressor 25 having a silicon nitride force is formed so as to cover the upper and side surfaces of the gate electrode 18 and the surface of the gate insulating film 15 on both sides thereof.
  • the stressor 25 is formed, for example, by reduced pressure thermal CVD using SiH4, NH3, and N2 as source gases, under conditions of a pressure of 100 Pa and a growth temperature of 800 ° C.
  • the stressor 25 formed under this condition contains tensile stress. That is, the stressor 25 tends to shrink in the in-plane direction.
  • the tensile force is applied to the channel region below the gate electrode 18 in the channel structure 2A.
  • a force is applied.
  • the tensile strain generated in the core member 2A of the channel portion becomes larger and the compressive strain generated in the first semiconductor film 10 is relieved. Electron mobility can be increased by generating tensile strain in the surface layer portion of the core member 2A.
  • FIG. 4 shows an energy band diagram in the thickness direction from the core member 2 A to the gate electrode 18 of the fin-type MOSFET according to the first embodiment.
  • a SiGe film having a thickness less than the critical film thickness is epitaxially grown on the Si substrate, the energy levels at the lower end of the conduction band of the Si substrate and the lower end of the conduction band of the SiGe film are almost equal.
  • the compressive strain of the first semiconductor film 10 made of SiGe is relaxed, and tensile strain is generated in the core member 2A made of S.
  • the energy level Ec force at the lower end of the conduction band of the surface layer portion of the core member 2A is lower than the energy level Ec at the lower end of the conduction band of the first semiconductor film 10.
  • the mobility of electrons accumulated at the interface between Si and Si02 is 500cm2ZV, and the electrons accumulated at the interface between Si and Si02 that caused tensile strain.
  • a donor may be added to the first semiconductor film 10.
  • Electronic force generated in the conduction band of the first semiconductor film 10 is accumulated at the interface between the core member 2A and the first semiconductor film 10, and a normally-on type MOSFET is obtained.
  • conductivity is imparted to the source and drain regions by the electrons accumulated at the interface between the core member 2A and the first semiconductor layer 10, so that the ions are formed using the gate electrode 18 shown in FIG. 3C as a mask. There is no need for an injection.
  • the core member 2A is made of Si and the first semiconductor film 10 is made of SiGe. However, both of them can be made of SiGe.
  • the Ge composition ratio of the first semiconductor film 10 is made larger than the Ge composition ratio of the core member 2A, a step having the same energy level as in the first embodiment is formed at the interface between the two. can do.
  • FIGS. 5A and 5B the fin-type MOSFET according to the second embodiment will be described by focusing on the differences from the fin-type MOSFET according to the first embodiment.
  • FIG. 5A shows a cross-sectional view of the fin-type MOSFET according to the second embodiment.
  • the cross-sectional view shown in FIG. 5A corresponds to the cross-sectional view shown in FIG. 3D of the fin-type MOSFET according to the first embodiment.
  • the support substrate 1, the base member 2B, and the core member 2A are made of Si, and the first semiconductor film 10 is made of SiGe.
  • the support substrate 1, the base member 2B, and the core member 2A are made of SiGe, and the first semiconductor film 10 is made of Si.
  • compressive strain is generated in the core member 2A made of SiGe
  • tensile strain is generated in the first semiconductor film 10 made of Si.
  • the force in which tensile stress is inherent in the stressor 25 inherently has compressive stress.
  • the stressor 25 is formed by plasma-excited CVD, for example, using tetramethylsilane (4MS), NH3, and N2 as source gases, under conditions of a pressure of 500 Pa and a growth temperature of 400 ° C. By depositing SiN under these conditions, the stressor 25 in which compressive stress is inherent can be formed.
  • the stressor 25 tends to extend in the in-plane direction, compressive stress is applied to the channel region below the gate electrode 18 in the channel structure 2A. For this reason, the compressive strain generated in the core member 2A of the channel portion becomes larger, and the tensile strain generated in the first semiconductor film 10 is relaxed. By generating a compressive strain in the surface layer portion of the core member 2A, the hole mobility can be increased.
  • FIG. 5B shows an energy band diagram in the thickness direction from the core member 2 A to the gate electrode 18 of the fin-type MOSFET according to the second embodiment.
  • the energy level Ev at the upper end of the valence band of the core member 2A is higher than the energy level ⁇ at the upper end of the valence band of the first semiconductor film 10.
  • the mobility of holes accumulated at the interface between Si and Si02 is 150cm2ZV, and accumulation at the interface between Si and Si02 that caused bow I tension strain
  • An acceptor may be added to the first semiconductor film 10. Holes generated in the valence band of the first semiconductor film 10 are accumulated at the interface between the core member 2A and the first semiconductor film 10, and a normally-on type p-channel MOSFET is obtained. In this case, since conductivity is imparted to the source and drain regions by the holes accumulated at the interface between the core member 2A and the first semiconductor layer 10, the source and drain regions are formed after the gate electrode 18 is formed. It is not necessary to perform ion implantation to form the film! /.
  • the core member 2A is formed of SiGe and the first semiconductor film 10 is formed of Si.
  • both of them can be formed of SiGe.
  • a step having the same energy level as that of the second embodiment is formed at the interface therebetween. be able to.
  • the gate insulating film 15 that also has silicon oxide force is disposed between the first semiconductor film 10 and the gate electrode 18.
  • the gate electrode 18 may be brought into Schottky contact.
  • a Schottky contact can be obtained by forming the gate electrode 18 of platinum (Pt), titanium (Ti), aluminum (A1), or the like.
  • the first semiconductor film 10 and the gate electrode 18 are arranged on the side surface and the upper end surface of the core member 2A. Since the upper end face is extremely narrow compared to the side face, the channel formed on the upper end face has little effect on the operation of the MOSFET. Therefore, the semiconductor film 10 and the gate electrode 18 may be disposed only on the two side surfaces of the core member 2A.
  • the fin-type MOSFET according to the third embodiment will be described focusing on the differences from the fin-type MOSFET according to the first embodiment.
  • FIG. 6A is a sectional view of the channel structure 11 of the fin-type MOSFET according to the third embodiment.
  • the channel structure 11 is composed of the core member 2A and the first semiconductor film 10, but in the third embodiment, the first semiconductor film 10's On the surface, a second semiconductor film 12 having a thickness of about 5 nm and further comprising S is formed.
  • the gate insulating film 15 is formed on the surface of the second semiconductor film 12.
  • Other configurations are the same as those of the fin-type MOSFET according to the first embodiment.
  • FIG. 6B shows an energy band diagram in the thickness direction from the core member 2 A to the gate electrode 18.
  • electrons are accumulated at the interface C He between the core member 2A and the first semiconductor film 10, and an n-type channel is formed.
  • the second semiconductor film 12 is thin enough to exhibit the quantum effect, the ground quantum level of the conduction band is higher than the lower end of the conduction band of the core member 2A. Therefore, an n-type channel is formed preferentially at the interface CHe between the core member 2A and the first semiconductor film 10.
  • the energy level at the lower end of the valence band of the first semiconductor film 10 is higher than that of the second semiconductor film 12. For this reason, holes accumulate at the interface CHh between the two, forming a p-type channel.
  • the channel structure 11 by forming the channel structure 11 in a three-layer structure, if the source and drain regions are n-type, an n-channel fin-type MOSFET is realized, and the source and drain are formed. If the region is made p-type, a p-channel fin-type MOSFET can be realized. Therefore, it becomes possible to easily form a CMOS circuit.
  • a normal n-type MOSFET can be obtained by adding a donor to the first semiconductor film 10.
  • a normally-on type p-channel MOSFET can be obtained.
  • the core member 2A and the second semiconductor film 12 are formed of Si, and the first semiconductor film 10 is formed of SiGe. Also good. In this case, by making the Ge composition ratio of the first semiconductor film 10 larger than any Ge composition ratio of the core member 2A and the second semiconductor film 12, the same effect as the third embodiment is achieved. Can be obtained.
  • the core member 2A and the second semiconductor film 12 may be formed of Ge or SiGe, and the first semiconductor film 10 may be formed of S or SiGe.
  • the Ge composition ratio of the first semiconductor film 10 be smaller than the Ge composition ratio of any of the core member 2A and the second semiconductor film 12.
  • the valence band holes are accumulated at the interface between the core member 2A and the first semiconductor film 10 as in the case shown in FIG. 5B, and a p-type channel is formed.
  • the In the conduction band electrons accumulate at the interface between the first semiconductor film 10 and the second semiconductor film 12 to form an n-type channel.
  • an n-type channel is formed at the interface between the first semiconductor film 10 and the gate insulating film 15.
  • the n-type channel is formed in a region deeper than the interface between the semiconductor and the gate insulating film 15. The effect of increasing the mobility of electrons can be expected.
  • the gate insulating film 15 having a silicon oxide force is disposed between the second semiconductor film 12 and the gate electrode 18.
  • the gate electrode 18 is provided on the second semiconductor film 12.
  • Schottky contact may be used.
  • a Schottky contact can be obtained by forming the gate electrode 18 of platinum (Pt), titanium (Ti), aluminum (A1), or the like.
  • silicon nitride is used as the stressor 25, but other materials capable of containing compressive stress or tensile stress may be used.
  • a compressive stress is inherent in a titanium nitride (TiN) film or a carbon (C) film deposited by sputtering.
  • the support substrate 1, the base member 2B, and the core member 2A are formed from one silicon substrate cover.
  • a substrate made of a material may be used.
  • the base member 2B and the core member 2A can be formed by patterning a semiconductor film formed on an insulating substrate.
  • a preferable film thickness of the stressor 25 and a preferable cross-sectional shape of the gate electrode 18 will be described with reference to FIG. 3D.
  • the preferred dimensions described below also apply to the second and third implementations.
  • the thickness T2 of the stressor 25 is set to be not less than 5 times the distance T3 from the top surface of the core member 2A to the bottom surface of the stressor 25. Is preferred.
  • the stressor 25 deposited above the gate electrode 18 also has a tensile or compressive stress.
  • the stress in this part This affects the region and relaxes the distortion of the channel region.
  • the bottom force of the stressor 25 disposed on both sides of the gate electrode 18 is also set to the height T1 up to the bottom surface of the stressor 25 disposed on the gate electrode 18. It is preferable to be at least 1 times the dimension L in the X-axis direction of 18.
  • the stress applied to the channel region is 2 GPa or more.
  • the stress generated at the interface between the Si layer and the SiO.8GeO.2 layer is about 2 GPa.
  • the stress generated in the entire Si layer is about 2 GPa.

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Abstract

A channel structure is formed on a supporting substrate. The channel structure is arranged in a posture where a thickness direction is parallel to the surface of the supporting substrate. The channel structure is composed of a fin-like core member formed of a semiconductor material, and a semiconductor material different from that of the core member, and includes a first semiconductor film for covering two side planes of the core member. Gate electrodes are arranged on both sides of a region within the channel structure. The gate electrodes are brought into Schottky-contact with the side planes of the channel structure, or face the side planes of the channel structure through gate insulating films. In the channel structure, on the both sides of the region sandwiched with the gate electrodes, source and drain regions are formed. The core member in the region sandwiched with the gate electrodes has distortion.

Description

フィン型半導体装置及びその製造方法  Fin-type semiconductor device and manufacturing method thereof
技術分野  Technical field
[0001] 本発明は、フィン型半導体装置及びその製造方法に関し、特にフィン状部分を挟 むようにゲート電極を配したフィン型半導体装置及びその製造方法に関する。  The present invention relates to a fin-type semiconductor device and a method for manufacturing the same, and more particularly to a fin-type semiconductor device in which a gate electrode is disposed so as to sandwich a fin-shaped portion and a method for manufacturing the same.
背景技術  Background art
[0002] 下記非特許文献 1及び 2に、フィン型 MOSFETが開示されている。フィン型 MOS FETにおいては、基板面からほぼ垂直方向に突出したフィン型の半導体部分をチヤ ネルとして用い、その両側にゲート電極が配置される。チャネルの電位がその両側か ら制御されるため、ショートチャネル効果を低減することができる。  Non-Patent Documents 1 and 2 below disclose fin-type MOSFETs. In a fin-type MOS FET, a fin-type semiconductor portion protruding almost vertically from the substrate surface is used as a channel, and gate electrodes are arranged on both sides thereof. Since the channel potential is controlled from both sides, the short channel effect can be reduced.
[0003] 下記の特許文献 1に、歪を持たな 、半導体材料力もなるシードフィンの表面上に、 歪チャネル層を形成したフィン型 MOSFETが開示されて ヽる。チャネル層に歪を持 たせることにより、キャリアの移動度を高めることができる。  Patent Document 1 below discloses a fin-type MOSFET in which a strained channel layer is formed on the surface of a seed fin that has no strain and also has a semiconductor material force. Carrier mobility can be increased by imparting strain to the channel layer.
[0004] 特許文献 1 :特開 2005— 19970号公報  [0004] Patent Document 1: JP 2005-19970
非特干文献 1 : Sang- YunKim et ai., Hot Carrier-Induced Degradation in BulkFinFE Ts", IEEEElectron Device Letters, Vol. 26, No.8, p.566— p.568 (2005)  Non-Patent Literature 1: Sang- YunKim et ai., Hot Carrier-Induced Degradation in BulkFinFE Ts ", IEEE Electron Device Letters, Vol. 26, No.8, p.566—p.568 (2005)
非特許文献 2 : Taト SuPark et al., "Characteristics of Body-Tied Triple- GatepMOSF ETs", IEEEElectron Device Letters, Vol.25, No.12, p.798— p.800 (2004)  Non-Patent Document 2: Ta et SuPark et al., "Characteristics of Body-Tied Triple-GatepMOSF ETs", IEEE Electron Device Letters, Vol.25, No.12, p.798—p.800 (2004)
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0005] フィン型 MOSFETの動作速度をより高める技術が望まれている。本発明の目的は 、動作速度を高めることができるフィン型半導体装置及びその製造方法を提供するこ とである。 [0005] A technique for further increasing the operation speed of the fin-type MOSFET is desired. An object of the present invention is to provide a fin-type semiconductor device capable of increasing the operating speed and a method for manufacturing the same.
課題を解決するための手段  Means for solving the problem
[0006] 本発明の一観点によると、支持基板の上に、厚さ方向が該支持基板の表面と平行 な姿勢で配置され、半導体材料で形成されたフィン状のコア部材、及び該コア部材と は異なる半導体材料力 なり、該コア部材の 2つの側面を覆う第 1の半導体膜を含む チャネル構造体と、前記チャネル構造体の一部の領域の両側に配置され、該チヤネ ル構造体の側面にショットキ接触する力、または該チャネル構造体の側面にゲート絶 縁膜を介して対向するゲート電極と、前記チャネル構造体のうち、前記ゲート電極に 挟まれた領域の両側に形成されたソース及びドレイン領域とを有し、前記ゲート電極 で挟まれた領域の前記コア部材が歪を有するフィン型半導体装置が提供される。 [0006] According to one aspect of the present invention, a fin-shaped core member is formed on a support substrate in a posture in which the thickness direction is parallel to the surface of the support substrate and is formed of a semiconductor material, and the core member A semiconductor material force different from that of the first semiconductor film covering the two side surfaces of the core member. Disposed on both sides of the channel structure and a part of the channel structure, facing the side surface of the channel structure, or facing the side surface of the channel structure through a gate insulating film A source electrode and a drain region formed on both sides of a region sandwiched between the gate electrodes of the channel structure, and the core member in the region sandwiched between the gate electrodes has a strain. A fin-type semiconductor device is provided.
[0007] 本発明の他の観点によると、支持基板の表面上に、厚さ方向が該支持基板の表面 と平行になる姿勢で配置された半導体材料力 なるフィン状部材を有する下地構造 体を準備する工程と、前記下地構造体の上に、前記フィン状部材を埋め込むように 絶縁膜を形成する工程と、前記フィン状部材の上端の一部分が現れるように、前記 絶縁膜に凹部を形成する工程と、前記凹部内に現れた前記フィン状部材の一部分 の表層部を除去することにより、該フィン状部材の上端の一部分を薄くしたコア部材 を形成する工程と、前記コア部材の表面上に、該コア部材とは異なる半導体材料で 形成された第 1の半導体膜を形成する工程と、前記コア部材及び前記第 1の半導体 膜を含むチャネル構造体の一部分の両側にゲート電極を形成する工程とを有するフ イン型半導体装置の製造方法が提供される。  [0007] According to another aspect of the present invention, there is provided an underlying structure having a fin-like member having a semiconductor material force disposed on a surface of a support substrate in a posture in which a thickness direction is parallel to the surface of the support substrate. A step of preparing, a step of forming an insulating film so as to embed the fin-shaped member on the base structure, and a recess formed in the insulating film so that a part of the upper end of the fin-shaped member appears. Forming a core member in which a part of the upper end of the fin-like member is thinned by removing a surface layer portion of a part of the fin-like member appearing in the recess; and on the surface of the core member Forming a first semiconductor film formed of a semiconductor material different from the core member; and forming gate electrodes on both sides of a part of the channel structure including the core member and the first semiconductor film. And have Method for producing a full-in type semiconductor device is provided that.
発明の効果  The invention's effect
[0008] コア部材が歪を有することにより、コア部材と第 1の半導体膜との界面に蓄積される キャリアの移動度を高めることができる。コア部材と第 1の半導体膜との界面にチヤネ ルを形成すると、半導体とゲート絶縁膜との界面界面の粗さや界面準位の影響を受 けなくなる。これにより、キャリアの移動度を高めることができる。  [0008] Since the core member is distorted, the mobility of carriers accumulated at the interface between the core member and the first semiconductor film can be increased. When a channel is formed at the interface between the core member and the first semiconductor film, it is not affected by the roughness or interface state of the interface between the semiconductor and the gate insulating film. Thereby, the mobility of a carrier can be raised.
[0009] 凹部内に現れたフィン状部材の一部分を薄くすることにより、半導体装置の特性を 高めることができる。  [0009] The characteristics of the semiconductor device can be improved by thinning a part of the fin-like member appearing in the recess.
図面の簡単な説明  Brief Description of Drawings
[0010] [図 1]図 1は、第 1の実施例によるフィン型 MOSFETの斜視図である。 [0010] FIG. 1 is a perspective view of a fin-type MOSFET according to a first embodiment.
[図 2-1]図 2A及び図 2Bは、第 1の実施例によるフィン型 MOSFETの製造途中にお ける装置の断面図である。  [FIG. 2-1] FIGS. 2A and 2B are cross-sectional views of an apparatus in the course of manufacturing a fin-type MOSFET according to the first embodiment.
[図 2-2]図 2C及び図 2Dは、第 1の実施例によるフィン型 MOSFETの製造途中にお ける装置の断面図である。 [図 2-3]図 2E及び図 2Fは、第 1の実施例によるフィン型 MOSFETの製造途中にお ける装置の断面図である。 [FIG. 2-2] FIGS. 2C and 2D are cross-sectional views of the apparatus in the course of manufacturing the fin-type MOSFET according to the first embodiment. [FIGS. 2-3] FIGS. 2E and 2F are cross-sectional views of the apparatus in the course of manufacturing the fin-type MOSFET according to the first embodiment.
[図 2-4]図 2G及び図 2Hは、第 1の実施例によるフィン型 MOSFETの製造途中にお ける装置の断面図である。  [FIG. 2-4] FIGS. 2G and 2H are cross-sectional views of the device in the process of manufacturing the fin-type MOSFET according to the first embodiment.
[図 2-5]図 21は、第 1の実施例によるフィン型 MOSFETの製造途中における装置の 断面図である。  [FIG. 2-5] FIG. 21 is a cross-sectional view of the device in the middle of manufacturing the fin-type MOSFET according to the first embodiment.
[図 3-1]図 3A及び図 3Bは、第 1の実施例によるフィン型 MOSFETの製造途中にお ける装置の断面図である。  [FIG. 3-1] FIGS. 3A and 3B are cross-sectional views of a device in the process of manufacturing a fin-type MOSFET according to the first embodiment.
[図 3-2]図 3C及び図 3Dは、第 1の実施例によるフィン型 MOSFETの製造途中にお ける装置の断面図である。  [FIG. 3-2] FIGS. 3C and 3D are cross-sectional views of the device in the process of manufacturing the fin-type MOSFET according to the first embodiment.
[図 4]図 4は、第 1の実施例によるフィン型 MOSFETのエネルギバンド図である。  FIG. 4 is an energy band diagram of the fin-type MOSFET according to the first embodiment.
[図 5]図 5Aは、第 2の実施例によるフィン型 MOSFETの断面図であり、図 5Bは、そ のエネノレギバンド図である。  FIG. 5A is a cross-sectional view of a fin-type MOSFET according to a second embodiment, and FIG. 5B is its energy band diagram.
[図 6]図 6Aは、第 3の実施例によるフィン型 MOSFETのフィン状部分の断面図であ り、図 6Bは、そのエネノレギバンド図である。  FIG. 6A is a cross-sectional view of a fin-shaped portion of a fin-type MOSFET according to a third embodiment, and FIG. 6B is an energy band diagram.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0011] 図 1に、第 1の実施例によるフィン型 MOSFETの斜視図を示す。支持基板 1の表 面からほぼ垂直方向に、フィン状のベース部材 2Bが突出している。支持基板 1の表 面を XY面とし、ベース部材 2Bの側面に平行な面を ZX面とする XYZ直交座標系を 定義する。ベース部材 2Bの長さ方向が X軸に平行になり、ベース部材 2Bの厚さ方向 が Y軸に平行になる。 FIG. 1 shows a perspective view of a fin-type MOSFET according to the first embodiment. A fin-like base member 2B protrudes from the surface of the support substrate 1 in a substantially vertical direction. Define an XYZ Cartesian coordinate system in which the surface of the support substrate 1 is the XY plane and the plane parallel to the side surface of the base member 2B is the ZX plane. The length direction of the base member 2B is parallel to the X axis, and the thickness direction of the base member 2B is parallel to the Y axis.
[0012] ベース部材 2Bの上面から Z軸方向に、フィン状のコア部材 2Aが突出して!/、る。コア 部材 2Aの側面も ZX面に平行であり、コア部材 2Aの厚さはベース部材 2Bよりも薄 ヽ 。支持基板 1、ベース部材 2B、及びコア部材 2Aは、シリコン (Si)単結晶で形成され ている。一例として、ベース部材 2Bの厚さは 40nmであり、その高さは 260nmである 。コア部材 2Aの厚さは 5nmであり、その高さは 130nmである。  [0012] The fin-shaped core member 2A protrudes in the Z-axis direction from the upper surface of the base member 2B. The side surface of the core member 2A is also parallel to the ZX plane, and the thickness of the core member 2A is thinner than that of the base member 2B. The support substrate 1, the base member 2B, and the core member 2A are formed of silicon (Si) single crystal. As an example, the base member 2B has a thickness of 40 nm and a height of 260 nm. The core member 2A has a thickness of 5 nm and a height of 130 nm.
[0013] 酸ィ匕シリコン力もなる第 1の絶縁膜 3が、支持基板 1の上面及びベース部材 2Bの側 面を、下地表面に沿うように覆う。第 1の絶縁膜 3の厚さは、例えば 10nmである。窒 化シリコン力もなる第 2の絶縁膜 4が、第 1の絶縁膜 3の表面を、下地表面に沿うように 覆う。第 2の絶縁膜 4の厚さは、例えば 50nmである。第 2の絶縁膜 4の平坦面上に、 酸ィ匕シリコン力もなる第 3の絶縁膜 5が配置されている。ベース部材 2Bの側面上の第 1及び第 2の絶縁膜 3及び 4の上側の端面は、第 3の絶縁膜 5で覆われていない。第 3の絶縁膜 5の上面は、第 1及び第 2の絶縁膜 3及び 4の上側の端面よりも上方に位 置し、コア部材 2Aの上面よりもやや高い位置に配置される。このため、第 1及び第 2 の絶縁膜 3及び 4の上側の端面を底面の一部とし、第 3の絶縁膜 5が側面に露出した 凹部 8が画定される。凹部 8の底面力 コア部材 2Aが上方に突出して 、る。 [0013] The first insulating film 3 also having an oxide silicon force covers the upper surface of the support substrate 1 and the side surface of the base member 2B so as to be along the base surface. The thickness of the first insulating film 3 is, for example, 10 nm. Nitro The second insulating film 4 that also has siliconizing power covers the surface of the first insulating film 3 along the base surface. The thickness of the second insulating film 4 is, for example, 50 nm. On the flat surface of the second insulating film 4, a third insulating film 5 having an oxide silicon force is disposed. The upper end surfaces of the first and second insulating films 3 and 4 on the side surface of the base member 2B are not covered with the third insulating film 5. The upper surface of the third insulating film 5 is positioned higher than the upper end surfaces of the first and second insulating films 3 and 4, and is positioned slightly higher than the upper surface of the core member 2A. For this reason, the upper end surfaces of the first and second insulating films 3 and 4 are defined as a part of the bottom surface, and a recess 8 in which the third insulating film 5 is exposed on the side surface is defined. The bottom force of the recess 8 The core member 2A protrudes upward.
[0014] コア部材 2Aの側面及び上側の端面が、 SiGeからなる第 1の半導体膜 10で覆われ ている。第 1の半導体膜 10は、コア部材 2Aの表面上にェピタキシャル成長されてお り、その厚さは、例えば 5〜： LOnmである。 Siと SiGeとの格子定数の違いにより、第 1 の半導体膜 10の成膜直後に、コア部材 2Aに引張歪が生じ、第 1の半導体膜 10に圧 縮歪が生じる。コア部材 2Aと第 1の半導体膜 10とで構成されるフィン状の構造体を、 チャネル構造体 11と呼ぶこととする。チャネル構造体 11の表面力 酸ィ匕シリコンから なるゲート絶縁膜 15で覆われている。ゲート絶縁膜 15の厚さは、例えば lnmである [0014] The side surface and the upper end surface of the core member 2A are covered with a first semiconductor film 10 made of SiGe. The first semiconductor film 10 is epitaxially grown on the surface of the core member 2A, and the thickness thereof is, for example, 5 to: LOnm. Due to the difference in lattice constant between Si and SiGe, a tensile strain is generated in the core member 2A immediately after the first semiconductor film 10 is formed, and a compressive strain is generated in the first semiconductor film 10. A fin-like structure including the core member 2A and the first semiconductor film 10 is referred to as a channel structure 11. The surface force of the channel structure 11 is covered with a gate insulating film 15 made of silicon oxide. The thickness of the gate insulating film 15 is, for example, lnm
[0015] X軸方向に長いチャネル構造体 11を横切るように、第 3の絶縁膜 5の上に、 Y軸方 向に長いゲート電極 18が形成されている。ゲート電極 18は、例えばポリシリコンで形 成される。ゲート電極 18は、凹部 8と重なる領域において、凹部 8の底面まで達すると 共に、ゲート絶縁膜 15を介してチャネル構造体 11の上面及び側面に対向する。 A gate electrode 18 that is long in the Y-axis direction is formed on the third insulating film 5 so as to cross the channel structure 11 that is long in the X-axis direction. The gate electrode 18 is made of, for example, polysilicon. The gate electrode 18 reaches the bottom surface of the recess 8 in a region overlapping with the recess 8, and faces the upper surface and side surface of the channel structure 11 through the gate insulating film 15.
[0016] チャネル構造体 11のうち、ゲート電極 18の両側に位置する領域にドナーが添加さ れており、この部分がソース領域 20及びドレイン領域 21となる。  In the channel structure 11, donors are added to regions located on both sides of the gate electrode 18, and these portions become the source region 20 and the drain region 21.
[0017] 第 1〜第 3の絶縁膜 3、 4、 5、及びゲート絶縁膜 15の表面のうち、ゲート電極 18の 側面に連続する領域、及びゲート電極 18の表面を覆うように、窒化シリコン (SiN)か らなるストレッサ 25が形成されて 、る。  Among the surfaces of the first to third insulating films 3, 4, 5 and the gate insulating film 15, a silicon nitride is formed so as to cover a region continuing to the side surface of the gate electrode 18 and the surface of the gate electrode 18. A stressor 25 made of (SiN) is formed.
[0018] 図 2A〜図 21、図 3A〜図 3Dを参照して、第 1の実施例によるフィン型半導体装置 の製造方法について説明する。図 2A〜図 21は、図 1に示した斜視図の、ゲート電極 18とコア部材 2Aとの交差箇所を通過する YZ面に平行な断面に対応し、図 3 A〜図 3Dは、 ZX面に平行な断面に対応する。 With reference to FIGS. 2A to 21 and FIGS. 3A to 3D, a method of manufacturing the fin-type semiconductor device according to the first embodiment will be described. 2A to 21 correspond to a cross section parallel to the YZ plane passing through the intersection of the gate electrode 18 and the core member 2A in the perspective view shown in FIG. 3D corresponds to a cross section parallel to the ZX plane.
[0019] 図 2Aに示すように、支持基板 1の表面から、フィン状部材 2がほぼ垂直方向に突出 した下地構造体を準備する。フィン状部材 2の厚さ方向 (Y軸方向）は、支持基板 1の 表面と平行になる。支持基板 1及びフィン状部材 2は、共にシリコン単結晶で形成さ れる。フィン状部材 2は、紙面に垂直な方向（X軸方向）に延在する。例えば、フィン 状部材 2の厚さは約 40nm、高さは約 400nmとする。  As shown in FIG. 2A, a base structure in which the fin-like member 2 protrudes in a substantially vertical direction from the surface of the support substrate 1 is prepared. The thickness direction (Y-axis direction) of the fin-like member 2 is parallel to the surface of the support substrate 1. Both the support substrate 1 and the fin-like member 2 are formed of silicon single crystal. The fin-like member 2 extends in a direction perpendicular to the paper surface (X-axis direction). For example, the fin-like member 2 has a thickness of about 40 nm and a height of about 400 nm.
[0020] 以下、下地構造体の形成方法について説明する。シリコン基板の表面の一部をマ スクして表層部をエッチングし、フィン状部材 2を残す。エッチング直後のフィン状部 材 2の厚さは、 40nmよりも厚い。シリコン基板の表面を熱酸ィ匕して酸ィ匕シリコン膜を 形成し、この酸ィ匕シリコン膜をエッチングすることにより、フィン状部材 2を厚さ 40nm まで薄くする。  [0020] Hereinafter, a method for forming a base structure will be described. Mask the surface of the silicon substrate to etch the surface layer, leaving the fin-like member 2. The thickness of the fin-like member 2 immediately after etching is thicker than 40 nm. The surface of the silicon substrate is thermally oxidized to form an oxide silicon film, and the oxide silicon film is etched to thin the fin-like member 2 to a thickness of 40 nm.
[0021] 図 2Bに示すように、下地基板 1及びフィン状部材 2の表面を熱酸化することにより、 厚さ約 lOnmの第 1の絶縁膜 3を形成する。第 1の絶縁膜 3の表面上に、化学気相成 長（CVD)により窒化シリコン (SiN)を堆積させ、厚さ約 50nmの第 2の絶縁膜 4を形 成する。次に、第 2の絶縁膜 4の上に、 CVDにより酸ィ匕シリコンを堆積させることにより 、第 3の絶縁膜 5を形成する。第 3の絶縁膜 5の厚さは、支持基板 1の平坦面上にお いて、第 3の絶縁膜 5の上面が、フィン状部材 2の上方における第 2の絶縁膜 4の上 面よりも高くなる程度とする。  As shown in FIG. 2B, the first insulating film 3 having a thickness of about lOnm is formed by thermally oxidizing the surfaces of the base substrate 1 and the fin-like member 2. Silicon nitride (SiN) is deposited on the surface of the first insulating film 3 by chemical vapor deposition (CVD) to form a second insulating film 4 having a thickness of about 50 nm. Next, a third insulating film 5 is formed on the second insulating film 4 by depositing silicon oxide by CVD. The thickness of the third insulating film 5 is such that the upper surface of the third insulating film 5 is higher than the upper surface of the second insulating film 4 above the fin-like member 2 on the flat surface of the support substrate 1. It will be higher.
[0022] 図 2Cに示すように、フィン状部材 2の上方にぉ 、て第 2の絶縁膜 4が露出するまで 、第 3の絶縁膜 5の表層部を化学機械研磨する。  As shown in FIG. 2C, the surface layer portion of the third insulating film 5 is subjected to chemical mechanical polishing until the second insulating film 4 is exposed above the fin-like member 2.
[0023] 図 2Dに示すように、フィン状部材 2の上端側の一部分を覆う第 2の絶縁膜 4を、燐 酸を用いてエッチングする。このエッチングにより、凹部 8が形成される。凹部 8の底 面から、フィン状部材 2の上端側の一部が突出する。この突出部分は、第 1の絶縁膜 3で覆われている。  As shown in FIG. 2D, the second insulating film 4 covering a part of the upper end side of the fin-like member 2 is etched using phosphoric acid. By this etching, a recess 8 is formed. A part on the upper end side of the fin-like member 2 protrudes from the bottom surface of the recess 8. This protruding portion is covered with the first insulating film 3.
[0024] 図 2Eに示すように、フィン状部材 2の突出部を覆う第 1の絶縁膜 3を、希フッ酸溶液 を用いて除去する。このとき、第 3の絶縁膜 5の表層部も薄くエッチングされる。これに より、凹部 8内に、フィン状部材 2の上端側の一部が露出する。  As shown in FIG. 2E, the first insulating film 3 covering the protrusions of the fin-like member 2 is removed using a dilute hydrofluoric acid solution. At this time, the surface layer portion of the third insulating film 5 is also thinly etched. As a result, a part of the upper end side of the fin-like member 2 is exposed in the recess 8.
[0025] 図 2Fに示すように、フィン状部材 2の露出した部分の表層部の酸化、及び酸化によ り形成された酸ィ匕シリコン膜のエッチングを行うことにより、フィン状部材 2の上端側の 一部を、例えば厚さ 5nmまで薄層化する。フィン状部材 2のうち、薄層化された部分 をコア部材 2Aと呼び、薄層化されていない部分を、ベース部材 2Bと呼ぶこととする。 [0025] As shown in FIG. 2F, the exposed surface layer of the fin-like member 2 is oxidized and oxidized. By etching the silicon oxide film thus formed, a part of the upper end side of the fin-like member 2 is thinned to a thickness of, for example, 5 nm. Of the fin-like member 2, the thinned portion is referred to as a core member 2A, and the non-thinned portion is referred to as a base member 2B.
[0026] 図 2Gに示すように、凹部 8内に露出しているシリコン表面、すなわちコア部材 2Aの 側面と上側の端面、及びベース部材 2Bの上面の上に、 SiGeを選択的にェピタキシ ャル成長させることにより、厚さ 5〜： LOnmの第 1の半導体膜 10を形成する。第 1の半 導体膜 10は、例えばシラン (SiH4)とゲルマン (GeH4)とを用いた熱 CVDにより形 成することができる。 Siと SiGeとの格子定数の相違により、 Siからなるコア部材 2Aに 引張歪が生じ、 SiGeからなる第 1の半導体膜 10に圧縮歪が生じる。  [0026] As shown in FIG. 2G, SiGe is selectively epitaxially exposed on the silicon surface exposed in the recess 8, that is, on the side and upper end surfaces of the core member 2A and the upper surface of the base member 2B. By growing, a first semiconductor film 10 having a thickness of 5 to: LOnm is formed. The first semiconductor film 10 can be formed, for example, by thermal CVD using silane (SiH4) and germane (GeH4). Due to the difference in lattice constant between Si and SiGe, tensile strain is generated in the core member 2A made of Si, and compressive strain is generated in the first semiconductor film 10 made of SiGe.
[0027] 図 2Hに示すように、第 1の半導体膜 10の表層部を熱酸ィ匕することにより、厚さ lnm のゲート絶縁膜 15を形成する。ゲート絶縁膜 15は、実質的に酸化シリコンで形成さ れることになる。コア部材 2Aと第 1の半導体膜 10とにより、フィン状のチャネル構造体 11が構成される。  As shown in FIG. 2H, the surface insulating layer 15 of the first semiconductor film 10 is thermally oxidized to form a gate insulating film 15 having a thickness of 1 nm. The gate insulating film 15 is substantially formed of silicon oxide. The core member 2A and the first semiconductor film 10 constitute a fin-like channel structure 11.
[0028] 図 21に示すように、全面にポリシリコン膜 18Aを、 CVDにより堆積させる。ポリシリコ ン膜 18は、凹部 8内に充填される。  As shown in FIG. 21, a polysilicon film 18A is deposited on the entire surface by CVD. The polysilicon film 18 is filled in the recess 8.
[0029] 図 3Aに、図 21の一点鎖線 A3— A3における断面図を示す。コア部材 2Aの上面の 上に、第 1の半導体膜 10、ゲート絶縁膜 15、及びポリシリコン膜 18Aが積層されてい る。 FIG. 3A is a cross-sectional view taken along one-dot chain line A3-A3 in FIG. A first semiconductor film 10, a gate insulating film 15, and a polysilicon film 18A are stacked on the upper surface of the core member 2A.
[0030] 図 3Bに示すように、ポリシリコン膜 18Aをパターユングすることにより、ポリシリコンか らなるゲート電極 18を形成する。ゲート電極 18は、 Y軸方向に延在する。  As shown in FIG. 3B, by patterning the polysilicon film 18A, the gate electrode 18 made of polysilicon is formed. The gate electrode 18 extends in the Y-axis direction.
[0031] 図 3Cに示すように、ゲート電極 18をマスクとして、その両側のチャネル構造体 11に 、ドナーをイオン注入することにより、ソース領域 20及びドレイン領域 21を形成する。  As shown in FIG. 3C, using the gate electrode 18 as a mask, a source region 20 and a drain region 21 are formed by ion-implanting a donor into the channel structure 11 on both sides thereof.
[0032] 図 3Dに示すように、ゲート電極 18の上面と側面、及びその両側のゲート絶縁膜 15 の表面を覆うように、窒化シリコン力もなるストレッサ 25を形成する。ストレッサ 25は、 例えば原料ガスとして SiH4、 NH3、及び N2を用い、圧力 100Pa、成長温度 800°C の条件で、減圧熱 CVDにより形成する。この条件で形成されたストレッサ 25には、引 張応力が内在する。すなわち、ストレッサ 25は面内方向に縮もうとする。  As shown in FIG. 3D, a stressor 25 having a silicon nitride force is formed so as to cover the upper and side surfaces of the gate electrode 18 and the surface of the gate insulating film 15 on both sides thereof. The stressor 25 is formed, for example, by reduced pressure thermal CVD using SiH4, NH3, and N2 as source gases, under conditions of a pressure of 100 Pa and a growth temperature of 800 ° C. The stressor 25 formed under this condition contains tensile stress. That is, the stressor 25 tends to shrink in the in-plane direction.
[0033] このため、チャネル構造体 2Aのうちゲート電極 18の下方のチャネル領域に引張応 力が印加される。チャネル部のコア部材 2Aに生じていた引張歪がより大きくなるとと もに、第 1の半導体膜 10に生じていた圧縮歪が緩和される。コア部材 2Aの表層部に 引張歪を生じさせることにより、電子の移動度を高めることができる。 [0033] For this reason, the tensile force is applied to the channel region below the gate electrode 18 in the channel structure 2A. A force is applied. The tensile strain generated in the core member 2A of the channel portion becomes larger and the compressive strain generated in the first semiconductor film 10 is relieved. Electron mobility can be increased by generating tensile strain in the surface layer portion of the core member 2A.
[0034] 図 4に、第 1の実施例によるフィン型 MOSFETのコア部材 2Aからゲート電極 18ま での厚さ方向に関するエネルギバンド図を示す。 Si基板上に、臨界膜厚以下の厚さ の SiGe膜をェピタキシャル成長させた場合、 Si基板の伝導帯下端と、 SiGe膜の伝 導帯下端とのエネルギレベルはほぼ等しくなる。ところが、第 1の実施例の場合には、 SiGeからなる第 1の半導体膜 10の圧縮歪が緩和され、 S なるコア部材 2Aに引 張歪が生じる。これにより、コア部材 2Aの表層部の伝導帯下端のエネルギレベル Ec 力 第 1の半導体膜 10の伝導帯下端のエネルギレベル Ecよりも低くなる。  FIG. 4 shows an energy band diagram in the thickness direction from the core member 2 A to the gate electrode 18 of the fin-type MOSFET according to the first embodiment. When a SiGe film having a thickness less than the critical film thickness is epitaxially grown on the Si substrate, the energy levels at the lower end of the conduction band of the Si substrate and the lower end of the conduction band of the SiGe film are almost equal. However, in the case of the first embodiment, the compressive strain of the first semiconductor film 10 made of SiGe is relaxed, and tensile strain is generated in the core member 2A made of S. Thereby, the energy level Ec force at the lower end of the conduction band of the surface layer portion of the core member 2A is lower than the energy level Ec at the lower end of the conduction band of the first semiconductor film 10.
[0035] ゲート電極 18に正電圧を印加すると、コア部材 2と第 1の半導体膜 10との界面 CH eに電子が蓄積されチャネルが形成される。このように、ゲート絶縁膜 15と第 1の半導 体膜 10との界面よりも深い領域に、チャネルが形成される。チャネル内を移動する電 子が、ゲート絶縁膜 15と第 1の半導体膜 10との界面の粗さや界面準位の影響を受 けないため、電子の移動度の向上が期待できる。  When a positive voltage is applied to the gate electrode 18, electrons are accumulated at the interface CH e between the core member 2 and the first semiconductor film 10 to form a channel. Thus, a channel is formed in a region deeper than the interface between the gate insulating film 15 and the first semiconductor film 10. Since electrons moving in the channel are not affected by the roughness or interface state of the interface between the gate insulating film 15 and the first semiconductor film 10, an improvement in electron mobility can be expected.
[0036] 例えば、本願発明者の評価実験によると、 Siと Si02との界面に蓄積された電子の 移動度が 500cm2ZVであり、引張歪を生じさせた Siと Si02との界面に蓄積された 電子の移動度が 700cm2ZVであるのに対し、引張歪を生じさせた Siと SiGeとの界 面に蓄積された電子の移動度は、 2600〜3000cm2ZVであった。  [0036] For example, according to the evaluation experiment of the present inventor, the mobility of electrons accumulated at the interface between Si and Si02 is 500cm2ZV, and the electrons accumulated at the interface between Si and Si02 that caused tensile strain. The mobility of electrons accumulated at the interface between Si and SiGe, which caused tensile strain, was 2600-3000 cm2ZV.
[0037] 第 1の半導体膜 10にドナーを添加しておいてもよい。第 1の半導体膜 10の伝導帯 内に発生した電子力 コア部材 2Aと第 1の半導体膜 10との界面に蓄積され、ノーマ リオン型の MOSFETが得られる。この場合、コア部材 2Aと第 1の半導体層 10との界 面に蓄積された電子によって、ソース及びドレイン領域に導電性が付与されるため、 図 3Cに示したゲート電極 18をマスクとしたイオン注入を行う必要はない。  [0037] A donor may be added to the first semiconductor film 10. Electronic force generated in the conduction band of the first semiconductor film 10 is accumulated at the interface between the core member 2A and the first semiconductor film 10, and a normally-on type MOSFET is obtained. In this case, conductivity is imparted to the source and drain regions by the electrons accumulated at the interface between the core member 2A and the first semiconductor layer 10, so that the ions are formed using the gate electrode 18 shown in FIG. 3C as a mask. There is no need for an injection.
[0038] 上記第 1の実施例では、コア部材 2Aを Siで形成し、第 1の半導体膜 10を SiGeで 形成したが、両者を SiGeで形成することも可能である。この場合、第 1の半導体膜 10 の Geの組成比を、コア部材 2Aの Geの組成比よりも大きくすることにより、両者の界面 に、第 1の実施例と同様のエネルギレベルの段差を形成することができる。 [0039] 次に、図 5A及び図 5Bを参照して、第 2の実施例によるフィン型 MOSFETについ て、第 1の実施例によるフィン型 MOSFETとの相違点に着目して説明する。 In the first embodiment, the core member 2A is made of Si and the first semiconductor film 10 is made of SiGe. However, both of them can be made of SiGe. In this case, by making the Ge composition ratio of the first semiconductor film 10 larger than the Ge composition ratio of the core member 2A, a step having the same energy level as in the first embodiment is formed at the interface between the two. can do. Next, with reference to FIGS. 5A and 5B, the fin-type MOSFET according to the second embodiment will be described by focusing on the differences from the fin-type MOSFET according to the first embodiment.
[0040] 図 5Aに、第 2の実施例によるフィン型 MOSFETの断面図を示す。図 5Aに示した 断面図は、第 1の実施例によるフィン型 MOSFETの図 3Dに示した断面図に対応す る。第 1の実施例では、支持基板 1、ベース部材 2B、及びコア部材 2Aが Siで形成さ れ、第 1の半導体膜 10が SiGeで形成されていた力 第 2の実施例では、その逆に、 支持基板 1、ベース部材 2B、及びコア部材 2Aが SiGeで形成され、第 1の半導体膜 10が Siで形成されている。第 1の半導体膜 10を形成した直後には、 SiGeからなるコ ァ部材 2Aに圧縮歪が生じ、 Siからなる第 1の半導体膜 10に引張歪が生じる。  FIG. 5A shows a cross-sectional view of the fin-type MOSFET according to the second embodiment. The cross-sectional view shown in FIG. 5A corresponds to the cross-sectional view shown in FIG. 3D of the fin-type MOSFET according to the first embodiment. In the first embodiment, the support substrate 1, the base member 2B, and the core member 2A are made of Si, and the first semiconductor film 10 is made of SiGe. The support substrate 1, the base member 2B, and the core member 2A are made of SiGe, and the first semiconductor film 10 is made of Si. Immediately after the formation of the first semiconductor film 10, compressive strain is generated in the core member 2A made of SiGe, and tensile strain is generated in the first semiconductor film 10 made of Si.
[0041] また、第 1の実施例では、ストレッサ 25に引張応力が内在していた力 第 2の実施 例では、ストレッサ 25に圧縮応力が内在している。ストレッサ 25は、例えば原料ガスと してテトラメチルシラン（4MS)、 NH3、及び N2を用い、圧力 500Pa、成長温度 400 °Cの条件で、プラズマ励起型 CVDにより形成する。この条件で SiNを堆積させること により、圧縮応力が内在するストレッサ 25を形成することができる。  Further, in the first embodiment, the force in which tensile stress is inherent in the stressor 25 In the second embodiment, the stressor 25 inherently has compressive stress. The stressor 25 is formed by plasma-excited CVD, for example, using tetramethylsilane (4MS), NH3, and N2 as source gases, under conditions of a pressure of 500 Pa and a growth temperature of 400 ° C. By depositing SiN under these conditions, the stressor 25 in which compressive stress is inherent can be formed.
[0042] ストレッサ 25が面内方向に伸びようとするため、チャネル構造体 2Aのうちゲート電 極 18の下方のチャネル領域に圧縮応力が印加される。このため、チャネル部のコア 部材 2Aに生じていた圧縮歪がより大きくなるとともに、第 1の半導体膜 10に生じてい た引張歪が緩和される。コア部材 2Aの表層部に圧縮歪を生じさせることにより、正孔 の移動度を高めることができる。  Since the stressor 25 tends to extend in the in-plane direction, compressive stress is applied to the channel region below the gate electrode 18 in the channel structure 2A. For this reason, the compressive strain generated in the core member 2A of the channel portion becomes larger, and the tensile strain generated in the first semiconductor film 10 is relaxed. By generating a compressive strain in the surface layer portion of the core member 2A, the hole mobility can be increased.
[0043] 図 5Bに、第 2の実施例によるフィン型 MOSFETのコア部材 2Aからゲート電極 18 までの厚さ方向に関するエネルギバンド図を示す。コア部材 2Aの荷電子帯上端の エネルギレベル Evが、第 1の半導体膜 10の荷電子帯上端のエネルギレベル Ενより も高くなる。  FIG. 5B shows an energy band diagram in the thickness direction from the core member 2 A to the gate electrode 18 of the fin-type MOSFET according to the second embodiment. The energy level Ev at the upper end of the valence band of the core member 2A is higher than the energy level Εν at the upper end of the valence band of the first semiconductor film 10.
[0044] ゲート電極 18に負電圧を印加すると、コア部材 2と第 1の半導体膜 10との界面 CH hに正孔が蓄積されチャネルが形成される。このように、ゲート絶縁膜 15と第 1の半導 体膜 10との界面よりも深い領域に、チャネルが形成される。チャネル内を移動する正 孔が、ゲート絶縁膜 15と第 1の半導体膜 10との界面の粗さや界面準位の影響を受 けないため、正孔の移動度の向上が期待できる。 [0045] 例えば、本願発明者の評価実験によると、 Siと Si02との界面に蓄積された正孔の 移動度が 150cm2ZVであり、弓 I張歪を生じさせた Siと Si02との界面に蓄積された 正孔の移動度が 190cm2ZVであるのに対し、圧縮歪を生じさせた SiGeと Siとの界 面に蓄積された正孔の移動度は、 800〜1000cm2ZVであった。 When a negative voltage is applied to the gate electrode 18, holes are accumulated at the interface CH h between the core member 2 and the first semiconductor film 10 to form a channel. Thus, a channel is formed in a region deeper than the interface between the gate insulating film 15 and the first semiconductor film 10. Since the holes moving in the channel are not affected by the roughness or interface state of the interface between the gate insulating film 15 and the first semiconductor film 10, an improvement in hole mobility can be expected. [0045] For example, according to the evaluation experiment of the present inventor, the mobility of holes accumulated at the interface between Si and Si02 is 150cm2ZV, and accumulation at the interface between Si and Si02 that caused bow I tension strain The hole mobility accumulated at the interface between SiGe and Si, which caused the compressive strain, was 800-1000 cm2ZV, whereas the mobility of the generated holes was 190 cm2ZV.
[0046] 第 1の半導体膜 10にァクセプタを添加しておいてもよい。第 1の半導体膜 10の荷 電子帯内に発生した正孔が、コア部材 2Aと第 1の半導体膜 10との界面に蓄積され、 ノーマリオン型の pチャネル MOSFETが得られる。この場合、コア部材 2Aと第 1の半 導体層 10との界面に蓄積された正孔によって、ソース及びドレイン領域に導電性が 付与されるため、ゲート電極 18の形成後に、ソース領域及びドレイン領域を形成する ためのイオン注入を行う必要はな！/、。  An acceptor may be added to the first semiconductor film 10. Holes generated in the valence band of the first semiconductor film 10 are accumulated at the interface between the core member 2A and the first semiconductor film 10, and a normally-on type p-channel MOSFET is obtained. In this case, since conductivity is imparted to the source and drain regions by the holes accumulated at the interface between the core member 2A and the first semiconductor layer 10, the source and drain regions are formed after the gate electrode 18 is formed. It is not necessary to perform ion implantation to form the film! /.
[0047] 上記第 2の実施例では、コア部材 2Aを SiGeで形成し、第 1の半導体膜 10を Siで 形成したが、両者を SiGeで形成することも可能である。この場合、コア部材 2Aの Ge の組成比を第 1の半導体膜 10の Geの組成比よりも大きくすることにより、両者の界面 に、第 2の実施例と同様のエネルギレベルの段差を形成することができる。  [0047] In the second embodiment, the core member 2A is formed of SiGe and the first semiconductor film 10 is formed of Si. However, both of them can be formed of SiGe. In this case, by making the Ge composition ratio of the core member 2A larger than the Ge composition ratio of the first semiconductor film 10, a step having the same energy level as that of the second embodiment is formed at the interface therebetween. be able to.
[0048] 上記第 1及び第 2の実施例では、第 1の半導体膜 10とゲート電極 18との間に、酸 化シリコン力もなるゲート絶縁膜 15を配置したが、第 1の半導体膜 10にゲート電極 1 8をショットキ接触させてもよい。ゲート電極 18を、白金（Pt)、チタン (Ti)、アルミ-ゥ ム (A1)等で形成することにより、ショットキ接触を得ることができる。  In the first and second embodiments, the gate insulating film 15 that also has silicon oxide force is disposed between the first semiconductor film 10 and the gate electrode 18. The gate electrode 18 may be brought into Schottky contact. A Schottky contact can be obtained by forming the gate electrode 18 of platinum (Pt), titanium (Ti), aluminum (A1), or the like.
[0049] 上記第 1及び第 2の実施例では、コア部材 2Aの側面上及び上側の端面上に、第 1 の半導体膜 10及びゲート電極 18を配置した。上側の端面は、側面に比べて幅が極 めて狭いため、上側の端面に形成されるチャネルは MOSFETの動作にほとんど影 響を及ぼさない。従って、コア部材 2Aの 2つの側面上にのみ半導体膜 10及びゲート 電極 18を配置してもよい。  In the first and second embodiments, the first semiconductor film 10 and the gate electrode 18 are arranged on the side surface and the upper end surface of the core member 2A. Since the upper end face is extremely narrow compared to the side face, the channel formed on the upper end face has little effect on the operation of the MOSFET. Therefore, the semiconductor film 10 and the gate electrode 18 may be disposed only on the two side surfaces of the core member 2A.
[0050] 次に、図 6A及び図 6Bを参照して、第 3の実施例によるフィン型 MOSFETについ て、第 1の実施例によるフィン型 MOSFETとの相違点に着目して説明する。  Next, with reference to FIGS. 6A and 6B, the fin-type MOSFET according to the third embodiment will be described focusing on the differences from the fin-type MOSFET according to the first embodiment.
[0051] 図 6Aに、第 3の実施例によるフィン型 MOSFETのチャネル構造体 11の断面図を 示す。第 1の実施例では、図 21に示したように、チャネル構造体 11がコア部材 2Aと 第 1の半導体膜 10とで構成されていたが、第 3の実施例では、第 1の半導体膜 10の 表面上に、さらに S もなる厚さ約 5nmの第 2の半導体膜 12が形成されている。ゲ ート絶縁膜 15は、第 2の半導体膜 12の表面上に形成されている。その他の構成は、 第 1の実施例によるフィン型 MOSFETの構成と同じである。 FIG. 6A is a sectional view of the channel structure 11 of the fin-type MOSFET according to the third embodiment. In the first embodiment, as shown in FIG. 21, the channel structure 11 is composed of the core member 2A and the first semiconductor film 10, but in the third embodiment, the first semiconductor film 10's On the surface, a second semiconductor film 12 having a thickness of about 5 nm and further comprising S is formed. The gate insulating film 15 is formed on the surface of the second semiconductor film 12. Other configurations are the same as those of the fin-type MOSFET according to the first embodiment.
[0052] 図 6Bに、コア部材 2Aからゲート電極 18までの厚さ方向に関するエネルギバンド図 を示す。第 1の実施例の場合と同様に、コア部材 2Aと第 1の半導体膜 10との界面 C Heに電子が蓄積され、 n型のチャネルが形成される。なお、第 2の半導体膜 12は、 量子効果が発現する程度に薄いため、その伝導帯の基底量子準位は、コア部材 2A の伝導帯下端よりも高い。従って、コア部材 2Aと第 1の半導体膜 10との界面 CHeに 優先的に n型のチャネルが形成される。  FIG. 6B shows an energy band diagram in the thickness direction from the core member 2 A to the gate electrode 18. As in the case of the first embodiment, electrons are accumulated at the interface C He between the core member 2A and the first semiconductor film 10, and an n-type channel is formed. Since the second semiconductor film 12 is thin enough to exhibit the quantum effect, the ground quantum level of the conduction band is higher than the lower end of the conduction band of the core member 2A. Therefore, an n-type channel is formed preferentially at the interface CHe between the core member 2A and the first semiconductor film 10.
[0053] 第 1の半導体膜 10の荷電子帯下端のエネルギレベルが、第 2の半導体膜 12のそ れよりも高い。このため、両者の界面 CHhに正孔が蓄積され、 p型のチャネルが形成 される。  The energy level at the lower end of the valence band of the first semiconductor film 10 is higher than that of the second semiconductor film 12. For this reason, holes accumulate at the interface CHh between the two, forming a p-type channel.
[0054] 第 3の実施例のように、チャネル構造体 11を 3層構造にすることにより、ソース及び ドレイン領域を n型にすれば、 nチャネルのフィン型 MOSFETが実現され、ソース及 びドレイン領域を p型にすれば、 pチャネルのフィン型 MOSFETが実現される。この ため、容易に CMOS回路を形成することが可能になる。  [0054] As in the third embodiment, by forming the channel structure 11 in a three-layer structure, if the source and drain regions are n-type, an n-channel fin-type MOSFET is realized, and the source and drain are formed. If the region is made p-type, a p-channel fin-type MOSFET can be realized. Therefore, it becomes possible to easily form a CMOS circuit.
[0055] 第 3の実施例においても、第 1の半導体膜 10にドナーを添加することにより、ノーマ リオン型の nチャネル MOSFETが得られる。また、第 1の半導体膜 10にァクセプタを 添カ卩することにより、ノーマリオン型の pチャネル MOSFETが得られる。  Also in the third embodiment, a normal n-type MOSFET can be obtained by adding a donor to the first semiconductor film 10. In addition, by adding an acceptor to the first semiconductor film 10, a normally-on type p-channel MOSFET can be obtained.
[0056] 第 3の実施例では、コア部材 2A及び第 2の半導体膜 12を Siで形成し、第 1の半導 体膜 10を SiGeで形成した力 これらをすベて SiGeで形成してもよい。この場合、第 1の半導体膜 10の Geの組成比を、コア部材 2A及び第 2の半導体膜 12のいずれの Geの組成比よりも大きくすることにより、第 3の実施例と同様の作用効果を得ることが できる。  [0056] In the third embodiment, the core member 2A and the second semiconductor film 12 are formed of Si, and the first semiconductor film 10 is formed of SiGe. Also good. In this case, by making the Ge composition ratio of the first semiconductor film 10 larger than any Ge composition ratio of the core member 2A and the second semiconductor film 12, the same effect as the third embodiment is achieved. Can be obtained.
[0057] また、コア部材 2A及び第 2の半導体膜 12を、 Geまたは SiGeで形成し、第 1の半導 体膜 10を Sほたは SiGeで形成してもよい。この場合、第 1の半導体膜 10の Geの組 成比を、コア部材 2A及び第 2の半導体膜 12のいずれの Geの組成比よりも小さくする ことが好ましい。 [0058] この構成とした場合、荷電子帯では、図 5Bに示した場合と同様に、コア部材 2Aと 第 1の半導体膜 10との界面に正孔が蓄積され、 p型チャネルが形成される。伝導帯 では、第 1の半導体膜 10と第 2の半導体膜 12との界面に電子が蓄積され、 n型チヤ ネルが形成される。図 5Bに積層構造を用いて nチャネル MOSFETを構成すると、第 1の半導体膜 10とゲート絶縁膜 15との界面に n型チャネルが形成される。第 1の半導 体膜 10とゲート絶縁膜 15との間に第 2の半導体膜 12を挿入すると、 n型チャネルが 、半導体とゲート絶縁膜 15との界面よりも深い領域に形成されるため、電子の移動度 が高くなるという効果が期待できる。 Further, the core member 2A and the second semiconductor film 12 may be formed of Ge or SiGe, and the first semiconductor film 10 may be formed of S or SiGe. In this case, it is preferable that the Ge composition ratio of the first semiconductor film 10 be smaller than the Ge composition ratio of any of the core member 2A and the second semiconductor film 12. In this configuration, in the valence band, holes are accumulated at the interface between the core member 2A and the first semiconductor film 10 as in the case shown in FIG. 5B, and a p-type channel is formed. The In the conduction band, electrons accumulate at the interface between the first semiconductor film 10 and the second semiconductor film 12 to form an n-type channel. When an n-channel MOSFET is configured using the stacked structure in FIG. 5B, an n-type channel is formed at the interface between the first semiconductor film 10 and the gate insulating film 15. When the second semiconductor film 12 is inserted between the first semiconductor film 10 and the gate insulating film 15, the n-type channel is formed in a region deeper than the interface between the semiconductor and the gate insulating film 15. The effect of increasing the mobility of electrons can be expected.
[0059] 上記第 3の実施例では、第 2の半導体膜 12とゲート電極 18との間に、酸化シリコン 力もなるゲート絶縁膜 15を配置したが、第 2の半導体膜 12にゲート電極 18をショット キ接触させてもよい。ゲート電極 18を、白金 (Pt)、チタン (Ti)、アルミニウム (A1)等 で形成することにより、ショットキ接触を得ることができる。  In the third embodiment, the gate insulating film 15 having a silicon oxide force is disposed between the second semiconductor film 12 and the gate electrode 18. However, the gate electrode 18 is provided on the second semiconductor film 12. Schottky contact may be used. A Schottky contact can be obtained by forming the gate electrode 18 of platinum (Pt), titanium (Ti), aluminum (A1), or the like.
[0060] 上記第 1〜第 3の実施例では、ストレッサ 25として窒化シリコンを用いたが、圧縮応 力または引張応力を内在させることができるその他の材料を用いてもよい。例えば、 スパッタリングにより堆積させた窒化チタン (TiN)膜やカーボン (C)膜には圧縮応力 が内在する。  [0060] In the first to third embodiments, silicon nitride is used as the stressor 25, but other materials capable of containing compressive stress or tensile stress may be used. For example, a compressive stress is inherent in a titanium nitride (TiN) film or a carbon (C) film deposited by sputtering.
[0061] また、上記第 1〜第 3の実施例では、支持基板 1、ベース部材 2B、及びコア部材 2 Aを、 1枚のシリコン基板カゝら形成したが、支持基板 1として絶縁性の材料からなる基 板を用いてもよい。ベース部材 2B及びコア部材 2Aは、絶縁性基板上に形成された 半導体膜をパターユングすることにより形成することができる。  In the first to third embodiments, the support substrate 1, the base member 2B, and the core member 2A are formed from one silicon substrate cover. A substrate made of a material may be used. The base member 2B and the core member 2A can be formed by patterning a semiconductor film formed on an insulating substrate.
[0062] 図 3Dを参照して、ストレッサ 25の好ましい膜厚、及びゲート電極 18の好ましい断面 形状について説明する。なお、以下に説明する好適な寸法は、第 2及び第 3の実施 にも当てはまる。  A preferable film thickness of the stressor 25 and a preferable cross-sectional shape of the gate electrode 18 will be described with reference to FIG. 3D. The preferred dimensions described below also apply to the second and third implementations.
[0063] コア部材 2Aのチャネル領域に効率的に歪を生じさせるために、ストレッサ 25の厚さ T2を、コア部材 2Aの上面からストレッサ 25の底面までの距離 T3の 5倍以上とするこ とが好ましい。  [0063] In order to efficiently generate strain in the channel region of the core member 2A, the thickness T2 of the stressor 25 is set to be not less than 5 times the distance T3 from the top surface of the core member 2A to the bottom surface of the stressor 25. Is preferred.
[0064] 上記実施例では、ゲート電極 18の上方に堆積したストレッサ 25にも引張または圧 縮応力が内在している。ゲート電極 18が薄い場合には、この部分の応力がチャネル 領域まで影響を及ぼし、チャネル領域の歪を緩和させてしまう。チャネル領域に効率 的に歪を生じさせるために、ゲート電極 18の両側に配置されたストレッサ 25の底面 力もゲート電極 18の上に配置されたストレッサ 25の底面までの高さ T1を、ゲート電 極 18の X軸方向の寸法 Lの 1倍以上とすることが好ましい。 In the above embodiment, the stressor 25 deposited above the gate electrode 18 also has a tensile or compressive stress. When the gate electrode 18 is thin, the stress in this part This affects the region and relaxes the distortion of the channel region. In order to efficiently generate strain in the channel region, the bottom force of the stressor 25 disposed on both sides of the gate electrode 18 is also set to the height T1 up to the bottom surface of the stressor 25 disposed on the gate electrode 18. It is preferable to be at least 1 times the dimension L in the X-axis direction of 18.
[0065] チャネルを歪ませることによる十分な効果を得るために、チャネル領域に印加される 応力が 2GPa以上になるような構成とすることが好ましい。例えば、 Si層と SiO. 8GeO . 2層との界面に発生する応力が約 2GPaである。一例として、歪の緩和した SiO. 8G eO. 2層上に Si層をェピタキシャル成長させた場合に、 Si層全体に発生する応力が 約 2GPaになる。 [0065] In order to obtain a sufficient effect by distorting the channel, it is preferable that the stress applied to the channel region is 2 GPa or more. For example, the stress generated at the interface between the Si layer and the SiO.8GeO.2 layer is about 2 GPa. As an example, when a Si layer is epitaxially grown on a SiO. 8G eO. 2 layer with relaxed strain, the stress generated in the entire Si layer is about 2 GPa.
[0066] 以上実施例に沿って本発明を説明したが、本発明はこれらに制限されるものでは ない。例えば、種々の変更、改良、組み合わせ等が可能なことは当業者に自明であ ろう。  [0066] Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

Claims

請求の範囲 The scope of the claims
[1] 支持基板の上に、厚さ方向が該支持基板の表面と平行な姿勢で配置され、半導体 材料で形成されたフィン状のコア部材、及び該コア部材とは異なる半導体材料力ゝらな り、該コア部材の 2つの側面を覆う第 1の半導体膜を含むチャネル構造体と、 前記チャネル構造体の一部の領域の両側に配置され、該チャネル構造体の側面 にショットキ接触するか、または該チャネル構造体の側面にゲート絶縁膜を介して対 向するゲート電極と、  [1] A fin-like core member formed of a semiconductor material, the thickness direction of which is arranged in a posture parallel to the surface of the support substrate, and a semiconductor material force different from that of the core member. In other words, a channel structure including a first semiconductor film covering two side surfaces of the core member and a Schottky contact with the side surface of the channel structure, which is disposed on both sides of a partial region of the channel structure. Or a gate electrode facing the side surface of the channel structure through a gate insulating film,
前記チャネル構造体のうち、前記ゲート電極に挟まれた領域の両側に形成されたソ ース及びドレイン領域と  A source and drain region formed on both sides of a region sandwiched between the gate electrodes of the channel structure;
を有し、前記ゲート電極で挟まれた領域の前記コア部材が歪を有するフィン型半導 体装置。  And a fin-type semiconductor device in which the core member in a region sandwiched between the gate electrodes is distorted.
[2] さらに、前記ゲート電極の両側の前記チャネル構造体の表面上に形成され、圧縮 応力または引張応力が内在するストレッサを有する請求項 1に記載のフィン型半導体 装置。  [2] The fin-type semiconductor device according to [1], further comprising a stressor formed on a surface of the channel structure on both sides of the gate electrode and having a compressive stress or a tensile stress.
[3] 前記第 1の半導体膜にドナーが添加されており、前記ソース及びドレイン領域が n 型導電性を有する請求項 1に記載のフィン型半導体装置。  3. The fin-type semiconductor device according to claim 1, wherein a donor is added to the first semiconductor film, and the source and drain regions have n-type conductivity.
[4] 前記第 1の半導体膜にァクセプタが添加されており、前記ソース及びドレイン領域 力 ¾型導電性を有する請求項 1に記載のフィン型半導体装置。 [4] The fin-type semiconductor device according to [1], wherein an acceptor is added to the first semiconductor film, and the source and drain regions have high conductivity.
[5] 前記コア部材が Sほたは SiGeで形成され、前記第 1の半導体膜が SiGeで形成さ れており、該第 1の半導体膜の Geの組成比が該コア部材の Geの組成比よりも大きい 請求項 1に記載のフィン型半導体装置。 [5] The core member is formed of S or SiGe, the first semiconductor film is formed of SiGe, and the composition ratio of Ge of the first semiconductor film is the composition of Ge of the core member. The fin-type semiconductor device according to claim 1, wherein the fin-type semiconductor device is larger than a ratio.
[6] 前記第 1の半導体膜が Sほたは SiGeで形成され、前記コア部材が SiGeで形成さ れており、該コア部材の Geの組成比が該第 1の半導体膜の Geの組成比よりも大きい 請求項 1に記載のフィン型半導体装置。 [6] The first semiconductor film is made of S or SiGe, the core member is made of SiGe, and the Ge composition ratio of the core member is the Ge composition of the first semiconductor film. The fin-type semiconductor device according to claim 1, wherein the fin-type semiconductor device is larger than a ratio.
[7] 前記チャネル構造体が、さらに、前記第 1の半導体膜の側面を覆う第 2の半導体膜 を含み、該第 2の半導体膜は、該第 1の半導体膜とは異なる半導体材料で形成され ており、前記ゲート電極が、該第 2の半導体膜の表面にショットキ接触する力、または 該第 2の半導体膜の表面にゲート絶縁膜を介して対向する請求項 1に記載のフィン 型半導体装置。 [7] The channel structure further includes a second semiconductor film covering a side surface of the first semiconductor film, and the second semiconductor film is formed of a semiconductor material different from the first semiconductor film. 2. The fin according to claim 1, wherein the gate electrode faces the surface of the second semiconductor film through a Schottky contact, or faces the surface of the second semiconductor film through a gate insulating film. Type semiconductor device.
[8] 前記コア部材及び前記第 2の半導体膜が、 Sほたは SiGeで形成されており、前記 第 1の半導体膜が SiGeで形成されており、該第 1の半導体膜の Geの組成比が、前 記コア部材及び前記第 2の半導体膜の 、ずれの Geの組成比よりも大き 、請求項 1に 記載のフィン型半導体装置。  [8] The core member and the second semiconductor film are made of S or SiGe, the first semiconductor film is made of SiGe, and the composition of Ge of the first semiconductor film 2. The fin-type semiconductor device according to claim 1, wherein the ratio is larger than the composition ratio of the shifted Ge between the core member and the second semiconductor film.
[9] 前記コア部材及び前記第 2の半導体膜が、 Geまたは SiGeで形成されており、前記 第 1の半導体膜が SiGeで形成されており、該第 1の半導体膜の Geの組成比が、前 記コア部材及び前記第 2の半導体膜の 、ずれの Geの組成比よりも小さ 、請求項 1に 記載のフィン型半導体装置。  [9] The core member and the second semiconductor film are made of Ge or SiGe, the first semiconductor film is made of SiGe, and the composition ratio of Ge of the first semiconductor film is 2. The fin-type semiconductor device according to claim 1, wherein the core member and the second semiconductor film have a smaller composition ratio of Ge.
[10] さらに、  [10] In addition,
前記支持基板の上に、厚さ方向が該支持基板の表面に平行になる姿勢で配置さ れ、前記コア部材と同一の半導体材料で形成されたフィン状のベース部材と、 前記ベース部材の両側の前記支持基板の表面上に配置され、前記ベース部材の 側面に接する絶縁部材と  A fin-like base member that is disposed on the support substrate in a posture in which the thickness direction is parallel to the surface of the support substrate and is formed of the same semiconductor material as the core member, and both sides of the base member An insulating member disposed on a surface of the support substrate and in contact with a side surface of the base member;
を有し、前記チャネル構造体が、前記ベース部材の上面の上に、両者の厚さ方向が 相互に平行になる姿勢で配置され、前記コア部材が、前記ベース部材よりも薄い請 求項 1に記載のフィン型半導体装置。  The channel structure is disposed on the upper surface of the base member in a posture in which both thickness directions are parallel to each other, and the core member is thinner than the base member. The fin-type semiconductor device according to 1.
[11] 前記コア部材の歪を有する部分の伝導帯下端のエネルギ準位が、前記第 1の半導 体膜の伝導帯下端のエネルギ準位よりも低 、請求項 1に記載のフィン型半導体装置 [11] The fin-type semiconductor according to [1], wherein the energy level at the lower end of the conduction band of the portion having strain of the core member is lower than the energy level at the lower end of the conduction band of the first semiconductor film. Equipment
[12] 前記第 1の半導体膜の荷電子帯上端のエネルギ準位が、前記第 2の半導体膜の 荷電子帯上端のエネルギ準位よりも高い請求項 7に記載のフィン型半導体装置。 12. The fin-type semiconductor device according to claim 7, wherein the energy level at the upper end of the valence band of the first semiconductor film is higher than the energy level at the upper end of the valence band of the second semiconductor film.
[13] 支持基板の表面上に、厚さ方向が該支持基板の表面と平行になる姿勢で配置され た半導体材料からなるフィン状部材を有する下地構造体を準備する工程と、 前記下地構造体の上に、前記フィン状部材を埋め込むように絶縁膜を形成するェ 程と、  [13] preparing a base structure having a fin-like member made of a semiconductor material disposed on the surface of the support substrate in a posture in which the thickness direction is parallel to the surface of the support substrate; Forming an insulating film on the substrate so as to embed the fin-like member;
前記フィン状部材の上端の一部分が現れるように、前記絶縁膜に凹部を形成する 工程と、 前記凹部内に現れた前記フィン状部材の一部分の表層部を除去することにより、該 フィン状部材の上端の一部分を薄くしたコア部材を形成する工程と、 Forming a recess in the insulating film such that a part of the upper end of the fin-like member appears; Removing a surface layer portion of a part of the fin-like member that appears in the recess, thereby forming a core member in which a part of the upper end of the fin-like member is thinned; and
前記コア部材の表面上に、該コア部材とは異なる半導体材料で形成された第 1の 半導体膜を形成する工程と、  Forming a first semiconductor film made of a semiconductor material different from the core member on the surface of the core member;
前記コア部材及び前記第 1の半導体膜を含むチャネル構造体の一部分の両側に ゲート電極を形成する工程と  Forming a gate electrode on both sides of a part of a channel structure including the core member and the first semiconductor film;
を有するフィン型半導体装置の製造方法。 Of manufacturing a fin-type semiconductor device.
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