WO2007046150A1 - Dispositif semi-conducteur de type à ailettes et son procédé de fabrication - Google Patents

Dispositif semi-conducteur de type à ailettes et son procédé de fabrication Download PDF

Info

Publication number
WO2007046150A1
WO2007046150A1 PCT/JP2005/019388 JP2005019388W WO2007046150A1 WO 2007046150 A1 WO2007046150 A1 WO 2007046150A1 JP 2005019388 W JP2005019388 W JP 2005019388W WO 2007046150 A1 WO2007046150 A1 WO 2007046150A1
Authority
WO
WIPO (PCT)
Prior art keywords
fin
semiconductor film
core member
semiconductor device
channel structure
Prior art date
Application number
PCT/JP2005/019388
Other languages
English (en)
Japanese (ja)
Inventor
Takashi Mimura
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2007540867A priority Critical patent/JP5167816B2/ja
Priority to PCT/JP2005/019388 priority patent/WO2007046150A1/fr
Publication of WO2007046150A1 publication Critical patent/WO2007046150A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Definitions

  • the present invention relates to a fin-type semiconductor device and a method for manufacturing the same, and more particularly to a fin-type semiconductor device in which a gate electrode is disposed so as to sandwich a fin-shaped portion and a method for manufacturing the same.
  • Non-Patent Documents 1 and 2 below disclose fin-type MOSFETs.
  • a fin-type MOS FET a fin-type semiconductor portion protruding almost vertically from the substrate surface is used as a channel, and gate electrodes are arranged on both sides thereof. Since the channel potential is controlled from both sides, the short channel effect can be reduced.
  • Patent Document 1 discloses a fin-type MOSFET in which a strained channel layer is formed on the surface of a seed fin that has no strain and also has a semiconductor material force. Carrier mobility can be increased by imparting strain to the channel layer.
  • Patent Document 1 JP 2005-19970
  • Non-Patent Literature 1 Sang- YunKim et ai., Hot Carrier-Induced Degradation in BulkFinFE Ts ", IEEE Electron Device Letters, Vol. 26, No.8, p.566—p.568 (2005)
  • Non-Patent Document 2 Ta et SuPark et al., "Characteristics of Body-Tied Triple-GatepMOSF ETs", IEEE Electron Device Letters, Vol.25, No.12, p.798—p.800 (2004)
  • An object of the present invention is to provide a fin-type semiconductor device capable of increasing the operating speed and a method for manufacturing the same.
  • a fin-shaped core member is formed on a support substrate in a posture in which the thickness direction is parallel to the surface of the support substrate and is formed of a semiconductor material, and the core member A semiconductor material force different from that of the first semiconductor film covering the two side surfaces of the core member.
  • Disposed on both sides of the channel structure and a part of the channel structure, facing the side surface of the channel structure, or facing the side surface of the channel structure through a gate insulating film A source electrode and a drain region formed on both sides of a region sandwiched between the gate electrodes of the channel structure, and the core member in the region sandwiched between the gate electrodes has a strain.
  • a fin-type semiconductor device is provided.
  • an underlying structure having a fin-like member having a semiconductor material force disposed on a surface of a support substrate in a posture in which a thickness direction is parallel to the surface of the support substrate.
  • a step of preparing a step of forming an insulating film so as to embed the fin-shaped member on the base structure, and a recess formed in the insulating film so that a part of the upper end of the fin-shaped member appears.
  • the core member Since the core member is distorted, the mobility of carriers accumulated at the interface between the core member and the first semiconductor film can be increased.
  • a channel is formed at the interface between the core member and the first semiconductor film, it is not affected by the roughness or interface state of the interface between the semiconductor and the gate insulating film. Thereby, the mobility of a carrier can be raised.
  • the characteristics of the semiconductor device can be improved by thinning a part of the fin-like member appearing in the recess.
  • FIG. 1 is a perspective view of a fin-type MOSFET according to a first embodiment.
  • FIGS. 2A and 2B are cross-sectional views of an apparatus in the course of manufacturing a fin-type MOSFET according to the first embodiment.
  • FIGS. 2C and 2D are cross-sectional views of the apparatus in the course of manufacturing the fin-type MOSFET according to the first embodiment.
  • FIGS. 2E and 2F are cross-sectional views of the apparatus in the course of manufacturing the fin-type MOSFET according to the first embodiment.
  • FIGS. 2G and 2H are cross-sectional views of the device in the process of manufacturing the fin-type MOSFET according to the first embodiment.
  • FIG. 21 is a cross-sectional view of the device in the middle of manufacturing the fin-type MOSFET according to the first embodiment.
  • FIGS. 3A and 3B are cross-sectional views of a device in the process of manufacturing a fin-type MOSFET according to the first embodiment.
  • FIGS. 3C and 3D are cross-sectional views of the device in the process of manufacturing the fin-type MOSFET according to the first embodiment.
  • FIG. 4 is an energy band diagram of the fin-type MOSFET according to the first embodiment.
  • FIG. 5A is a cross-sectional view of a fin-type MOSFET according to a second embodiment, and FIG. 5B is its energy band diagram.
  • FIG. 6A is a cross-sectional view of a fin-shaped portion of a fin-type MOSFET according to a third embodiment, and FIG. 6B is an energy band diagram.
  • FIG. 1 shows a perspective view of a fin-type MOSFET according to the first embodiment.
  • a fin-like base member 2B protrudes from the surface of the support substrate 1 in a substantially vertical direction.
  • Define an XYZ Cartesian coordinate system in which the surface of the support substrate 1 is the XY plane and the plane parallel to the side surface of the base member 2B is the ZX plane.
  • the length direction of the base member 2B is parallel to the X axis, and the thickness direction of the base member 2B is parallel to the Y axis.
  • the fin-shaped core member 2A protrudes in the Z-axis direction from the upper surface of the base member 2B.
  • the side surface of the core member 2A is also parallel to the ZX plane, and the thickness of the core member 2A is thinner than that of the base member 2B.
  • the support substrate 1, the base member 2B, and the core member 2A are formed of silicon (Si) single crystal.
  • the base member 2B has a thickness of 40 nm and a height of 260 nm.
  • the core member 2A has a thickness of 5 nm and a height of 130 nm.
  • the first insulating film 3 also having an oxide silicon force covers the upper surface of the support substrate 1 and the side surface of the base member 2B so as to be along the base surface.
  • the thickness of the first insulating film 3 is, for example, 10 nm.
  • Nitro The second insulating film 4 that also has siliconizing power covers the surface of the first insulating film 3 along the base surface.
  • the thickness of the second insulating film 4 is, for example, 50 nm.
  • a third insulating film 5 having an oxide silicon force is disposed on the flat surface of the second insulating film 4.
  • the upper end surfaces of the first and second insulating films 3 and 4 on the side surface of the base member 2B are not covered with the third insulating film 5.
  • the upper surface of the third insulating film 5 is positioned higher than the upper end surfaces of the first and second insulating films 3 and 4, and is positioned slightly higher than the upper surface of the core member 2A. For this reason, the upper end surfaces of the first and second insulating films 3 and 4 are defined as a part of the bottom surface, and a recess 8 in which the third insulating film 5 is exposed on the side surface is defined. The bottom force of the recess 8 The core member 2A protrudes upward.
  • the side surface and the upper end surface of the core member 2A are covered with a first semiconductor film 10 made of SiGe.
  • the first semiconductor film 10 is epitaxially grown on the surface of the core member 2A, and the thickness thereof is, for example, 5 to: LOnm. Due to the difference in lattice constant between Si and SiGe, a tensile strain is generated in the core member 2A immediately after the first semiconductor film 10 is formed, and a compressive strain is generated in the first semiconductor film 10.
  • a fin-like structure including the core member 2A and the first semiconductor film 10 is referred to as a channel structure 11.
  • the surface force of the channel structure 11 is covered with a gate insulating film 15 made of silicon oxide.
  • the thickness of the gate insulating film 15 is, for example, lnm
  • a gate electrode 18 that is long in the Y-axis direction is formed on the third insulating film 5 so as to cross the channel structure 11 that is long in the X-axis direction.
  • the gate electrode 18 is made of, for example, polysilicon.
  • the gate electrode 18 reaches the bottom surface of the recess 8 in a region overlapping with the recess 8, and faces the upper surface and side surface of the channel structure 11 through the gate insulating film 15.
  • a silicon nitride is formed so as to cover a region continuing to the side surface of the gate electrode 18 and the surface of the gate electrode 18.
  • a stressor 25 made of (SiN) is formed.
  • 2A to 21 correspond to a cross section parallel to the YZ plane passing through the intersection of the gate electrode 18 and the core member 2A in the perspective view shown in FIG. 3D corresponds to a cross section parallel to the ZX plane.
  • a base structure in which the fin-like member 2 protrudes in a substantially vertical direction from the surface of the support substrate 1 is prepared.
  • the thickness direction (Y-axis direction) of the fin-like member 2 is parallel to the surface of the support substrate 1.
  • Both the support substrate 1 and the fin-like member 2 are formed of silicon single crystal.
  • the fin-like member 2 extends in a direction perpendicular to the paper surface (X-axis direction).
  • the fin-like member 2 has a thickness of about 40 nm and a height of about 400 nm.
  • the first insulating film 3 having a thickness of about lOnm is formed by thermally oxidizing the surfaces of the base substrate 1 and the fin-like member 2.
  • Silicon nitride (SiN) is deposited on the surface of the first insulating film 3 by chemical vapor deposition (CVD) to form a second insulating film 4 having a thickness of about 50 nm.
  • CVD chemical vapor deposition
  • a third insulating film 5 is formed on the second insulating film 4 by depositing silicon oxide by CVD.
  • the thickness of the third insulating film 5 is such that the upper surface of the third insulating film 5 is higher than the upper surface of the second insulating film 4 above the fin-like member 2 on the flat surface of the support substrate 1. It will be higher.
  • the surface layer portion of the third insulating film 5 is subjected to chemical mechanical polishing until the second insulating film 4 is exposed above the fin-like member 2.
  • the second insulating film 4 covering a part of the upper end side of the fin-like member 2 is etched using phosphoric acid. By this etching, a recess 8 is formed. A part on the upper end side of the fin-like member 2 protrudes from the bottom surface of the recess 8. This protruding portion is covered with the first insulating film 3.
  • the first insulating film 3 covering the protrusions of the fin-like member 2 is removed using a dilute hydrofluoric acid solution.
  • the surface layer portion of the third insulating film 5 is also thinly etched. As a result, a part of the upper end side of the fin-like member 2 is exposed in the recess 8.
  • the exposed surface layer of the fin-like member 2 is oxidized and oxidized.
  • a part of the upper end side of the fin-like member 2 is thinned to a thickness of, for example, 5 nm.
  • the thinned portion is referred to as a core member 2A
  • the non-thinned portion is referred to as a base member 2B.
  • SiGe is selectively epitaxially exposed on the silicon surface exposed in the recess 8, that is, on the side and upper end surfaces of the core member 2A and the upper surface of the base member 2B.
  • a first semiconductor film 10 having a thickness of 5 to: LOnm is formed.
  • the first semiconductor film 10 can be formed, for example, by thermal CVD using silane (SiH4) and germane (GeH4). Due to the difference in lattice constant between Si and SiGe, tensile strain is generated in the core member 2A made of Si, and compressive strain is generated in the first semiconductor film 10 made of SiGe.
  • the surface insulating layer 15 of the first semiconductor film 10 is thermally oxidized to form a gate insulating film 15 having a thickness of 1 nm.
  • the gate insulating film 15 is substantially formed of silicon oxide.
  • the core member 2A and the first semiconductor film 10 constitute a fin-like channel structure 11.
  • a polysilicon film 18A is deposited on the entire surface by CVD.
  • the polysilicon film 18 is filled in the recess 8.
  • FIG. 3A is a cross-sectional view taken along one-dot chain line A3-A3 in FIG.
  • a first semiconductor film 10, a gate insulating film 15, and a polysilicon film 18A are stacked on the upper surface of the core member 2A.
  • the gate electrode 18 made of polysilicon is formed.
  • the gate electrode 18 extends in the Y-axis direction.
  • a source region 20 and a drain region 21 are formed by ion-implanting a donor into the channel structure 11 on both sides thereof.
  • a stressor 25 having a silicon nitride force is formed so as to cover the upper and side surfaces of the gate electrode 18 and the surface of the gate insulating film 15 on both sides thereof.
  • the stressor 25 is formed, for example, by reduced pressure thermal CVD using SiH4, NH3, and N2 as source gases, under conditions of a pressure of 100 Pa and a growth temperature of 800 ° C.
  • the stressor 25 formed under this condition contains tensile stress. That is, the stressor 25 tends to shrink in the in-plane direction.
  • the tensile force is applied to the channel region below the gate electrode 18 in the channel structure 2A.
  • a force is applied.
  • the tensile strain generated in the core member 2A of the channel portion becomes larger and the compressive strain generated in the first semiconductor film 10 is relieved. Electron mobility can be increased by generating tensile strain in the surface layer portion of the core member 2A.
  • FIG. 4 shows an energy band diagram in the thickness direction from the core member 2 A to the gate electrode 18 of the fin-type MOSFET according to the first embodiment.
  • a SiGe film having a thickness less than the critical film thickness is epitaxially grown on the Si substrate, the energy levels at the lower end of the conduction band of the Si substrate and the lower end of the conduction band of the SiGe film are almost equal.
  • the compressive strain of the first semiconductor film 10 made of SiGe is relaxed, and tensile strain is generated in the core member 2A made of S.
  • the energy level Ec force at the lower end of the conduction band of the surface layer portion of the core member 2A is lower than the energy level Ec at the lower end of the conduction band of the first semiconductor film 10.
  • the mobility of electrons accumulated at the interface between Si and Si02 is 500cm2ZV, and the electrons accumulated at the interface between Si and Si02 that caused tensile strain.
  • a donor may be added to the first semiconductor film 10.
  • Electronic force generated in the conduction band of the first semiconductor film 10 is accumulated at the interface between the core member 2A and the first semiconductor film 10, and a normally-on type MOSFET is obtained.
  • conductivity is imparted to the source and drain regions by the electrons accumulated at the interface between the core member 2A and the first semiconductor layer 10, so that the ions are formed using the gate electrode 18 shown in FIG. 3C as a mask. There is no need for an injection.
  • the core member 2A is made of Si and the first semiconductor film 10 is made of SiGe. However, both of them can be made of SiGe.
  • the Ge composition ratio of the first semiconductor film 10 is made larger than the Ge composition ratio of the core member 2A, a step having the same energy level as in the first embodiment is formed at the interface between the two. can do.
  • FIGS. 5A and 5B the fin-type MOSFET according to the second embodiment will be described by focusing on the differences from the fin-type MOSFET according to the first embodiment.
  • FIG. 5A shows a cross-sectional view of the fin-type MOSFET according to the second embodiment.
  • the cross-sectional view shown in FIG. 5A corresponds to the cross-sectional view shown in FIG. 3D of the fin-type MOSFET according to the first embodiment.
  • the support substrate 1, the base member 2B, and the core member 2A are made of Si, and the first semiconductor film 10 is made of SiGe.
  • the support substrate 1, the base member 2B, and the core member 2A are made of SiGe, and the first semiconductor film 10 is made of Si.
  • compressive strain is generated in the core member 2A made of SiGe
  • tensile strain is generated in the first semiconductor film 10 made of Si.
  • the force in which tensile stress is inherent in the stressor 25 inherently has compressive stress.
  • the stressor 25 is formed by plasma-excited CVD, for example, using tetramethylsilane (4MS), NH3, and N2 as source gases, under conditions of a pressure of 500 Pa and a growth temperature of 400 ° C. By depositing SiN under these conditions, the stressor 25 in which compressive stress is inherent can be formed.
  • the stressor 25 tends to extend in the in-plane direction, compressive stress is applied to the channel region below the gate electrode 18 in the channel structure 2A. For this reason, the compressive strain generated in the core member 2A of the channel portion becomes larger, and the tensile strain generated in the first semiconductor film 10 is relaxed. By generating a compressive strain in the surface layer portion of the core member 2A, the hole mobility can be increased.
  • FIG. 5B shows an energy band diagram in the thickness direction from the core member 2 A to the gate electrode 18 of the fin-type MOSFET according to the second embodiment.
  • the energy level Ev at the upper end of the valence band of the core member 2A is higher than the energy level ⁇ at the upper end of the valence band of the first semiconductor film 10.
  • the mobility of holes accumulated at the interface between Si and Si02 is 150cm2ZV, and accumulation at the interface between Si and Si02 that caused bow I tension strain
  • An acceptor may be added to the first semiconductor film 10. Holes generated in the valence band of the first semiconductor film 10 are accumulated at the interface between the core member 2A and the first semiconductor film 10, and a normally-on type p-channel MOSFET is obtained. In this case, since conductivity is imparted to the source and drain regions by the holes accumulated at the interface between the core member 2A and the first semiconductor layer 10, the source and drain regions are formed after the gate electrode 18 is formed. It is not necessary to perform ion implantation to form the film! /.
  • the core member 2A is formed of SiGe and the first semiconductor film 10 is formed of Si.
  • both of them can be formed of SiGe.
  • a step having the same energy level as that of the second embodiment is formed at the interface therebetween. be able to.
  • the gate insulating film 15 that also has silicon oxide force is disposed between the first semiconductor film 10 and the gate electrode 18.
  • the gate electrode 18 may be brought into Schottky contact.
  • a Schottky contact can be obtained by forming the gate electrode 18 of platinum (Pt), titanium (Ti), aluminum (A1), or the like.
  • the first semiconductor film 10 and the gate electrode 18 are arranged on the side surface and the upper end surface of the core member 2A. Since the upper end face is extremely narrow compared to the side face, the channel formed on the upper end face has little effect on the operation of the MOSFET. Therefore, the semiconductor film 10 and the gate electrode 18 may be disposed only on the two side surfaces of the core member 2A.
  • the fin-type MOSFET according to the third embodiment will be described focusing on the differences from the fin-type MOSFET according to the first embodiment.
  • FIG. 6A is a sectional view of the channel structure 11 of the fin-type MOSFET according to the third embodiment.
  • the channel structure 11 is composed of the core member 2A and the first semiconductor film 10, but in the third embodiment, the first semiconductor film 10's On the surface, a second semiconductor film 12 having a thickness of about 5 nm and further comprising S is formed.
  • the gate insulating film 15 is formed on the surface of the second semiconductor film 12.
  • Other configurations are the same as those of the fin-type MOSFET according to the first embodiment.
  • FIG. 6B shows an energy band diagram in the thickness direction from the core member 2 A to the gate electrode 18.
  • electrons are accumulated at the interface C He between the core member 2A and the first semiconductor film 10, and an n-type channel is formed.
  • the second semiconductor film 12 is thin enough to exhibit the quantum effect, the ground quantum level of the conduction band is higher than the lower end of the conduction band of the core member 2A. Therefore, an n-type channel is formed preferentially at the interface CHe between the core member 2A and the first semiconductor film 10.
  • the energy level at the lower end of the valence band of the first semiconductor film 10 is higher than that of the second semiconductor film 12. For this reason, holes accumulate at the interface CHh between the two, forming a p-type channel.
  • the channel structure 11 by forming the channel structure 11 in a three-layer structure, if the source and drain regions are n-type, an n-channel fin-type MOSFET is realized, and the source and drain are formed. If the region is made p-type, a p-channel fin-type MOSFET can be realized. Therefore, it becomes possible to easily form a CMOS circuit.
  • a normal n-type MOSFET can be obtained by adding a donor to the first semiconductor film 10.
  • a normally-on type p-channel MOSFET can be obtained.
  • the core member 2A and the second semiconductor film 12 are formed of Si, and the first semiconductor film 10 is formed of SiGe. Also good. In this case, by making the Ge composition ratio of the first semiconductor film 10 larger than any Ge composition ratio of the core member 2A and the second semiconductor film 12, the same effect as the third embodiment is achieved. Can be obtained.
  • the core member 2A and the second semiconductor film 12 may be formed of Ge or SiGe, and the first semiconductor film 10 may be formed of S or SiGe.
  • the Ge composition ratio of the first semiconductor film 10 be smaller than the Ge composition ratio of any of the core member 2A and the second semiconductor film 12.
  • the valence band holes are accumulated at the interface between the core member 2A and the first semiconductor film 10 as in the case shown in FIG. 5B, and a p-type channel is formed.
  • the In the conduction band electrons accumulate at the interface between the first semiconductor film 10 and the second semiconductor film 12 to form an n-type channel.
  • an n-type channel is formed at the interface between the first semiconductor film 10 and the gate insulating film 15.
  • the n-type channel is formed in a region deeper than the interface between the semiconductor and the gate insulating film 15. The effect of increasing the mobility of electrons can be expected.
  • the gate insulating film 15 having a silicon oxide force is disposed between the second semiconductor film 12 and the gate electrode 18.
  • the gate electrode 18 is provided on the second semiconductor film 12.
  • Schottky contact may be used.
  • a Schottky contact can be obtained by forming the gate electrode 18 of platinum (Pt), titanium (Ti), aluminum (A1), or the like.
  • silicon nitride is used as the stressor 25, but other materials capable of containing compressive stress or tensile stress may be used.
  • a compressive stress is inherent in a titanium nitride (TiN) film or a carbon (C) film deposited by sputtering.
  • the support substrate 1, the base member 2B, and the core member 2A are formed from one silicon substrate cover.
  • a substrate made of a material may be used.
  • the base member 2B and the core member 2A can be formed by patterning a semiconductor film formed on an insulating substrate.
  • a preferable film thickness of the stressor 25 and a preferable cross-sectional shape of the gate electrode 18 will be described with reference to FIG. 3D.
  • the preferred dimensions described below also apply to the second and third implementations.
  • the thickness T2 of the stressor 25 is set to be not less than 5 times the distance T3 from the top surface of the core member 2A to the bottom surface of the stressor 25. Is preferred.
  • the stressor 25 deposited above the gate electrode 18 also has a tensile or compressive stress.
  • the stress in this part This affects the region and relaxes the distortion of the channel region.
  • the bottom force of the stressor 25 disposed on both sides of the gate electrode 18 is also set to the height T1 up to the bottom surface of the stressor 25 disposed on the gate electrode 18. It is preferable to be at least 1 times the dimension L in the X-axis direction of 18.
  • the stress applied to the channel region is 2 GPa or more.
  • the stress generated at the interface between the Si layer and the SiO.8GeO.2 layer is about 2 GPa.
  • the stress generated in the entire Si layer is about 2 GPa.

Abstract

Dans la présente invention, une structure de canal est formée sur un substrat de support. La structure de canal est disposée dans une position où une direction de l'épaisseur est parallèle à la surface du substrat de support. La structure de canal est composée d’un élément de noyau en forme d’ailette formé d'un matériau semi-conducteur, et d’un matériau semi-conducteur différent de celui de l'élément de noyau, et comprend une première pellicule semi-conductrice servant à recouvrir deux plans latéraux de l'élément de noyau. Des électrodes de gâchette sont disposées de part et d’autre d’une zone à l’intérieur de la structure de canal. Les électrodes de gâchette sont mises en contact de Schottky avec les plans latéraux de la structure de canal, ou font face aux plans latéraux de la structure de canal à travers des pellicules d’isolation de gâchette. Dans la structure de canal, de part et d’autre de la zone intercalée entre les électrodes de gâchette, sont définies des zones de source et de drain. L'élément de noyau dans la zone intercalée entre les électrodes de gâchette présente une distorsion.
PCT/JP2005/019388 2005-10-21 2005-10-21 Dispositif semi-conducteur de type à ailettes et son procédé de fabrication WO2007046150A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007540867A JP5167816B2 (ja) 2005-10-21 2005-10-21 フィン型半導体装置及びその製造方法
PCT/JP2005/019388 WO2007046150A1 (fr) 2005-10-21 2005-10-21 Dispositif semi-conducteur de type à ailettes et son procédé de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/019388 WO2007046150A1 (fr) 2005-10-21 2005-10-21 Dispositif semi-conducteur de type à ailettes et son procédé de fabrication

Publications (1)

Publication Number Publication Date
WO2007046150A1 true WO2007046150A1 (fr) 2007-04-26

Family

ID=37962252

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/019388 WO2007046150A1 (fr) 2005-10-21 2005-10-21 Dispositif semi-conducteur de type à ailettes et son procédé de fabrication

Country Status (2)

Country Link
JP (1) JP5167816B2 (fr)
WO (1) WO2007046150A1 (fr)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010157723A (ja) * 2008-12-29 2010-07-15 Taiwan Semiconductor Manufacturing Co Ltd 集積回路構造及びその製造方法
JP2010258443A (ja) * 2009-04-01 2010-11-11 Taiwan Semiconductor Manufacturing Co Ltd 改善されたオン／オフ電流比の高移動度多重ゲートトランジスタ
JP2011035391A (ja) * 2009-07-31 2011-02-17 Taiwan Semiconductor Manufacturing Co Ltd 高移動度マルチゲートトランジスタのフィン構造
JP2011061196A (ja) * 2009-09-01 2011-03-24 Taiwan Semiconductor Manufacturing Co Ltd 蓄積型ｆｉｎｆｅｔ、回路、及びその製造方法
JP2013513250A (ja) * 2009-12-23 2013-04-18 インテル コーポレイション 非平面ゲルマニウム量子井戸デバイス
JP2013513973A (ja) * 2009-12-30 2013-04-22 インテル・コーポレーション マルチゲートｉｉｉ−ｖ量子井戸構造
US8455860B2 (en) 2009-04-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing source/drain resistance of III-V based transistors
US8617976B2 (en) 2009-06-01 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
WO2014062586A1 (fr) * 2012-10-15 2014-04-24 Semi Solutions Llc Finfet résistant à une fluctuation de dopage aléatoire
US8816391B2 (en) 2009-04-01 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain engineering of devices with high-mobility channels
KR101452122B1 (ko) 2013-03-08 2014-10-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 변형된 웰 영역을 갖는 finfet
US9087902B2 (en) 2013-02-27 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
EP2878013A4 (fr) * 2012-07-27 2015-12-30 Intel Corp Canaux contraints à mobilité élevée pour transistors à base d'ailettes
CN105280496A (zh) * 2014-06-05 2016-01-27 联华电子股份有限公司 具有鳍状结构的半导体元件及其制作方法
US9385234B2 (en) 2013-02-27 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
KR20160136296A (ko) * 2014-03-27 2016-11-29 인텔 코포레이션 핀 기반 nmos 트랜지스터를 위한 고 이동도 변형된 채널
US9590105B2 (en) 2014-04-07 2017-03-07 National Chiao-Tung University Semiconductor device with metal alloy over fin, conductive layer over channel region of fin, and semiconductive layer over conductive layer and formation thereof
JP2017517895A (ja) * 2014-11-14 2017-06-29 ユニスト（ウルサン ナショナル インスティテュート オブ サイエンス アンド テクノロジー）Ｕｎｉｓｔ （Ｕｌｓａｎ Ｎａｔｉｏｎａｌ Ｉｎｓｔｉｔｕｔｅ Ｏｆ Ｓｃｉｅｎｃｅ Ａｎｄ Ｔｅｃｈｎｏｌｏｇｙ） 表面ラフネス散乱を最小化または無くした高性能低電力電界効果トランジスタ素子の製造方法
US9768305B2 (en) 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
US9847404B2 (en) 2013-07-06 2017-12-19 Semiwise Limited Fluctuation resistant FinFET

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105900243A (zh) * 2013-09-27 2016-08-24 英特尔公司 在包覆的iii-v族沟道材料中实现高迁移率的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
JP2005005633A (ja) * 2003-06-16 2005-01-06 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2005019970A (ja) * 2003-06-23 2005-01-20 Sharp Corp 歪みシリコンフィンｆｅｔデバイス
JP2005521258A (ja) * 2002-03-19 2005-07-14 インターナショナル・ビジネス・マシーンズ・コーポレーション 歪みフィンｆｅｔ構造および方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
JP3843043B2 (ja) * 1996-09-17 2006-11-08 松下電器産業株式会社 半導体装置
JPH11274315A (ja) * 1998-03-19 1999-10-08 Hitachi Ltd 半導体装置
JP2005064500A (ja) * 2003-08-14 2005-03-10 Samsung Electronics Co Ltd マルチ構造のシリコンフィンおよび製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
JP2005521258A (ja) * 2002-03-19 2005-07-14 インターナショナル・ビジネス・マシーンズ・コーポレーション 歪みフィンｆｅｔ構造および方法
JP2005005633A (ja) * 2003-06-16 2005-01-06 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2005019970A (ja) * 2003-06-23 2005-01-20 Sharp Corp 歪みシリコンフィンｆｅｔデバイス

Cited By (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010157723A (ja) * 2008-12-29 2010-07-15 Taiwan Semiconductor Manufacturing Co Ltd 集積回路構造及びその製造方法
US8816391B2 (en) 2009-04-01 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain engineering of devices with high-mobility channels
JP2010258443A (ja) * 2009-04-01 2010-11-11 Taiwan Semiconductor Manufacturing Co Ltd 改善されたオン／オフ電流比の高移動度多重ゲートトランジスタ
US10109748B2 (en) 2009-04-01 2018-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US9590068B2 (en) 2009-04-01 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US8927371B2 (en) 2009-04-01 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US8674341B2 (en) 2009-04-01 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US8455860B2 (en) 2009-04-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing source/drain resistance of III-V based transistors
US8674408B2 (en) 2009-04-30 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing source/drain resistance of III-V based transistors
US9768305B2 (en) 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
US10269970B2 (en) 2009-05-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
US9006788B2 (en) 2009-06-01 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
US8617976B2 (en) 2009-06-01 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
JP2011035391A (ja) * 2009-07-31 2011-02-17 Taiwan Semiconductor Manufacturing Co Ltd 高移動度マルチゲートトランジスタのフィン構造
US8896055B2 (en) 2009-09-01 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
JP2011061196A (ja) * 2009-09-01 2011-03-24 Taiwan Semiconductor Manufacturing Co Ltd 蓄積型ｆｉｎｆｅｔ、回路、及びその製造方法
JP2013513250A (ja) * 2009-12-23 2013-04-18 インテル コーポレイション 非平面ゲルマニウム量子井戸デバイス
JP2013513973A (ja) * 2009-12-30 2013-04-22 インテル・コーポレーション マルチゲートｉｉｉ−ｖ量子井戸構造
EP3998639A1 (fr) * 2012-07-27 2022-05-18 INTEL Corporation Canaux contraints à mobilité élevée pour transistors à base d'ailettes
EP2878013A4 (fr) * 2012-07-27 2015-12-30 Intel Corp Canaux contraints à mobilité élevée pour transistors à base d'ailettes
US9893149B2 (en) 2012-07-27 2018-02-13 Intel Corporation High mobility strained channels for fin-based transistors
WO2014062586A1 (fr) * 2012-10-15 2014-04-24 Semi Solutions Llc Finfet résistant à une fluctuation de dopage aléatoire
US9859380B2 (en) 2013-02-27 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9087902B2 (en) 2013-02-27 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US10158015B2 (en) 2013-02-27 2018-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9159824B2 (en) 2013-02-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9601342B2 (en) 2013-02-27 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9748142B2 (en) 2013-02-27 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9748143B2 (en) 2013-02-27 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9455320B2 (en) 2013-02-27 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9385234B2 (en) 2013-02-27 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US10164022B2 (en) 2013-03-08 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US10164023B2 (en) 2013-03-08 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
KR101452122B1 (ko) 2013-03-08 2014-10-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 변형된 웰 영역을 갖는 finfet
US9847404B2 (en) 2013-07-06 2017-12-19 Semiwise Limited Fluctuation resistant FinFET
KR20160136296A (ko) * 2014-03-27 2016-11-29 인텔 코포레이션 핀 기반 nmos 트랜지스터를 위한 고 이동도 변형된 채널
US10854752B2 (en) 2014-03-27 2020-12-01 Intel Corporation High mobility strained channels for fin-based NMOS transistors
KR102201112B1 (ko) * 2014-03-27 2021-01-12 인텔 코포레이션 핀 기반 nmos 트랜지스터를 위한 고 이동도 변형된 채널
KR101779650B1 (ko) * 2014-04-07 2017-09-18 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 디바이스 및 그 형성
US9590105B2 (en) 2014-04-07 2017-03-07 National Chiao-Tung University Semiconductor device with metal alloy over fin, conductive layer over channel region of fin, and semiconductive layer over conductive layer and formation thereof
CN105280496A (zh) * 2014-06-05 2016-01-27 联华电子股份有限公司 具有鳍状结构的半导体元件及其制作方法
CN105280496B (zh) * 2014-06-05 2019-06-11 联华电子股份有限公司 具有鳍状结构的半导体元件及其制作方法
JP2017517895A (ja) * 2014-11-14 2017-06-29 ユニスト（ウルサン ナショナル インスティテュート オブ サイエンス アンド テクノロジー）Ｕｎｉｓｔ （Ｕｌｓａｎ Ｎａｔｉｏｎａｌ Ｉｎｓｔｉｔｕｔｅ Ｏｆ Ｓｃｉｅｎｃｅ Ａｎｄ Ｔｅｃｈｎｏｌｏｇｙ） 表面ラフネス散乱を最小化または無くした高性能低電力電界効果トランジスタ素子の製造方法

Also Published As

Publication number Publication date
JP5167816B2 (ja) 2013-03-21
JPWO2007046150A1 (ja) 2009-04-23

Similar Documents

Publication Publication Date Title
JP5167816B2 (ja) フィン型半導体装置及びその製造方法
US7154118B2 (en) Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7405436B2 (en) Stressed field effect transistors on hybrid orientation substrate
JP5443983B2 (ja) 応力がかけられたチャネル領域を有する改善されたｃｍｏｓデバイス及びそれを製造する方法（半導体デバイスおよび該半導体デバイスの形成方法）
US8232191B2 (en) Semiconductor device manufacturing method
KR100962947B1 (ko) 고이동도 평면 및 다중-게이트 ＭＯＳＦＥＴｓ을 위한 혼성기판 기술
US6603156B2 (en) Strained silicon on insulator structures
US8502284B2 (en) Semiconductor device and method of manufacturing semiconductor device
US7166897B2 (en) Method and apparatus for performance enhancement in an asymmetrical semiconductor device
TWI261323B (en) MOSFET device with localized stressor
KR20020066191A (ko) Ｍｏｓ 전계 효과 트랜지스터
US8963248B2 (en) Semiconductor device having SSOI substrate with relaxed tensile stress
US20070298549A1 (en) Method of fabricating a strained multi-gate transistor and devices obtained thereof
US7485929B2 (en) Semiconductor-on-insulator (SOI) strained active areas
TW200428472A (en) Semiconductor substrate, semiconductor device, and method of manufacturing the same
JP2007536736A (ja) チャネルキャリア移動度向上のための高応力ライナーを備えたＳｉ−Ｇｅに基づく半導体デバイス
JP2013534052A (ja) 埋め込みストレッサ要素を含む半導体構造およびその製造方法
JP2009503892A (ja) 応力がかけられたｍｏｓデバイスの製造方法
CN101431101A (zh) 制造半导体器件的方法
WO2007036998A1 (fr) Dispositif semiconducteur et son procédé de fabrication
US9947689B2 (en) Semiconductor device structure with 110-PFET and 111-NFET current flow direction
US20090101945A1 (en) Semiconductor device
WO2008038346A1 (fr) Dispositif semiconducteur et son procédé de fabrication
US10446666B2 (en) Semiconductor structure and fabrication method thereof
US20050070070A1 (en) Method of forming strained silicon on insulator

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2007540867

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05795613

Country of ref document: EP

Kind code of ref document: A1