TWI603476B - 使用源極與汲極應力源之應變通道區域電晶體及包括其之系統 - Google Patents

使用源極與汲極應力源之應變通道區域電晶體及包括其之系統 Download PDF

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TWI603476B
TWI603476B TW105124465A TW105124465A TWI603476B TW I603476 B TWI603476 B TW I603476B TW 105124465 A TW105124465 A TW 105124465A TW 105124465 A TW105124465 A TW 105124465A TW I603476 B TWI603476 B TW I603476B
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凡 雷
哈洛德 肯拿
威利 瑞奇曼第
拉維 皮拉瑞斯提
傑克 卡瓦李耶羅
尼洛依 穆可吉
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英特爾股份有限公司
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Description

使用源極與汲極應力源之應變通道區域電晶體及包括其之系統
本發明之實施例一般係關於積體電路、半導體裝置、電晶體、單(single)及多閘(multigate)電晶體以及奈米帶(nanoribbon)與奈米線(nanowire)電晶體。
推往更小更高度的積體電路(IC;integrated circuit)及其它半導體裝置對於用以建構裝置的技術及材料下訂了巨量的需求。一般來說,IC晶片為亦如所知的微晶片、矽晶片或是晶片。積體電路晶片已在各種一般的裝置中發現、像是在電腦、汽車、電視、CD播放器及行動電話中的處理器。複數的IC晶片一般建立在矽晶圓(wafer)(薄矽圓盤,具有直徑,例如為300mm的)上,並且在處理後晶圓被切開以產生單獨的晶片。具有約90奈米(nm)左右之特徵尺寸的1平方公分(cm2)IC晶片能夠包含數以億計(hundreds of millions)的組件。 目前的技術正推向小於45nm的特徵尺寸。IC晶片的組件例如包括電晶體,諸如互補式金氧半導體(CMOS;complementary metal oxide semiconductor)裝置、電容結構、電阻結構及提供介於組件與外部裝置之間的電子連接之金屬線。
本發明之詳細說明
本發明之實施例提供具有應變(strained)通道區域之電晶體結構。提供具有由創建在電晶體通道區域中之應力(stress)的材料組成的源極與汲極區域之電晶體。在本發明實施例中,電晶體源極與汲極區域能夠由包含自周期表IIIA(3A)及VA(5A)族群的元素的摻雜材料組成(摻雜的III-V複合半導體(compound semiconductor)材料)。在本發明實施例中,電晶體通道區域能夠由鍺(germanium)、矽、鍺與矽的結合或鍺、矽、以及或是錫的結合(像是,GexSiySn1-x-y)組成。本發明的實施例在各種電晶體結構中是非常有用的,例如像是三閘(trigate)、雙閘(bigate)及單閘(single gate)電晶體以及具有由奈米線或奈米帶組成之通道區域的電晶體。
一般來說,在CMOS電晶體通道區域中之載體(電洞或電子)的遷移率能夠被在通道區域中的材料組成及應變(拉伸(tensile)或壓縮(compressive))所影響。對於PMOS(p通道金氧半導體)電晶體裝置來說,具有單軸 (uniaxial)壓縮應變之通道區域能夠提供用於給定設計電壓之增大的驅動電流以及在電晶體通道區域上未展現壓縮應變的閘極長度。對於NMOS(n通道金氧半導體)電晶體裝置來說,具有單軸拉伸應變之通道區域能夠提供用於給定設計電壓之增大的驅動電流以及在電晶體通道區域上未展現拉伸應變的閘極長度。包含具有大於通道區域之者的晶格常數(crystal lattice constant)之材料的源極與汲極區域能夠在PMOS電晶體的通道區域中創建壓縮應變,並且包含具有小於通道區域之者的晶格常數之材料的源極與汲極區域能夠在NMOS電晶體的通道區域中創建拉伸應變。
105‧‧‧基板
110‧‧‧隔離溝槽
115‧‧‧通道區域
120‧‧‧源極區域
125‧‧‧汲極區域
130‧‧‧閘極電極區域
135‧‧‧閘極介電區域
140‧‧‧選擇的絕緣間隔層
205‧‧‧基板
210‧‧‧通道區域
220‧‧‧源極區域
225‧‧‧汲極區域
230‧‧‧絕緣區域
240‧‧‧閘極電極
245‧‧‧絕緣間隔層
246‧‧‧絕緣間隔層
250‧‧‧絕緣區域
251‧‧‧絕緣區域
305‧‧‧基板
310‧‧‧通道區域
320‧‧‧源極區域
325‧‧‧汲極區域
335‧‧‧閘極介電質
340‧‧‧閘極電極
345‧‧‧絕緣間隔層
346‧‧‧絕緣間隔層
350‧‧‧絕緣區域
351‧‧‧絕緣區域
405‧‧‧基板
410‧‧‧奈米帶/奈米線
415‧‧‧通道區域
420‧‧‧源極區域
425‧‧‧汲極區域
430‧‧‧閘極電極區域
435‧‧‧閘極介電質
440‧‧‧閘極電極
445‧‧‧絕緣間隔層
450‧‧‧絕緣區域
1000‧‧‧計算裝置
1002‧‧‧主機板
1004‧‧‧處理器
1006‧‧‧通訊晶片
圖1為闡述單閘電晶體結構之示意圖。
圖2A~B為闡述雙閘電晶體結構剖面視圖之示意圖。
圖3A~B為闡述三閘電晶體結構剖面視圖之示意圖。
圖4A~B為闡述在通道區域中包含奈米線或奈米帶之電晶體結構的剖面視圖之示意圖。
圖5為依據本發明之實現建立的計算裝置。
圖1闡述具有應變通道區域的單閘電晶體結構。其它結構亦可能用於單閘電晶體,像是具有相對於彼此不同定向特徵者以及具有帶有不同形狀及或尺寸之特徵的結構。 例如,具有相對於通道區域並未凹進的源極與汲極區域之單閘電晶體結構亦為可能。在圖1中,基板105具有最近的隔離溝槽110並且內藏通道區域115。隔離溝槽110由絕緣材料組成並且能夠自組成半導體晶片的其它裝置電性隔離電晶體結構。在本發明實施例中,基板105例如包含矽、鍺、SixGe1-x、在絕緣體上的矽、在絕緣體上的鍺或III-V複合材料(包含來自周期表的IIIA及VA族群的元素之材料)。在本發明實施例中,通道區域115包含鍺、矽、鍺與矽的結合、或是鍺、矽以及或錫(例如像是GexSiySn1-x-y)的結合。通道區域115能夠被摻雜或不摻雜。在本發明實施例中,摻雜濃度範圍從1e16至1e20原子/立方公分(atoms/cm3)。源極與汲極區域120及125在通道區域115中創建壓縮或伸張應變並且由具有相對於通道較大或較小(個別的)晶格常數的材料所組成。在本發明實施例中,源極與汲極區域120及125由摻雜III-V複合半導體材料(包含自周期表的IIIA族群與VA族群元素之材料)組成。在本發明實施例中,摻雜物包括鍺(germanium)、碳(carbon)、矽(silicon)、鎂(magnesium)、鈹(beryllium)、錳(manganese)及或鋅(zinc)。其它摻雜物亦有可能。閘極電極區域130在通道區域115的一側且藉由閘極介電區域135自通道區域115分離。選擇的絕緣間隔層140在裝置製造期間形成以促進製造並且用作電性隔離電晶體閘極區域。
圖2A~B繪示具有應變通道區域的雙閘電晶體結構。 圖2B代表沿著旋轉45°的圖2A結構的2-2之視圖。在圖2A~B中,基板205內藏通道區域210。在本發明實施例中,通道區域210由鍺、矽、鍺與矽的結合、或是鍺、矽以及或錫(例如像是GexSiySn1-x-y)的結合組成。通道區域115能夠被摻雜或不摻雜。在本發明實施例中,摻雜濃度範圍從1e16至1e20原子/立方公分(atoms/cm3)。基板205例如由矽、鍺、SixGe1-x、在絕緣體上的矽、在絕緣體上的鍺或III-V複合材料。源極與汲極區域220與225鄰近通道區域210的末端。源極與汲極區域220與225在通道區域中創建壓縮或伸張應變並且由具有比通道區域之者較大或較小的(個別的)晶格常數之材料組成。在本發明實施例中,源極與汲極區域220與225由摻雜III-V複合半導體材料(包含來自周期表的IIIA族群及VA族群的元素之材料)組成。在本發明實施例中,摻雜物包括鍺(germanium)、碳(carbon)、矽(silicon)、鎂(magnesium)、鈹(beryllium)、錳(manganese)及或鋅(zinc)。其它摻雜物亦有可能。絕緣區域230置於通道區域210的一側。
在圖2B中,雙閘電晶體結構額外的包含閘極介電質235與閘極電極240。閘極介電質235置於通道區域210的兩個相對側上。閘極電極240置於閘極介電質235上。選擇地,絕緣間隔層245及246鄰近閘極介電質235與閘極電極240。電晶體結構一般覆於絕緣介電層,其部分的繪示為絕緣區域250及251。
圖3A~B繪示具有應變通道區域的三閘電晶體結構。圖3B代表沿著沿著旋轉45°的圖3A結構的3-3之視圖。在圖3A~B中,基板305內藏通道區域310。在本發明實施例中,通道區域310由鍺、矽、鍺與矽的結合或是鍺、矽以及或錫(例如像是GexSiySn1-x-y)的結合組成。基板305例如由矽、鍺、SixGe1-x、在絕緣體上的矽、在絕緣體上的鍺或III-V複合材料組成。源極與汲極區域320與325鄰近通道區域310的末端。源極與汲極區域320與325在通道區域中創建壓縮或伸張應變並且由具有比通道區域之者較大或較小(個別的)的晶格常數之材料組成。在本發明實施例中,源極與汲極區域320與325由摻雜III-V複合半導體材料(包含自周期表的IIIA族群與VA族群的元素之材料)組成。在本發明實施例中,摻雜物包括鍺、碳、矽、鎂、鈹、錳以及或鋅。其它摻雜物亦有可能。
三閘電晶體結構額外的包含閘極介電質335及閘極電極340。閘極介電質335置於通道區域的三側。閘極電極340置於閘極介電質335上。選擇地,絕緣間隔層345與346鄰近閘極介電質335與閘極電極340。電晶體結構一般覆於絕緣介電層,其部分的繪示為絕緣區域350與351。
圖4A~B繪示具有應變奈米帶或奈米線通道區域之電晶體結構。一般而言,奈米線能夠被視為具有大約相等之寬度及高度,且奈米帶能夠被視為具有大於高度之寬度 (長度維度為沿著線或帶之長度的維度)。圖4B代表沿著旋轉45°之圖4A結構之4-4的視圖。在圖4A~B中,設置了基板405及由應變奈米帶或奈米線410所構成的通道區域。基板405例如由矽、鍺、SixGe1-x、在絕緣體上的矽、在絕緣體上的鍺、或III-V複合材料。在本發明實施例中,奈米線410由鍺、矽、鍺與矽的結合或是鍺、矽以及或錫(例如像是GexSiySn1-x-y)的結合組成。雖然四個奈米帶或奈米線410繪示於圖4A~B中,其它數目的奈米帶或奈米線410亦有可能,像是在電晶體中介於以及包括1與8條奈米帶或奈米線。其它數目的奈米帶或奈米線410亦有可能,像是多於8條奈米帶或奈米線410。
在圖4A中,源極與汲極區域420及425鄰近奈米帶或奈米線410的末端。源極與汲極區域420與425在奈米線或奈米帶410中創建壓縮或伸張應變並且由具有大於或小於(個別的)通道區域之者的晶格常數之材料組成。在本發明實施例中,源極與汲極區域420與425由摻雜III-V複合半導體材料(包含自周期表的IIIA族群與VA族群元素之材料)組成。在本發明實施例中,摻雜物包括鍺、碳、矽、鎂、鈹、錳以及或鋅。其它摻雜物亦有可能。在圖4A~B中,電晶體結構額外的包含閘極介電質435及閘極電極440。閘極介電質435置於奈米帶或奈米線410上。閘極電極440置於閘極介電質435上。閘極介電質435及閘極電極440以能夠說明為四周或360°的方式圍繞奈米帶或奈米線410。選擇地,絕緣間隔層445鄰近閘極 介電質435及閘極電極440。電晶體結構一般係覆於絕緣介電層,其部分的繪示為絕緣區域450。
相對於本發明實施例120、125、220、225、320、325、420及425(經由圖4A~B之圖1A~B)說明的源極與汲極區域由摻雜III-V複合半導體材料組成。在本發明進一步實施例中,源極與極極區域120、125、220、225、320、325、420及425由自下列族群中至少一個元素組成:B、Al、Ga及或是In以及自下列族群中至少一個元素組成:P、As及或是Sb。在額外的實施例中,源極與汲極區域120、125、220、225、320、325、420及425由具有自周期表的IIIA族群的至少一個元素以及自周期表的VA族群的至少一個元素組成。在本發明實施例中,源極與汲極區域120、125、220、225、320、325、420及425能夠包含III-V的三重(ternary)合金(三個元素的混合)或是III V四重(quaternary)合金(四個元素的混合)。在本發明實施例中,相對於通道區域之源極與汲極區域120、125、220、225、320、325、420及425之晶格應變不匹配係為來自1%至2%的無論何處(雖然其它值亦為可能)。在本發明實施例中,具有伸張應變的源極與汲極區域120、125、220、225、320、325、420及425由AlxIn1-xP(其中0.5<x<0.8)、GaxIn1-xP(其中0.5<x<0.8)、GaSbxP1-x(其中0.1<x<0.3)、AlSbxP1-x(其中0.1<x<0.3)、AlAsxP1-x(其中0.5<x<1)或是GaAsxP1-x(其中0.5<x<1)組成。在本發明進一步實施例 中,具有壓縮應變之源極與汲極區域120、125、220、225、320、325、420以及425由AlxIn1-xP(其中0.2<x<0.5)、GaxIn1-xP(其中0.2<x<0.5)、GaxIn1-xAs(其中0.7<x<1)、AlxIn1-xP(其中0.7<x<1)、GaSbxP1-x(其中0.3<x<0.5)、AlSbxP1-x(其中0.3<x<0.5)、GaAsxSb1-x(其中0.75<x<1)或是AlAsxSb1-x(其中0.75<x<1)組成。在本發明實施例中,用於源極與汲極的摻雜物包括鍺、碳、矽、鎂、鈹、錳以及或鋅。一般而言,在源極與汲極區域120、125、220、225、320、325、420及425中的摻雜物濃度能夠介於5e19與5e21atoms/cm3之間。
用於介電層、特徵及或是層間介電質(ILD;interlayer dielectrics)的一般介電材料包括二氧化矽(silicon dioxide)及低介電質(low k)介電材料。可被使用之介電材料例如包括碳摻雜氧化物(CDO;carbon doped oxide)、氮化矽(silicon nitride)、碳化矽(silicon carbide)、氮氧化矽(silicon oxynitride)、有機聚合物(organic polymers)(像是八氟環丁烷(perfluorocyclobutane)或是聚四氟乙烯(polytetrafluoroethylene))、氟矽玻璃(FSG;fluorosilicate glass)以及有機矽酸鹽(organosilicates)(像是半矽氧烷(silsesquioxane)、矽氧烷(siloxane))或碳化矽玻璃(organosilicate glass))。其它材料亦有可能。介電層可包括孔以進一步降低介電常 數。
閘極介電材料例如包括絕緣材料,諸如二氧化矽(SiO2)、氮氧化矽(SiOxNy)、氮化矽(Si3N4)以及或是高介電質(high-k)介電材料。一般而言,high-k介電質為具有大於SiO2之者的介電常數之介電材料。SiO2之介電常數為3.9。示範性high-k介電材料包括二氧化鉿(HfO2)、矽氧化鉿(hafnium silicon oxide)、氧化鑭(lanthanum oxide)、鋁鑭氧化物(lanthanum aluminum oxide)、二氧化鋯(ZrO2)、氧化矽鋯(zirconium silicon oxide)、二氧化鈦(TiO2)、五氧化二鉭(Ta2O5)、鋇鍶鈦氧化物(barium strontium titanium oxide)、鋇鈦氧化物(barium titanium oxide)、鍶鈦氧化物(strontium titanium oxide)、氧化釔(yttrium oxide)、氧化鋁(aluminum oxide)、鉛鈧鈦氧化物(lead scandium tantalum oxide)、鉛鋅鈮酸鹽(lead zinc niobate)及其它在半導體領域中已知的材料。閘極電極材料例如包括像是Ti、W、Ta、Al及其中的合金之材料,以及具有稀土元素的合金,諸如Er、Dy或是貴金屬(其像是Pt)與氮化物(像是TaN及TiN)。
在此繪示個別的電晶體可包含額外的結構,像是絕緣層,其包圍電晶體、金屬溝槽及將源極與汲極連接至其它組件的連接點(vias)及其它額外的層以及或是組件。取決於例如施用在建構裝置及理想的裝置性質中的製程,闡述為用於簡化的一層之組件能夠包含相同或不同材料之複 數個層。
本發明實施例能夠使用標準半導體處理技術來完成。例如使用分子束磊晶(MBE;molecular beam epitaxy)、化學汽相沈積(CVD;chemical vapor deposition)、有機金屬氣相磊晶(MOVPE;metalorganic vapor phase epitaxy)、有機金屬化學氣相沈積(MOCVD;metal organic chemical vapor deposition)、快速加熱化學氣相沈積(RTCVD;rapid thermal chemical vapor deposition)或是超高真空CVD(UHV CVD;ultra high-vacuum chemical vapor deposition)完成了包含摻雜III-V複合半導體材料之源極與汲極區域。
一般來說,圖1A~B至圖4A~B的電晶體結構為一部分的積體電路晶片且整合至積體電路晶片中,其組件為了闡述之明確而未繪示。本發明的實現係安置於基板上,像是半導體基板。依據本發明實施例電晶體構造於其上的基板能夠形成例如包括氫端鍵結矽(H terminated silicon)、二氧化矽、矽、矽化鍺、III-V族群(或是於額外的周期表欄位編號圖表之13-14族群)複合半導體、主族群氧化物(main group oxide)、金屬以及或是二元或混合金屬氧化物。額外的層及/或包含裝置的層亦能說明為其上製造有本發明實施例的基板或部分的基板。基於建有半導體裝置之基板一般為半導體晶圓,其分切成塊以產出個別IC晶片。雖然本發明實施例並未取決於所使用基板的類型,但晶片建於其上的基底基板一般為矽晶圓。 基板亦能由其單獨本身或是與矽或二氧化矽或其它絕緣材料結合之鍺(germanium)、銻化銦(indium antimonide)、碲化鉿(lead telluride)、砷化銦(indium arsenide)、磷化銦(indium phosphide)、砷化鎵(gallium arsenide)、銻化鎵(gallium antimonide)以及或是其它III-V族群材料組成。
圖5闡述依據本發明的實現之計算裝置1000。計算裝置1000內置有主機板1002。主機板1002可包括一些組件,包括但不限於處理器1004及至少一個通訊晶片1006。處理器1004實體上及電性上耦接至主機板1002。在一些實現中,至少一個通訊晶片1006亦實體上及電性上耦接至主機板1002。
取決於其應用,計算裝置1000可包括其它組件,其可或不可實體上及電性上耦接至主機板1002。這些其它組件包括(但不限於此)揮發性記憶體(例如DRAM)、非揮發性記憶體(例如ROM)、圖形處理器、數位信號處理器、密碼處理器(crypto processor)、晶片組、天線、顯示器、觸碰螢幕顯示器、觸碰螢幕控制器、電池、音頻編解碼器(audio codec)、視頻編解碼器(video codec)、功率放大器、全球定位系統(GPS;global positioning system)裝置、羅盤、加速度計、陀螺儀(gyroscope)、揚聲器、相機以及大量儲存裝置(諸如硬碟驅動機(hard disk drive)、光碟(CD;compact disk)、數位多功能光碟(DVD;digital versatile disk) 等等)。
通訊晶片1006致能用於到達及來自計算裝置1000之資料傳遞之無線通訊。詞彙「無線」及其衍生可用以說明電路、裝置、系統、方法、技術、通訊通道等,其透過經由非固態(non-solid)媒體之調變的電磁放射之使用可通傳資料。此詞彙並非暗示關聯的裝置並沒有包含任何導線(雖然在一些實施例中他們也許是沒有)。通訊晶片1006可實現任何若干無線標準或協定,其包括但不限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演進(LTE;long term evolution)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙(Bluetooth)及其中的衍生以及任何其它指定為3G、4G、5G及超過之無線協定。計算裝置1000可包括複數個通訊晶片1006。例如,第一通訊晶片1006可專屬於較短範圍無線通訊,像是Wi-Fi及藍牙,並且第二通訊晶片1006可專屬於較長範圍無線通訊,像是GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO以及其它。
計算裝置1000之處理器1004包括封裝在處理器1004內之積體電路晶粒。在一些本發明之實現中,處理器的積體電路晶粒包括一或多個裝置,像是電晶體,其依據本發明之實現形成。詞彙「處理器」可參照至任何裝置或裝置的部分,其自暫存器及/或記憶體處理電子資料以轉換電子資料至其它可存儲在暫存器及/或記憶體中之電 子資料。
通訊晶片1006亦包括封裝在通訊晶片1006內之積體電路晶粒。依據另一個本發明的實現,通訊晶片之積體電路晶粒包括一或多個裝置,像是電晶體,其依據本發明之實現形成。
在進一步的實現中,內置在計算裝置1000內的另一個組件可包含積體電路晶粒,其包括一或多個裝置,像是電晶體,其依據本發明的實現形成。
在各種實現中,計算裝置1000可為膝上型電腦(laptop)、上網本(netbook)、筆記型電腦(notebook)、智慧型手機、平板電腦(tablet)、個人數位助理(PDA;personal digital assistant)、超級行動個人電腦(ultra mobile PC)、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒(set-top box)、娛樂控制單元(entertainment control unit)、數位相機、可攜式音樂播放器或數位視頻錄影機(digital video recorder)。在進一步實現中,計算裝置1000可為任何其它處理資料的電子裝置。
在先前的說明中,為了提供本發明實施例的全面了解,提出許多特定的細節,像是用於電晶體及材料體系的佈局。對於本領域具有通常知識者將顯而易見的是本發明之實施例可不以這些特定細節來實作。在其它例子中,由於不必要模糊本發明之實施例,熟知的特徵(像是用於電晶體與積體電路設計佈局之電性連接方案)並未詳細說 明。進一步來說,可了解的是各種繪示在圖式中的實施例係為說明的代表且不必要按比例繪製。
在相關領域具有通常知識者了解貫穿本揭露及結合以及對於各種顯示與說明的組件之代換而進行修改及變化是可能的。遍佈本說明書而參照至有關實施例所說明的「一個實施例」或「一實施例」意味特定的特徵、結構、材料或特性包括在至少一個本發明的實施例,但不需代表他們出現在每個實施例中。此外,揭露在實施例中的特定的特徵、結構、材料或特性可在一或多個實施例中以任何合適的方法組合。可包括各種額外的層及/或結構及/或所說明的特徵可在其它實施例中省略。
105‧‧‧基板
110‧‧‧隔離溝槽
115‧‧‧通道區域
120‧‧‧源極區域
125‧‧‧汲極區域
130‧‧‧閘極電極區域
135‧‧‧閘極介電區域
140‧‧‧選擇的絕緣間隔層

Claims (28)

  1. 一種半導體裝置,包含:第一區域與第二區域,其中該第一區域與該第二區域包含摻雜III-V複合半導體材料,以及該摻雜III-V複合半導體材料包含一或多個來自周期表III族群之元素以及一或多個來自周期表V族群之元素,第三區域,配置於該第一區域與該第二區域之間,其中該第一區域與該第二區域的該摻雜III-V複合半導體材料造成在該第三區域中的應變,閘極介電材料,配置在該第三區域的至少二側,以及閘極電極材料,配置在該閘極介電質上。
  2. 如申請專利範圍第1項之半導體裝置,其中該第三區域包含鍺。
  3. 如申請專利範圍第1項之半導體裝置,其中該第三區域包含鍺與矽的結合或是鍺、矽及錫的結合。
  4. 如申請專利範圍第1項之半導體裝置,其中該第三區域包含矽。
  5. 如申請專利範圍第1項之半導體裝置,其中該一或多個來自周期表族群III的元素選自由B、Al、Ga及In組成的族群,並且該一或多個來自周期表族群V的元素選自由P、As及Sb組成的族群。
  6. 如申請專利範圍第1項之半導體裝置,其中該第一區域與該第二區域包含具有0.5<x<0.8的AlxIn1-xP、具有0.5<x<0.8的GaxIn1-xP、具有0.1<x<0.3的GasbxP1-x、具 有01<x<0.3的AlSbxP1-x、具有0.5<x<1的AlAsxP1-x或具有0.5<x<1的GaAsxP1-x
  7. 如申請專利範圍第1項之半導體裝置,其中該第一區域與該第二區域包含具有介於0.2與0.5之間的x的AlxIn1-xP、具有介於0.2與0.5之間的x的GaxIn1-xP、具有介於0.7與1之間的x的GaxIn1-xAs、具有介於0.7與1之間的x的AlxIn1-xP、具有介於0.3與0.5之間的x的GaSbxP1-x、具有介於0.3與0.5之間的x的AlSbxP1-x、具有介於0.75與1之間的x的GaAsxSb1-x或具有介於0.75與1之間的x的AlAsxSb1-x
  8. 如申請專利範圍第1項之半導體裝置,其中該第三區域為拉伸應變。
  9. 如申請專利範圍第1項之半導體裝置,其中該第三區域為壓縮應變。
  10. 如申請專利範圍第1項之半導體裝置,其中該第一區域與該第二區域係摻雜以鍺、碳、矽、鎂、鈹、錳或鋅。
  11. 如申請專利範圍第1項之半導體裝置,其中該第三區域包含奈米線或奈米帶。
  12. 如申請專利範圍第1項之半導體裝置,進一步包含鄰接該閘極電極材料的絕緣間隔件。
  13. 如申請專利範圍第1項之半導體裝置,其中該半導體裝置為電晶體。
  14. 一種半導體裝置,包含: 第一區域;第二區域與第三區域,其中該第二區域與該第三區域包含III-V複合半導體材料,該III-V複合半導體材料包含一或多個來自周期表的III族群元素以及一或多個來自周期表的V族群元素,其中該第二區域與該第三區域的該III-V複合半導體材料造成在該第一區域中的應變,閘極介電材料,配置在該第三區域,閘極電極材料,配置在該閘極介電材料上,以及間隔件材料,鄰接該閘極電極材料。
  15. 如申請專利範圍第14項之半導體裝置,其中該第一區域包含鍺與矽的結合或是鍺、矽及錫的結合。
  16. 如申請專利範圍第14項之半導體裝置,其中該第一區域包含矽。
  17. 如申請專利範圍第14項之半導體裝置,其中該一或多個來自周期表之族群III的元素選自由B、Al、Ga及In所組成的族群,並且該一或多個來自周期表之族群V的元素選自由P、As及Sb組成的族群。
  18. 如申請專利範圍第14項之半導體裝置,其中該第二區域與該第三區域包含具有0.5<x<0.8的AlxIn1-xP、具有0.5<x<0.8的GaxIn1-xP、具有0.1<x<0.3的GaSbxP1-x、具有0.1<x<0.3的AlSbxP1-x、具有0.5<x<1的AlAsxP1-x或具有0.5<x<1的GaAsxP1-x
  19. 如申請專利範圍第14項之半導體裝置,其中該第二區域與該第三區域包含具有介於0.2與0.5之間的x的 AlxIn1-xP、具有介於0.2與0.5之間的x的GaxIn1-xP、具有介於0.7與1之間的x的GaxIn1-xAs、具有介於0.7與1之間的x的AlxIn1-xP、具有介於0.3與0.5之間的x的GaSbxP1-x、具有介於0.3與0.5之間的x的AlSbxP1-x、具有介於0.75與1之間的x的GaAsxSb1-x或具有介於0.75與1之間的x的AlAsxsb1-x
  20. 如申請專利範圍第14項之半導體裝置,其中該第二區域與該第三區域係配置接近於該第一區域的兩個不同的分離區域。
  21. 如申請專利範圍第20項之半導體裝置,其中該第一區域的該等兩個不同的分離區域包含奈米帶或奈米線,以及該閘極電極材料係配置於奈米帶或奈米線附近。
  22. 一種計算裝置,包含:記憶體裝置;以及處理裝置,耦接至該記憶體裝置,其中該處理器裝置包括:第一區域與第二區域,包含III-V複合半導體材料,其中該III-V複合半導體材料包含一或多個來自周期表之族群III的元素以及一或多個來自周期表之族群V的元素,第三區域,介於該第一區域與該第二區域之間,其中該第三區域的第一端鄰接第一區域,該第三區域的第二端鄰接該第二區域,以及該III-V複合半導體材料具有與該第三區域的材料的晶格失配, 閘極介電材料,配置於該第三區域上,以及閘極電極材料,配置於該閘極介電質上。
  23. 如申請專利範圍第22項之計算裝置,其中該一或多個來自周期表族群III的元素選自由B、Al、Ga及In組成的族群,並且該一或多個來自周期表族群V的元素選自由P、As及Sb組成的族群。
  24. 如申請專利範圍第22項之計算裝置,其中該第一區域與該第二區域包含AlxIn1-xP,其中0.5<x<0.8、包含GaxIn1-xP,其中0.5<x<0.8、包含GaSbxP1-x,其中0.1<x<0.3、包含AlSbxP1-x,其中0.1<x<0.3、包含AlAsxP1-x,其中0.5<x<1或包含GaAsxP1-x,其中0.5<x<1。
  25. 如申請專利範圍第22項之計算裝置,其中該第一區域與該第二區域包含AlxIn1-xP,其中x介於0.2與0.5之間、包含GaxIn1-xP,其中x介於0.2與0.5之間、包含GaxIn1-xAs,其中x介於0.7與1之間、包含AlxIn1-xP,其中x介於0.7與1之間、包含GaSbxP1-x,其中x介於0.3與0.5之間、包含AlSbxP1-x,其中x介於0.3與0.5之間、包含GaAsxSb1-x,其中x介於0.75與1之間或包含AlAsxSb1-x,其中x介於0.75與1之間。
  26. 如申請專利範圍第22項之計算裝置,其中該第三區域包括複數個奈米線或奈米帶。
  27. 如申請專利範圍第26項之計算裝置,其中該複數個奈米線或奈米帶係懸掛在該第一區域與該第二區域之 間。
  28. 如申請專利範圍第22項之計算裝置,其中該第三區域為應變的。
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