CN112992787A - 半导体器件和形成半导体器件的方法 - Google Patents

半导体器件和形成半导体器件的方法 Download PDF

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CN112992787A
CN112992787A CN202011313544.5A CN202011313544A CN112992787A CN 112992787 A CN112992787 A CN 112992787A CN 202011313544 A CN202011313544 A CN 202011313544A CN 112992787 A CN112992787 A CN 112992787A
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layer
dielectric
transition metal
gate
metal dichalcogenide
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苏圣凯
蔡劲
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

方法包括：蚀刻介电层以形成介电鳍；在介电鳍上沉积过渡金属二硫属化物层；以及对过渡金属二硫属化物层实施各向异性蚀刻工艺。去除过渡金属二硫属化物层的水平部分，并且保留位于介电鳍的侧壁上的过渡金属二硫属化物层的垂直部分以形成垂直半导体环。该方法还包括：在二维半导体垂直半导体环的第一部分上形成栅极堆叠件；以及形成源极/漏极接触插塞，其中，源极/漏极接触插塞接触垂直半导体环的第二部分的侧壁。本申请的实施例还涉及半导体器件和形成半导体器件的方法。

Description

半导体器件和形成半导体器件的方法
技术领域
本申请的实施例涉及半导体器件和形成半导体器件的方法。
背景技术
半导体器件用于各种电子应用(诸如个人计算机、手机、数码相机和其他电子设备)中。通常通过以下方式制造半导体器件：依次在半导体衬底上方沉积材料的绝缘或介电层、导电层和半导体层，并且使用光刻工艺图案化各个材料层以在其上形成电路组件和元件。
半导体工业通过不断减小最小部件尺寸来不断改善各个电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这使得更多的组件可以集成至给定区域中。然而，随着减小最小部件尺寸，出现了应该解决的额外问题。
发明内容
本申请的一些实施例提供了一种形成半导体器件的方法，包括：蚀刻介电层以形成介电鳍；在所述介电鳍上沉积过渡金属二硫属化物层；对所述过渡金属二硫属化物层实施第一各向异性蚀刻工艺，其中，去除所述过渡金属二硫属化物层的水平部分，并且保留位于所述介电鳍侧壁上的所述过渡金属二硫属化物层的垂直部分以形成垂直半导体环；在所述垂直半导体环的第一部分上形成栅极堆叠件；以及形成源极/漏极接触插塞，其中，所述源极/漏极接触插塞接触所述垂直半导体环的第二部分的侧壁。
本申请的另一些实施例提供了一种半导体器件，包括：介电鳍；过渡金属二硫属化物层，位于所述介电鳍的侧壁上；栅极堆叠件，位于所述介电鳍和所述过渡金属二硫属化物层上，其中，所述栅极堆叠件接触所述过渡金属二硫属化物层的侧壁的第一部分；栅极间隔件，接触所述栅极堆叠件；以及源极/漏极接触插塞，接触所述过渡金属二硫属化物层的侧壁的第二部分。
本申请的又一些实施例提供了一种半导体器件，包括：介电层；介电鳍，位于所述介电层上方；二维半导体材料，形成环绕并且接触所述介电鳍的侧壁的环；栅极电介质，接触所述介电鳍和所述介电层的顶面，并且还接触所述二维半导体材料；栅电极，位于所述栅极电介质上方，其中，所述二维半导体材料包括位于所述栅电极的相对侧上的源极部分和漏极部分；以及源极/漏极接触插塞，接触所述二维半导体材料的所述源极部分和所述漏极部分中的一个。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A、图1B、图1C、图2A、图2B、图2C、图3A、图3B、图3C、图4A、图4B、图4C、图5A、图5B、图5C、图6A、图6B、图6C、图7A、图7B、图7C、图8A、图8B、图8C、图9A、图9B、图9C、图10A、图10B、图10C、图11A、图11B、图11C和图11D示出了根据一些实施例的在包括二维材料的三维晶体管的形成中的中间阶段的平面图和截面图。
图12示出了根据一些实施例的三维晶体管的部分的截面图。
图13示出了根据一些实施例的二维材料的单层。
图14示出了根据一些实施例的若干类型的晶体管的最小沟道长度与沟道宽度方向尺寸。
图15示出了根据一些实施例的用于形成包括二维材料的三维晶体管的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下面”、“在…下方”、“下部”、“在…上面”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，提供了由二维(2D)半导体材料形成的三维(3D)晶体管及其形成方法。根据本发明的一些实施例，3D晶体管包括介电鳍，在介电鳍的侧壁上形成2D半导体材料。本文讨论的实施例将提供实例以使得能够进行或使用本发明的主题，并且本领域普通技术人员将容易理解可以进行的修改，同时保持在不同实施例的预期范围内。贯穿各个视图和说明性实施例，相同的参考标号用于指示相同的元件。虽然可以讨论为以具体顺序实施方法实施例，但是可以以任何逻辑顺序实施其他方法实施例。
图1A、图1B、图1C、图2A、图2B、图2C、图3A、图3B、图3C、图4A、图4B、图4C、图5A、图5B、图5C、图6A、图6B、图6C、图7A、图7B、图7C、图8A、图8B、图8C、图9A、图9B、图9C、图10A、图10B、图10C、图11A、图11B、图11C和图11D示出了根据一些实施例的在使用二维材料的三维晶体管的形成中的中间阶段的平面图和截面图。对应的工艺也示意性地反映在图15所示的工艺流程中。贯穿本发明，附图编号随后可以是字母“A”、“B”或“C”，其中字母“A”表示相应的视图是平面图(顶视图)，字母“B”表示从相应的平面图中的参考截面B-B获得相应的附图，并且字母“C”表示从相应平面图中的参考截面C-C获得相应的附图。例如，图1B示出了图1A中的参考截面B-B，并且图1C示出了图1A中的参考截面C-C。
参考图1A、图1B和图1C，提供了包括衬底20的晶圆10。根据本发明的一些实施例，衬底20可以是半导体衬底，诸如块状半导体衬底、绝缘体上半导体(SOI)衬底等。衬底20可以是掺杂的(例如，用p型或n型掺杂物质)或未掺杂的。半导体衬底20可以是晶圆10的一部分，诸如硅晶圆。通常，SOI衬底是形成在绝缘层上的半导体材料层。绝缘层可以是例如埋氧(BOX)层、氧化硅层等。在通常为硅或玻璃衬底的衬底上提供绝缘层。也可以使用其他衬底，诸如多层或梯度衬底。在一些实施例中，半导体衬底20的半导体材料可以包括硅；锗；化合物半导体，包括掺杂碳的硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、碳掺杂的硅、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。
在衬底20上方形成隔离层22。相应的工艺示出为图15所示的工艺流程200中的工艺202。根据本发明的一些实施例，隔离层22与衬底20物理接触。根据本发明的可选实施例，在隔离层22和衬底20之间，可以存在其他层和器件，包括但不限于介电层、金属部件等。例如，可以存在层间电介质、金属间电介质(可以包括低k介电层)和/或等。可以存在或可以不存在形成在隔离层22和衬底20之间的诸如无源器件(电容器、电阻器、电感器等)和/或有源器件(晶体管、二极管等)的集成电路器件。
根据本发明的一些实施例，隔离层22包括或由氮化物(诸如氮化硅)、氧化物(诸如氧化硅)、氟化氧硅(SiOF)、碳化氧硅(SiOC)等或高k介电材料(诸如氧化铝、氧化铪、氧化锆、氧化镧等)形成。隔离层22可以是晶体层(单晶或多晶)或非晶层。隔离层22可以具有单层结构或包括多层的复合结构。例如，隔离层22可以包括双层结构、三层结构等。双层结构可以包括由不同材料形成的两层，例如，氧化硅层和位于氧化硅层上方的氮化硅层。根据本发明的一些实施例，隔离层22的厚度T1(图1B和图1C)在约5nm和约20nm之间的范围内。
隔离层22的形成工艺可以包括一个或多个沉积工艺，包括例如等离子体增强化学汽相沉积(PECVD)工艺、等离子体增强原子层沉积(PEALD)工艺、原子层沉积(ALD)工艺、化学汽相沉积(CVD)工艺等。根据本发明的一些实施例，例如，当隔离层22包括氧化硅并且当衬底20包括或由硅形成时，也可以通过热氧化、化学氧化等形成隔离层22。
在隔离层22上方形成介电层24。相应的工艺示出为图15所示的工艺流程200中的工艺204。介电层24由与隔离层22的材料不同的材料形成。根据本发明的一些实施例，介电层24包括或由氧化物(诸如氧化硅、氟氧化硅(SiOF)、碳氧化硅(SiOC)等)形成。介电层24可以由非高k材料形成，并且也可以由k值小于3.8的低k介电层形成。k值也可以小于约3.5或小于约3.0。使用低k介电层具有减小所得晶体管中的漏极区域与沟道区域的耦接的有利特征，这将在随后的段落中进行讨论。介电层24可以是多孔的，包括小孔以具有减小的k值。根据本发明的一些实施例，使用CVD、ALD、PEALD、PECVD等形成介电层24。根据本发明的一些实施例，介电层24的厚度T1(图1C)在约20nm和约60nm之间的范围内。
在介电层24上方形成可以是图案化的光刻胶的图案化的蚀刻掩模26。如图1A所示，图案化的蚀刻掩模26可包括多个细长带。应该理解，虽然示出了两个细长带，根据其形成晶体管，但是根据其他实施例，可以存在单个带、三个带、四个带或更多个用于形成晶体管。
然后，图案化的蚀刻掩模26用于蚀刻介电层24。相应的工艺示出为图15所示的工艺流程200中的工艺206。因此，如图2A、图2B和图2C所示，形成介电鳍24’。使用各向异性蚀刻工艺实施蚀刻。在蚀刻工艺中，隔离层22用作蚀刻停止层。根据本发明的一些实施例，介电鳍24’的宽度W1(图2B)在约3nm和约10nm之间的范围内。介电鳍24’的高度H1可以在约20nm和约60nm之间的范围内。
参考图3A、图3B和图3C，通过沉积形成半导体层28。相应的工艺示出为图15所示的工艺流程200中的工艺208。根据本发明的一些实施例，半导体层28由也被称为范德华材料的2D材料形成。2D材料包括一个或多个单层。在单层内形成强结合(诸如共价结合)，以使相同单层中的原子彼此结合。相邻单层之间的结合力是范德华力，这是一个弱力。因此，虽然半导体层28可以包括多于一个的单层，但是半导体可以作为范德华材料。半导体层28的厚度T3和T4可以小于约5nm，并且可以在约0.5nm和约5nm之间的范围内，或在约0.7nm和约3nm之间的范围内。
根据本发明的一些实施例，半导体层28包括或由过渡金属二硫属化物(TMD)材料(包括过渡金属和VIA族元素的化合物)形成。过渡金属可以包括W、Mo、Ti、V、Co、Ni、Zr、Tc、Rh、Pd、Hf、Ta、Re、Ir、Pt等。VIA族元素可以是硫(S)、硒(Se)、碲(Te)等。例如，半导体层28可以包括或由MoS2、MoSe2、WS2、WSe2等形成。
图13示出了示例性半导体层28的部分，作为实例示出两个单层30，但是单层的总数可以更大或更小。根据本发明的一些实施例，过渡金属原子32在中间形成层，并且VIA族原子33在过渡金属原子32的层下面形成第一层，并且在过渡金属原子32的层上方形成第二层。如上所述，过渡金属原子32可以是W原子、Mo原子、Ti原子等，并且如上所述，VIA族原子33可以是S原子、Se原子、Te原子等。过渡金属原子32中的每个结合至四个VIA族原子33，并且VIA族原子33中的每个结合至两个过渡金属原子32。过渡金属原子32的一层和VIA族原子33的两层的组合称为TMD材料的单层30。过渡金属原子32和VIA族原子33之间的结合为共价结合，并且单层30之间的结合通过范德华力。
再次参考图3A、图3B和图3C，根据本发明的一些实施例，半导体层28是共形层，垂直部分的厚度T3(图3B和图3C)和水平部分的厚度T4彼此接近，例如，差值小于厚度T3和T4中任一个的约20％(或10％或更小)。根据本发明的一些实施例，使用CVD沉积半导体层28，MoO3粉末和硫(或Se)粉末作为前驱体，并且氮(N2)作为载气。MoO3粉末和Se粉末中的每个的流速可以在约5sccm和约100sccm之间的范围内。根据本发明的可选实施例，使用PECVD或另一适用的方法。根据本发明的一些实施例，沉积温度可以在约750℃和约1,000℃之间，并且可以使用更高或更低的温度。沉积持续时间可以在约10分钟和约1小时的范围内。控制工艺带件以实现所需的单层总数。根据本发明的一些实施例，半导体层28包括1个(单个单层)和约4个之间的单层，同时可以形成更多的单层。相应地，厚度T3和T4可以在约0.7nm(对应于单个单层)和约3nm(对应于四个单层)之间的范围内。
根据一些实施例，半导体层28可以掺杂有阱掺杂。例如，当所得晶体管62是p型晶体管时，通过掺杂例如钾(K)将半导体层28掺杂为n型。当所得晶体管62是n型晶体管时，通过例如使用NO2掺杂将半导体层28掺杂为p型。
图4A、图4B和图4C示出了垂直半导体环28’的形成的平面图和截面图，该垂直半导体环通过对半导体层28实施各向异性蚀刻工艺形成。相应的工艺示出为图15所示的工艺流程200中的工艺210。根据本发明的一些实施例，使用包括Ar、SF6等的蚀刻气体实施蚀刻，在蚀刻中生成等离子体。由于各向异性蚀刻工艺，去除如图3B和图3C所示的半导体层28的水平部分，同时在蚀刻工艺之后，位于介电鳍24’的侧壁上的半导体层28的垂直部分仍然保留。由于各向异性蚀刻，垂直半导体环28’的顶部边缘可以具有倾斜的顶面(边缘)24SW。在随后的附图中，未示出倾斜的顶部边缘，同时它们仍可能存在于如图11A、图11B、图11C和图11D所示的最终的晶体管62中。垂直半导体环28’的最顶部尖端可以低于或与介电鳍24’的顶面处于相同的高度。在图4A所示的顶视图中，垂直半导体环28’具有环绕相应介电鳍24’的全环的形状。
随后的附图示出了根据一些实施例的晶体管的额外部件的形成。所示的工艺是先栅极工艺，其中在晶体管的源极/漏极区域的形成之前形成晶体管的栅极堆叠件。根据本发明的可选实施例，可以采用后栅极工艺，其中形成伪栅极堆叠件，并且随后用替换栅极堆叠件替换。
参考图5A、图5B和图5C，沉积栅极介电层34。相应的工艺示出为图15所示的工艺流程200中的工艺212。根据本发明的一些实施例，沉积的栅极介电层34和栅电极层36用于形成伪栅极堆叠件。例如，栅极介电层34可以由氧化硅形成。根据其他实施例，当栅极介电层34是伪栅极电介质时，不形成栅极介电层34。可以例如使用多晶硅形成栅电极层36，并且也可以使用其他材料。
根据本发明的一些实施例，沉积的栅极介电层34和栅电极层36用于形成实际的栅极堆叠件，其存在于最终的晶体管62中(图11A、图11B、图11C和图11D)。因此，栅极介电层34可以包括氧化硅、高k介电材料(诸如HfO2、ZrO2、HfZrOx、HfSiOx、HfSiON、ZrSiOx、HfZrSiOx、Al2O3、HfAlOx、HfAlN、ZrAlOx、La2O3、TiO2、Yb2O3、氮化硅等)或它们的复合层。例如，栅极介电层34可以包括氧化硅层和位于该氧化硅层上方的高k介电层。
在栅极介电层34上方形成栅电极层36。相应的工艺示出为图15所示的工艺流程200中的工艺214。栅电极层36可以包括一个或多个层。根据本发明的一些实施例，栅电极层36可以具有扩散阻挡层、位于扩散阻挡层上方的功函层、位于功函层上方的覆盖层，并且可以包括或可以不包括位于覆盖层上方的填充金属区域。扩散阻挡层可以包括或由TiN、TiSiN等形成。功函层可包括或由根据相应的晶体管是n型晶体管还是p型晶体管选择的材料形成。可以形成由金属或金属合金(诸如钨、钴等)形成的金属层以形成填充金属区域。根据其他实施例，栅电极层36包括多晶硅。
然后在图案化工艺中图案化栅极介电层34和栅电极层36，从而形成如图6A、图6B和图6C所示的栅极堆叠件38。相应的工艺示出为图15所示的工艺流程200中的工艺216。图案化的栅极介电层34的剩余部分称为栅极电介质34’，并且图案化的栅电极层36的剩余部分称为栅电极36’。栅极电介质34’和栅电极36’统称为栅极堆叠件38。如图6A所示，在实例中，栅极堆叠件38覆盖垂直半导体环28’中的每个的部分，并且使垂直半导体环28’的相对端部暴露。应该理解，虽然示出了一个栅极堆叠件38，但是可以在介电鳍24’和垂直半导体环28’上形成多个栅极堆叠件38，多个栅极堆叠件38彼此平行。多个栅极堆叠件38彼此间隔开，在垂直半导体环28’和介电鳍24’中的每个的一部分上形成每个栅极堆叠件，并且使垂直半导体环28’和介电鳍24’的其他部分暴露。
图7A、图7B和图7C示出了在栅极堆叠件38的侧壁上的栅极间隔件40的形成。相应的工艺示出为图15所示的工艺流程200中的工艺218。根据本发明的一些实施例，栅极间隔件40由介电材料(诸如氮化硅、氧化硅、碳氮化硅等)形成，并且可以具有包括多个介电层的单层结构或多层结构。栅极间隔件40的形成可以包括：沉积毯式间隔件层，以及实施各向异性蚀刻工艺以去除间隔件层的水平部分。由于在垂直半导体环28’的侧壁上可能剩下间隔件层的一些部分(示意性示为40’)，因此可以实施额外的蚀刻工艺以去除不期望的部分40’。间隔件部分40’的去除可以包括：形成蚀刻掩模42(诸如图案化的光刻胶)以覆盖栅极间隔件40和栅极堆叠件38，以及实施各向同性蚀刻工艺以去除垂直半导体环28’的侧壁上的不期望的间隔件40’。由于蚀刻不期望的间隔件40’，垂直半导体环28’的整个侧壁表面(包括靠近隔离层22的底部)被暴露。这将有利地增大随后形成的源极/漏极接触插塞和垂直半导体环28’之间的接触面积。然后去除蚀刻掩模42，如果形成的话。
根据本发明的一些实施例，掺杂垂直半导体环28’的暴露部分以形成源极/漏极区域43。当所得的晶体管是n型晶体管时，通过掺杂例如钾将垂直半导体环28’的暴露部分掺杂为n型。当所得的晶体管是p型晶体管时，通过掺杂例如NO2，将垂直半导体环28’的暴露部分掺杂为p型。
图8A、图8B和图8C示出了接触蚀刻停止层(CESL)44的形成之后的结构。相应的工艺示出为图15所示的工艺流程200中的工艺220。CESL 44可以由氧化硅、氮化硅、碳氮化硅等形成，并且可以使用CVD、ALD等形成。如图8C所示，CESL 44形成为共形层，并且可以与垂直半导体环28’的侧壁物理接触。此外，CESL 44可以与介电鳍24’的顶面物理接触。
图8A、图8B和图8C还示出了层间电介质(ILD)46的形成。相应的工艺示出为图15所示的工艺流程200中的工艺222。ILD 46可以包括使用例如FCVD、旋涂、CVD或另一沉积方法形成的介电材料。ILD 46可以由含氧的介电材料形成，可以是基于氧化硅的材料，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)等。可以实施平坦化工艺(诸如CMP工艺或机械研磨工艺)以使ILD 46的顶面水平。根据本发明的一些实施例，如图8B和图8C所示，在暴露CESL 44之前，平坦化工艺停止，并且ILD 46的层保留在CESL 44上方。根据本发明的可选实施例，可以实施平坦化，直至暴露栅极堆叠件38和栅极间隔件40，并且虚线48画出为示出停止平坦化工艺的示例性位置。
根据其中栅极堆叠件38是伪栅极堆叠件的一些实施例，可以在位置48处停止平坦化工艺，并且用替换栅极堆叠件38’替换伪栅极堆叠件38，其在图12中作为实例示出。替换工艺可以包括：实施蚀刻工艺以去除伪栅极堆叠件38，在相对的栅极间隔件40之间形成沟槽，沉积延伸至沟槽中的介电层和栅电极层(可以包括多个层)，以及实施平坦化工艺以去除过量的材料。所得的替换栅极电介质34”和栅电极36”(图12)的材料可以在对栅极介电层34和栅电极层36的讨论中找到，并且在此不再重复。
图9A、图9B和图9C示出了栅极接触开口50和源极/漏极接触开口52的形成。相应的工艺示出为图15所示的工艺流程200中的工艺224。形成工艺包括各向异性蚀刻工艺。使用CESL 44作为蚀刻停止层实施蚀刻。因此，位于垂直半导体环28’的侧壁上的CESL 44部分和位于介电鳍24’顶部上的CESL 44的水平部分暴露于源极/漏极接触开口52。
参考图10A、图10B和图10C，去除CESL 44的暴露部分以使栅极接触开口50和源极/漏极接触开口52向下延伸。相应的工艺示出为图15所示的工艺流程200中的工艺226。根据本发明的一些实施例，通过各向同性蚀刻工艺(可以是湿蚀刻工艺或干蚀刻工艺)实施蚀刻。结果，暴露垂直半导体环28’的整个侧壁表面(包括靠近隔离层22的底部)。
图11A、图11B、图11C和图11D示出了在栅极接触插塞54和源极/漏极接触插塞56的形成中的平面图和截面图。相应的工艺示出为图15所示的工艺流程200中的工艺228。该形成可以包括：沉积一个或多个导电层以填充栅极接触开口50和源极/漏极接触开口52，以及实施平坦化工艺以去除ILD 46上方过量的材料，留下栅极接触插塞54和源极/漏极接触插塞56。根据本发明的一些实施例，栅极接触插塞54和源极/漏极接触插塞56的整体由均质的导电材料(可以是金属或包括钨、钴、铝等的金属合金或它们的合金)形成。根据本发明的可选实施例，栅极接触插塞54和源极/漏极接触插塞56中的每个包括粘合层57A和位于粘合层上方的均质导电材料57B。粘合层57A可以包括或由钛、氮化钛、钽、氮化钽等形成。均质导电材料还可以是包括钨、钴、铝等的金属或金属合金或它们的合金。
图11D还示出了图11A中的参考截面D-D。如图11C和图11D所示，源极/漏极接触插塞56通过边缘接触件与垂直半导体环28’的侧壁接触，并且垂直半导体环28’中的每个的接触面积等于H1×(2L1+W1)(图11A)，其中高度H1在图11C中示出，而长度L1和宽度W1在图11A中示出。因此，接触插塞与对应的源极/漏极区域的接触面积较大，而接触电阻较小。
参考图11C，根据本发明的一些实施例，源极/漏极接触插塞56具有与栅极间隔件40的侧壁接触的侧壁。因此，最大化L1的值(图11A)。这可以使源极/漏极接触插塞56与源极/漏极区域43之间的接触面积最大化，并且因此导致源极/漏极接触电阻的减小。根据本发明的可选实施例，源极/漏极接触插塞56与相应的最近的栅极间隔件40间隔开以增大工艺裕度。例如，图12示出了其中源极/漏极接触插塞56与栅极间隔件40间隔开的实施例。
图12示出了根据可选实施例的图11A中的参考截面D-D。这些实施例类似于图11C所示的实施例，除了形成替换栅极堆叠件38’外，当栅极堆叠件38是伪栅极堆叠件时，该替换栅极堆叠件38’替换如图5A、图5B和图5C所示的栅极堆叠件38。替换栅极堆叠件38’包括替换栅极电介质34”和栅电极36”。替换栅极电介质可以包括氧化硅层，并且可以包括位于氧化硅层上方的高k介电层。高k介电层可以包括HfO2、ZrO2、HfZrOx、HfSiOx、HfSiON、ZrSiOx、HfZrSiOx、Al2O3、HfAlOx、HfAlN、ZrAlOx、La2O3、TiO2、Yb2O3、氮化硅等或它们的复合层。替换栅电极36”的材料可以包括或由与参考图5B和图5C的参考栅电极层36所讨论的类似的含金属材料形成。
图14示出了模拟几种类型晶体管性能的模拟结果。Y轴表示最小的栅极长度，具有该最小的栅极长度的相应的晶体管仍可以具有良好的栅极控制能力，例如，亚阈值摆幅(SS)小于约70mV/dec。X轴表示在垂直于栅极长度方向的方向上的沟道的尺寸(以下称为沟道宽度尺寸)，该尺寸可以是沟道厚度tCH、纳米线的直径D和/或沟道的宽度。模拟的晶体管包括单栅极晶体管、FinFET、纳米线(NW)晶体管以及根据本发明的实施例的晶体管。图14示出了最小沟道长度与沟道宽度尺寸的函数关系。模拟结果表明，当沟道宽度尺寸增大时，晶体管的最小(所需)沟道长度也可能会增大。当相同的沟道宽度尺寸用于所有类型的晶体管时，根据本发明的实施例的晶体管具有最小的最小化沟道长度。这表明根据本发明的实施例形成的晶体管可以具有最小的沟道长度，同时仍然在模拟的晶体管间保持良好的沟道控制。或者说，当沟道宽度尺寸相同时，根据本发明实施例形成的晶体管具有比其他类型的晶体管更好的缩放能力。例如，当沟道宽度尺寸为6nm时。根据本发明的实施例的晶体管具有6nm的最小沟道长度，而纳米线晶体管和FinFET分别具有约9nm和约14nm的最小沟道长度，其远高于根据本发明的实施例的晶体管。单栅极晶体管具有比纳米线晶体管和FinFET甚至更差的缩放能力。
本发明的实施例具有一些有利特征。通过形成作为晶体管的沟道的2D(范德华)材料，可以使短沟道效应最小化，并且可以按比例缩小所得晶体管的最小沟道长度，而不会引起亚阈值摆幅的增大。通过采用具有最大化面积的边缘接触件，可以减小源极/漏极接触件的接触电阻。
根据本发明的一些实施例，方法包括：蚀刻介电层以形成介电鳍；在介电鳍上沉积过渡金属二硫属化物层；对过渡金属二硫属化物层实施第一各向异性蚀刻工艺，其中，去除过渡金属二硫属化物层的水平部分，并且保留位于介电鳍侧壁上的过渡金属二硫属化物层的垂直部分，以形成垂直半导体环；在垂直半导体环的第一部分上形成栅极堆叠件；以及形成源极/漏极接触插塞，其中，源极/漏极接触插塞接触垂直半导体环的第二部分的侧壁。根据实施例，沉积过渡金属二硫属化物层包括沉积MoS2层。根据实施例，该方法还包括：在形成栅极堆叠件之后，沉积覆盖过渡金属二硫属化物层的接触蚀刻停止层和层间电介质，并且形成源极/漏极接触插塞包括：实施第二各向异性蚀刻工艺以形成穿透层间电介质的接触开口，使接触蚀刻停止层暴露于接触开口；对接触蚀刻停止层实施各向同性蚀刻工艺，以将过渡金属二硫属化物层暴露于接触开口；以及用导电材料填充接触开口。根据实施例，该方法还包括：在栅极堆叠件的侧壁上形成栅极间隔件，并且源极/漏极接触插塞接触栅极间隔件的侧壁。根据实施例，该方法还包括：形成栅极间隔件，其中，栅极堆叠件和栅极间隔件的侧壁彼此接触，并且源极/漏极接触插塞与栅极间隔件间隔开。根据实施例，使用额外的介电层作为蚀刻停止层实施蚀刻介电层以形成介电鳍，并且源极/漏极接触插塞与垂直半导体环形成界面，并且其中，界面从垂直半导体环的顶端延伸至额外的介电层的顶面。根据实施例，使用MoO3粉末和硫粉末作为前体的化学汽相沉积实施过渡金属二硫属化物层。
根据本发明的一些实施例，器件包括：介电鳍；过渡金属二硫属化物层，位于介电鳍的侧壁上；栅极堆叠件，位于介电鳍和过渡金属二硫属化物层上，其中，栅极堆叠件接触过渡金属二硫属化物层的侧壁的第一部分；栅极间隔件，接触栅极堆叠件；以及源极/漏极接触插塞，接触过渡金属二硫属化物层的侧壁的第二部分。根据实施例，该器件还包括：介电层，介电鳍位于介电层上方并且接触介电层，其中，过渡金属二硫属化物层延伸至介电层的顶面。根据实施例，源极/漏极接触插塞与过渡金属二硫属化物层形成界面，并且界面延伸至介电层的顶面。根据实施例，介电鳍和介电层由不同的介电材料形成。根据实施例，过渡金属二硫属化物层是单层。根据实施例，过渡金属二硫属化物层包括多个单层。根据实施例，过渡金属二硫属化物层包括MoS2。
根据本发明的一些实施例，器件包括：介电层；介电鳍，位于介电层上方；二维半导体材料，形成环绕并且接触介电鳍侧壁的环；栅极电介质，接触介电鳍和介电层的顶面，并且还接触二维半导体材料；栅电极，位于栅极电介质上方，其中，二维半导体材料包括位于栅电极的相对侧上的源极部分和漏极部分；以及源极/漏极接触插塞，接触二维半导体材料的源极部分和漏极部分中的一个。在实施例中，源极部分和漏极部分中的每个接触介电鳍的三个侧壁以形成U形结构。根据实施例，二维半导体材料没有平行于介电层和介电鳍之间的界面的水平部分。根据实施例，二维半导体材料包括过渡金属二硫属化物层。根据实施例，源极/漏极接触插塞和二维半导体材料形成延伸至介电层的顶面的界面。根据实施例，介电层和介电鳍由不同的介电材料形成。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
蚀刻介电层以形成介电鳍；
在所述介电鳍上沉积过渡金属二硫属化物层；
对所述过渡金属二硫属化物层实施第一各向异性蚀刻工艺，其中，去除所述过渡金属二硫属化物层的水平部分，并且保留位于所述介电鳍侧壁上的所述过渡金属二硫属化物层的垂直部分以形成垂直半导体环；
在所述垂直半导体环的第一部分上形成栅极堆叠件；以及
形成源极/漏极接触插塞，其中，所述源极/漏极接触插塞接触所述垂直半导体环的第二部分的侧壁。
2.根据权利要求1所述的方法，其中，所述沉积过渡金属二硫属化物层包括沉积MoS2层。
3.根据权利要求1所述的方法，还包括：在形成所述栅极堆叠件之后，沉积覆盖所述过渡金属二硫属化物层的接触蚀刻停止层和层间电介质，并且形成所述源极/漏极接触插塞包括：
实施第二各向异性蚀刻工艺以形成穿透所述层间电介质的接触开口，使所述接触蚀刻停止层暴露于所述接触开口；
对所述接触蚀刻停止层实施各向同性蚀刻工艺，以将所述过渡金属二硫属化物层暴露于所述接触开口；以及
用导电材料填充所述接触开口。
4.根据权利要求1所述的方法，还包括：在所述栅极堆叠件的侧壁上形成栅极间隔件，并且所述源极/漏极接触插塞接触所述栅极间隔件的侧壁。
5.根据权利要求1所述的方法，还包括：形成栅极间隔件，其中，所述栅极堆叠件和所述栅极间隔件的侧壁彼此接触，并且所述源极/漏极接触插塞与所述栅极间隔件间隔开。
6.根据权利要求1所述的方法，其中，使用额外的介电层作为蚀刻停止层实施蚀刻所述介电层以形成所述介电鳍，并且所述源极/漏极接触插塞与所述垂直半导体环形成界面，并且其中，所述界面从所述垂直半导体环的顶端延伸至所述额外的介电层的顶面。
7.根据权利要求1所述的方法，其中，使用MoO3粉末和硫粉末作为前体的化学汽相沉积实施所述过渡金属二硫属化物层。
8.一种半导体器件，包括：
介电鳍；
过渡金属二硫属化物层，位于所述介电鳍的侧壁上；
栅极堆叠件，位于所述介电鳍和所述过渡金属二硫属化物层上，其中，所述栅极堆叠件接触所述过渡金属二硫属化物层的侧壁的第一部分；
栅极间隔件，接触所述栅极堆叠件；以及
源极/漏极接触插塞，接触所述过渡金属二硫属化物层的侧壁的第二部分。
9.根据权利要求8所述的半导体器件，还包括：介电层，所述介电鳍位于所述介电层上方并且接触所述介电层，其中，所述过渡金属二硫属化物层延伸至所述介电层的顶面。
10.一种半导体器件，包括：
介电层；
介电鳍，位于所述介电层上方；
二维半导体材料，形成环绕并且接触所述介电鳍的侧壁的环；
栅极电介质，接触所述介电鳍和所述介电层的顶面，并且还接触所述二维半导体材料；
栅电极，位于所述栅极电介质上方，其中，所述二维半导体材料包括位于所述栅电极的相对侧上的源极部分和漏极部分；以及
源极/漏极接触插塞，接触所述二维半导体材料的所述源极部分和所述漏极部分中的一个。
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