TWI505349B - 製造半導體裝置之方法 - Google Patents

製造半導體裝置之方法 Download PDF

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Publication number
TWI505349B
TWI505349B TW099147377A TW99147377A TWI505349B TW I505349 B TWI505349 B TW I505349B TW 099147377 A TW099147377 A TW 099147377A TW 99147377 A TW99147377 A TW 99147377A TW I505349 B TWI505349 B TW I505349B
Authority
TW
Taiwan
Prior art keywords
layer
gate electrode
etching
forming
germanium
Prior art date
Application number
TW099147377A
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English (en)
Chinese (zh)
Other versions
TW201135830A (en
Inventor
鄭會晟
申東石
金東赫
許晶植
金明宣
Original Assignee
三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三星電子股份有限公司 filed Critical 三星電子股份有限公司
Publication of TW201135830A publication Critical patent/TW201135830A/zh
Application granted granted Critical
Publication of TWI505349B publication Critical patent/TWI505349B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching
    • H10P72/0422—Apparatus for fluid treatment for etching for wet etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H10P50/644—Anisotropic liquid etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
TW099147377A 2010-02-12 2010-12-31 製造半導體裝置之方法 TWI505349B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100013123A KR101576529B1 (ko) 2010-02-12 2010-02-12 습식 식각을 이용한 실리콘 파셋트를 갖는 반도체 장치 및 제조방법

Publications (2)

Publication Number Publication Date
TW201135830A TW201135830A (en) 2011-10-16
TWI505349B true TWI505349B (zh) 2015-10-21

Family

ID=44369924

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099147377A TWI505349B (zh) 2010-02-12 2010-12-31 製造半導體裝置之方法

Country Status (5)

Country Link
US (1) US8207040B2 (https=)
JP (1) JP5659416B2 (https=)
KR (1) KR101576529B1 (https=)
CN (1) CN102157380B (https=)
TW (1) TWI505349B (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102487015A (zh) * 2010-12-03 2012-06-06 中国科学院微电子研究所 一种半导体结构及其制造方法
US8383485B2 (en) * 2011-07-13 2013-02-26 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial process for forming semiconductor devices
KR20140038826A (ko) 2012-09-21 2014-03-31 삼성전자주식회사 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법
CN104217956B (zh) * 2013-06-05 2017-05-17 中芯国际集成电路制造(上海)有限公司 Pmos晶体管及其制作方法
US9209175B2 (en) 2013-07-17 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices having epitaxy regions with reduced facets
US9202916B2 (en) * 2013-12-27 2015-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure
US9613974B2 (en) 2015-03-13 2017-04-04 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
CN106558499B (zh) * 2015-09-30 2019-09-27 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
CN106887408B (zh) 2015-12-15 2019-12-17 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US10319832B2 (en) 2017-04-28 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming same
KR102365109B1 (ko) 2017-08-22 2022-02-18 삼성전자주식회사 집적회로 장치

Citations (5)

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US20030148563A1 (en) * 2000-03-06 2003-08-07 Kabushiki Kaisha Toshiba Transistor, semiconductor device and manufacturing method of semiconductor device
TWI225715B (en) * 2001-09-11 2004-12-21 Asia Pacific Microsystems Inc Manufacturing method of film bulk acoustic device
US20060125040A1 (en) * 2004-12-15 2006-06-15 Tower Semiconductor Ltd. Cobalt silicide schottky diode on isolated well
US20060131656A1 (en) * 2004-12-17 2006-06-22 Samsung Electronics Co., Ltd. CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same
US20090166625A1 (en) * 2007-12-28 2009-07-02 United Microelectronics Corp. Mos device structure

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JP2964925B2 (ja) 1994-10-12 1999-10-18 日本電気株式会社 相補型ｍｉｓ型ｆｅｔの製造方法
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
JP4837902B2 (ja) * 2004-06-24 2011-12-14 富士通セミコンダクター株式会社 半導体装置
US7288448B2 (en) * 2004-08-24 2007-10-30 Orlowski Marius K Method and apparatus for mobility enhancement in a semiconductor device
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7195985B2 (en) 2005-01-04 2007-03-27 Intel Corporation CMOS transistor junction regions formed by a CVD etching and deposition sequence
US7629273B2 (en) * 2006-09-19 2009-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method for modulating stresses of a contact etch stop layer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030148563A1 (en) * 2000-03-06 2003-08-07 Kabushiki Kaisha Toshiba Transistor, semiconductor device and manufacturing method of semiconductor device
TWI225715B (en) * 2001-09-11 2004-12-21 Asia Pacific Microsystems Inc Manufacturing method of film bulk acoustic device
US20060125040A1 (en) * 2004-12-15 2006-06-15 Tower Semiconductor Ltd. Cobalt silicide schottky diode on isolated well
US20060131656A1 (en) * 2004-12-17 2006-06-22 Samsung Electronics Co., Ltd. CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same
US20090166625A1 (en) * 2007-12-28 2009-07-02 United Microelectronics Corp. Mos device structure

Also Published As

Publication number Publication date
KR101576529B1 (ko) 2015-12-11
CN102157380B (zh) 2015-02-04
CN102157380A (zh) 2011-08-17
TW201135830A (en) 2011-10-16
KR20110093217A (ko) 2011-08-18
US20110201166A1 (en) 2011-08-18
JP2011166119A (ja) 2011-08-25
JP5659416B2 (ja) 2015-01-28
US8207040B2 (en) 2012-06-26

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