CN106887408B - 一种半导体器件的制造方法 - Google Patents

一种半导体器件的制造方法 Download PDF

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CN106887408B
CN106887408B CN201510939766.0A CN201510939766A CN106887408B CN 106887408 B CN106887408 B CN 106887408B CN 201510939766 A CN201510939766 A CN 201510939766A CN 106887408 B CN106887408 B CN 106887408B
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刘佳磊
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Abstract

本发明提供一种半导体器件的制造方法，涉及半导体技术领域。包括：提供形成有若干栅极结构的半导体衬底；沉积间隙壁材料层覆盖栅极结构以及半导体衬底的表面；刻蚀暴露的部分间隙壁材料层以形成位于NMOS区域内的栅极结构侧壁上的第一间隙壁；沉积牺牲材料层覆盖剩余的间隙壁材料层的表面、第一间隙壁以及半导体衬底暴露的表面；刻蚀PMOS区域暴露的牺牲材料层和间隙壁材料层，以形成位于PMOS区域中的栅极结构侧壁上的第二间隙壁；在PMOS区域内的源/漏区域形成应力层，在应力层上形成覆盖层；去除剩余的牺牲材料层、第一间隙壁和第二间隙壁。本发明的方法可有效避免覆盖层损失过多以至于不能很好的保护SiGe层的问题。

Description

一种半导体器件的制造方法
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件的制造方法。
背景技术
嵌入式锗硅(Embedded SiGe，E-SiGe)工艺被广泛应用于先进的CMOS工艺技术以在沟道区增加额外的压应力，因此显著提升PMOS的性能。然而E-SiGe工艺面临诸多挑战，包括单元处理过程(高Ge百分比含量，缺陷控制等)和集成问题(应力接近、嵌入式SiGe形状、热兼容性等)
∑型SiGe源/漏通常被用于产生额外的压应力到沟道以提高空穴迁移率。如图1A所示，在SiGe层101的顶部形成Si覆盖层102以保护SiGe 101层免于受到损伤。在之后的工艺过程期间，Si覆盖层102损失过多以至于不能很好的保护SiGe层101，如图1C所示。如图1B所示，NMOS器件区间隙壁氮化硅(SiN)103刻蚀工艺期间干法刻蚀和灰化步骤是造成Si覆盖层102损失的主要原因，而在该步骤期间PMOS区域的Si源区和漏区暴露，干法刻蚀时产生的等离子体使得Si覆盖层102受到损伤和氧化。
因此，为解决上述技术问题，有必要提出一种新的半导体器件的制造方法。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
针对现有技术的不足，本发明提供一种半导体器件的制造方法，包括：
提供半导体衬底，所述半导体衬底包括PMOS区域和NMOS区域，并在所述PMOS区域和NMOS区域的所述半导体衬底上形成有若干栅极结构；
沉积间隙壁材料层覆盖所述栅极结构以及所述半导体衬底的表面；
形成第一光阻层覆盖所述PMOS区域暴露所述NMOS区域；
刻蚀暴露的部分所述间隙壁材料层，以形成位于所述NMOS区域内的所述栅极结构侧壁上的第一间隙壁；
去除所述第一光阻层；
沉积牺牲材料层覆盖剩余的所述间隙壁材料层的表面、所述第一间隙壁的表面以及所述半导体衬底暴露的表面；
形成第二光阻层覆盖所述NMOS区域暴露所述PMOS区域，依次刻蚀暴露的所述牺牲材料层和所述间隙壁材料层，以形成位于所述PMOS区域中的所述栅极结构侧壁上的第二间隙壁；
去除所述第二光阻层，在所述PMOS区域内的所述半导体衬底的源/漏区域形成应力层，在所述应力层上形成覆盖层；
去除剩余的所述牺牲材料层、所述第一间隙壁和所述第二间隙壁。
进一步地，所述栅极结构包括自下而上的栅极介电层和栅极层。
进一步地，所述间隙壁材料层包括氮化物层和氧化物层。
进一步地，所述氮化物层位于所述氧化物层的上方。
进一步地，所述氮化物层为氮化硅，所述氧化物层为氧化硅。
进一步地，所述氮化物层和所述氧化物层的沉积方法选自高温炉管、化学气相沉积、物理气相沉积或原子层沉积中的一种。
进一步地，所述氮化物层的沉积温度范围为100℃至600℃。
进一步地，所述氧化物层的厚度范围为10至50埃，所述氮化物层的厚度范围为50至200埃。
进一步地，所述牺牲材料层与所述间隙壁材料层的外层材料具有相同的材质。
进一步地，在刻蚀暴露的部分所述间隙壁材料层的步骤中，采用干法刻蚀法刻蚀部分所述氮化物层停止于所述氧化物层，再采用湿法刻蚀法刻蚀部分所述氧化物层。
进一步地，所述湿法刻蚀采用稀释的氢氟酸作为腐蚀液，所述氢氟酸的摩尔浓度范围为0.01％至1％。
进一步地，采用湿法刻蚀的方法去除剩余的所述牺牲材料层、所述第一间隙壁和所述第二间隙壁。
进一步地，采用磷酸作为腐蚀液去除剩余的所述牺牲材料层、所述第一间隙壁和所述第二间隙壁，其中，反应温度范围为100℃至200℃。
进一步地，在沉积所述间隙壁材料层之前，在所述栅极结构的侧壁上还形成有偏移侧墙以及在所述栅极结构的顶面上形成有栅极硬掩蔽层。
进一步地，所述应力层的材料包括锗硅。
进一步地，所述覆盖层为硅层。
进一步地，所述牺牲材料层的沉积温度范围为100℃至600℃，所述牺牲材料层的厚度范围为50至200埃。
根据本发明的制造方法，可有效避免产生现有技术中干法刻蚀工艺时造成的覆盖层损失过多以至于不能很好的保护SiGe层的问题，进而使得SiGe层可以很好的给沟道施加压应力来提高载流子迁移率，最终提高了器件的良率和性能。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A-图1C示出了现有的一种半导体器件的制造方法的相关步骤所获得器件的剖视图；
图2A-2H示出了本发明一具体实施方式的半导体器件的制造方法依次实施所获得器件的剖视图；
图3为本发明一具体实施方式的半导体器件的制造方法的流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细的步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
下面，参考图2A-2H以及图3对本发明一具体实施例的半导体器件的制造方法做详细描述。其中，图2A-2H示出了本发明一具体实施方式的半导体器件的制造方法依次实施所获得器件的剖视图；图3为本发明一具体实施方式的半导体器件的制造方法的流程图。
作为示例，本实施例中的半导体器件的制造方法，具体包括如下步骤：
首先，执行步骤S301，提供半导体衬底，所述半导体衬底包括PMOS区域和NMOS区域，并在所述PMOS区域和NMOS区域的所述半导体衬底上形成有若干栅极结构。
具体地，如图2A所示，半导体衬底200的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底200的构成材料选用单晶硅。在半导体衬底200中形成有隔离结构201，隔离结构201为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构，作为示例，在所述半导体衬底中形成有浅沟槽隔离(STI)，所述浅沟槽隔离将半导体衬底分为NMOS区域和PMOS区域。半导体衬底200中还形成有各种阱(well)结构，为了简化，图示中予以省略。
所述半导体衬底200包括PMOS区域和NMOS区域，其对应可制作PMOS器件和NMOS器件。
在所述PMOS区域和NMOS区域的所述半导体衬底200上形成有若干栅极结构。作为示例，栅极结构包括自下而上依次层叠的栅极介电层2021和栅极层2022。示例性地，所述栅极介电层2021可以是氧化硅(SiO2)或氮氧化硅(SiON)。在一实施例中，栅极层2022由多晶硅材料组成，一般也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极层的材料。栅极介电层2021以及栅极层的形成方法包括化学气相沉积法(CVD)，如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(LTCVD)、等离子体化学气相沉积(PECVD)，也可使用例如溅镀及物理气相沉积(PVD)等一般相似方法。
作为示例，在栅极结构的侧壁上还形成有偏移侧墙2024(offset spacer)。所述偏移侧墙2024的材料例如是氮化硅、氧化硅或者氮氧化硅等绝缘材料。进一步地，在栅极结构的顶面上还可形成有栅极硬掩蔽层2023，栅极硬掩蔽层2023的材料可以是氮化硅、氧化硅或者氮氧化硅等，其还可以具有与偏移侧墙2024相同的材料。
接下来，执行步骤S302，沉积间隙壁材料层覆盖所述栅极结构以及所述半导体衬底的表面。
如图2A所示，本实施例中，间隙壁材料层覆盖栅极结构上的栅极硬掩蔽层2023以及偏移侧墙2024和暴露的半导体衬底200的表面。
间隙壁材料层可以为氧化硅、氮化硅、氮氧化硅中一种或者它们组合构成。作为本实施例的一个较佳地实施方式，所述间隙壁材料层为氧化硅2031、氮化硅2032共同组成，其中，氮化硅2032位于氧化硅2031的上方。可采用本领域技术人员熟知的任何方法沉积形成氧化硅2031和氮化硅2032，例如高温炉管(furnace)、化学气相沉积(CVD)、物理气相沉积(PVD)或原子层沉积(ALD)，其中，对于形成氧化硅2031，高温炉管为高温炉管氧化，而对于形成氮化硅2032，高温炉管为高温炉管氮化。
本实施例中，氧化硅2031的沉积温度范围可以为100℃至600℃，氧化硅2031的厚度范围为10至50埃。
作为示例，氮化硅2032的沉积温度范围可以为100℃至600℃，氮化硅2032的厚度范围为50至200埃。
接下来，执行步骤S303，形成第一光阻层覆盖所述PMOS区域暴露所述NMOS区域。
如图2B所示，形成第一光阻层2041覆盖所述PMOS区域暴露所述NMOS区域。形成第一光阻层2041的方法，可以包括涂胶、曝光、显影等步骤。
接下来，执行步骤S304，刻蚀暴露的部分所述间隙壁材料层，以形成位于所述NMOS区域内的所述栅极结构侧壁上的第一间隙壁。
如图2C所示，作为示例，当所述间隙壁材料层包括依次层叠的氧化硅2031和氮化硅2032时，可先采用干法刻蚀法刻蚀部分所述氮化硅2032停止于氧化硅2031，再采用湿法刻蚀法刻蚀部分氧化硅2031。其中，干法刻蚀为各向异性刻蚀。干法刻蚀工艺，例如反应离子刻蚀、离子束刻蚀、等离子刻蚀、激光烧蚀或者这些方法的任意组合。可以使用单一的刻蚀方法，或者也可以使用多于一个的刻蚀方法。
在一个示例中，采用稀释的氢氟酸作为腐蚀液，湿法刻蚀氧化硅2031，所述氢氟酸的摩尔浓度范围为0.01％至1％。
在本实施例中，经过本步骤的刻蚀形成位于所述NMOS区域内的所述栅极结构侧壁上的第一间隙壁203a，而同时将位于NMOS区域的半导体衬底200表面上的间隙壁材料层去除，暴露出半导体衬底200的部分表面。示例性地，当半导体衬底的表面上形成有栅极介电层2021时，还包括刻蚀部分栅极介电层2021暴露出半导体衬底200的部分表面的步骤。
接下来，执行步骤S305，去除所述第一光阻层。
如图2D所示，去除第一光阻层2041。可采用本领域技术人员技术人员熟知的任何方法去除该第一光阻层，例如，灰化的方法等。
接下来，执行步骤S306，沉积牺牲材料层覆盖剩余的所述间隙壁材料层的表面、所述第一间隙壁的表面以及所述半导体衬底暴露的表面。
如图2E所示，沉积牺牲材料层205覆盖剩余的所述间隙壁材料层的表面、所述第一间隙壁203a的表面以及所述半导体衬底200暴露的表面。沉积牺牲材料层205的材料例如是氮化硅、氧化硅或者氮氧化硅等绝缘材料。较佳地，该牺牲材料层205与所述间隙壁材料层的外层材料具有相同的材质，例如，间隙壁材料层包括依次层叠的氧化硅2031和氮化硅2032时，则牺牲材料层205的材料可以为氮化硅。可采用本领域技术人员熟知的任何方法沉积形成牺牲材料层205，例如高温炉管(furnace)、化学气相沉积(CVD)、物理气相沉积(PVD)或原子层沉积(ALD)，牺牲材料层205的沉积温度范围可以为100℃至600℃，牺牲材料层205的厚度范围为50至200埃。
接下来，执行步骤S307，形成第二光阻层覆盖所述NMOS区域暴露所述PMOS区域，依次刻蚀暴露的所述牺牲材料层和所述间隙壁材料层，以形成位于所述PMOS区域中的所述栅极结构侧壁上的第二间隙壁。
如图2F所示，形成第二光阻层2042覆盖所述NMOS区域暴露所述PMOS区域，依次刻蚀暴露的所述牺牲材料层205和所述间隙壁材料层，以形成位于所述PMOS区域中的所述栅极结构侧壁上的第二间隙壁203b。
作为示例，形成第二光阻层2042的方法，可以包括涂胶、曝光、显影等步骤。
作为示例，当所述间隙壁材料层包括依次层叠的氧化硅2031和氮化硅2032时，可先采用干法刻蚀法刻蚀部分所述氮化硅2032停止于氧化硅2031，再采用湿法刻蚀法刻蚀部分氧化硅2031。其中，干法刻蚀为各向异性刻蚀。干法刻蚀工艺，例如反应离子刻蚀、离子束刻蚀、等离子刻蚀、激光烧蚀或者这些方法的任意组合。可以使用单一的刻蚀方法，或者也可以使用多于一个的刻蚀方法。
在一个示例中，采用稀释的氢氟酸作为腐蚀液，湿法刻蚀氧化硅2031，所述氢氟酸的摩尔浓度范围为0.01％至1％。
在本实施例中，经过本步骤的刻蚀形成位于所述PMOS区域内的所述栅极结构侧壁上的第一间隙壁203b，而同时将位于PMOS区域的半导体衬底200表面上的间隙壁材料层去除，暴露出半导体衬底200的部分表面。示例性地，当半导体衬底的表面上形成有栅极介电层2021时，还包括刻蚀部分栅极介电层2021暴露出半导体衬底200的部分表面的步骤。
接着，执行步骤S308，去除所述第二光阻层，在所述PMOS区域内的所述半导体衬底的源/漏区域形成应力层，在所述锗硅应力层上形成覆盖层。
作为示例，如图2G所示，去除所述第二光阻层2042，在所述PMOS区域内的所述半导体衬底200的源/漏区域形成应力层206，在所述应力层206上形成覆盖层207。
示例性地，可采用例如灰化法或者剥离法等方法去除第二光阻层2042。所述应力层206可以选用任何具有压应力的材料，其中，较佳地，所述应力层206的材料包括锗硅。锗硅(SiGe)可以通过给沟道施加压应力来提高载流子迁移率。
在一个示例中，形成锗硅应力层206的工艺包括：在PMOS区域的半导体衬底中的源/漏区域形成凹槽，该凹槽的形成较佳地为Σ型，之后采用选择性外延生长工艺在凹槽中形成嵌入式锗硅应力层206。所述选择性外延生长工艺可以采用低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)、超高真空化学气相沉积(UHVCVD)、快速热化学气相沉积(RTCVD)和分子束外延(MBE)中的一种。在本实施例中，所述选择性外延生长工艺可以在低温下实施，所述低温的范围为500-850℃。
形成锗硅应力层206之后，在锗硅应力层206上形成覆盖层207，所述覆盖层207为一硅层或者一具有低锗含量的锗硅层。
接着，执行步骤S309，去除剩余的所述牺牲材料层、所述第一间隙壁和所述第二间隙壁。
如图2H所示，去除剩余的牺牲材料层205、第一间隙壁203a和第二间隙壁203b。
作为示例，采用湿法刻蚀的方法去除剩余的所述牺牲材料层205、所述第一间隙壁203a和所述第二间隙壁203b。在牺牲材料层205、所述第一间隙壁203a和所述第二间隙壁203b的材料包括氮化硅时，可采用磷酸作为腐蚀液去除，其中，反应温度范围为100℃至200℃。
在一个示例中，本步骤中，还包括去除栅极硬掩蔽层2023的步骤。
至此完成了本发明实施例中的关键步骤的介绍，其中，对于形成完整的器件，还包括其他中间步骤例如进行离子注入形成源极和漏极或者之后的工艺步骤等，在此均不再赘述。
综上所述，根据本发明的制造方法，可有效避免现有技术中干法刻蚀工艺时造成的覆盖层损失过多以至于不能很好的保护SiGe层的问题的产生，进而使得SiGe层可以很好的给沟道施加压应力来提高载流子迁移率，最终提高了器件的良率和性能。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (16)

1.一种半导体器件的制造方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底包括PMOS区域和NMOS区域，并在所述PMOS区域和NMOS区域的所述半导体衬底上形成有若干栅极结构；
沉积间隙壁材料层覆盖所述栅极结构以及所述半导体衬底的表面；
形成第一光阻层覆盖所述PMOS区域暴露所述NMOS区域；
刻蚀暴露的部分所述间隙壁材料层，以形成位于所述NMOS区域内的所述栅极结构侧壁上的第一间隙壁；
去除所述第一光阻层；
沉积牺牲材料层覆盖剩余的所述间隙壁材料层的表面、所述第一间隙壁的表面以及所述半导体衬底暴露的表面；
形成第二光阻层覆盖所述NMOS区域暴露所述PMOS区域，依次刻蚀暴露的所述牺牲材料层和所述间隙壁材料层，以形成位于所述PMOS区域中的所述栅极结构侧壁上的第二间隙壁；
去除所述第二光阻层，在所述PMOS区域内的所述半导体衬底的源/漏区域形成应力层，在所述应力层上形成覆盖层；
采用湿法刻蚀的方法去除剩余的所述牺牲材料层、所述第一间隙壁和所述第二间隙壁。
2.根据权利要求1所述的制造方法，其特征在于，所述栅极结构包括自下而上的栅极介电层和栅极层。
3.根据权利要求1所述的制造方法，其特征在于，所述间隙壁材料层包括氮化物层和氧化物层。
4.根据权利要求3所述的制造方法，其特征在于，所述氮化物层位于所述氧化物层的上方。
5.根据权利要求3所述的制造方法，其特征在于，所述氮化物层为氮化硅，所述氧化物层为氧化硅。
6.根据权利要求3所述的制造方法，其特征在于，所述氮化物层和所述氧化物层的沉积方法选自高温炉管、化学气相沉积、物理气相沉积或原子层沉积中的一种。
7.根据权利要求3所述的制造方法，其特征在于，所述氮化物层的沉积温度范围为100℃至600℃。
8.根据权利要求4所述的制造方法，其特征在于，所述氧化物层的厚度范围为10至50埃，所述氮化物层的厚度范围为50至200埃。
9.根据权利要求1所述的制造方法，其特征在于，所述牺牲材料层与所述间隙壁材料层的外层材料具有相同的材质。
10.根据权利要求4所述的制造方法，其特征在于，在刻蚀暴露的部分所述间隙壁材料层的步骤中，采用干法刻蚀法刻蚀部分所述氮化物层停止于所述氧化物层，再采用湿法刻蚀法刻蚀部分所述氧化物层。
11.根据权利要求10所述的制造方法，其特征在于，所述湿法刻蚀法采用稀释的氢氟酸作为腐蚀液，所述氢氟酸的摩尔浓度范围为0.01％至1％。
12.根据权利要求1所述的制造方法，其特征在于，采用磷酸作为腐蚀液去除剩余的所述牺牲材料层、所述第一间隙壁和所述第二间隙壁，其中，反应温度范围为100℃至200℃。
13.根据权利要求1所述的制造方法，其特征在于，在沉积所述间隙壁材料层之前，在所述栅极结构的侧壁上还形成有偏移侧墙以及在所述栅极结构的顶面上形成有栅极硬掩蔽层。
14.根据权利要求1所述的制造方法，其特征在于，所述应力层的材料包括锗硅。
15.根据权利要求1所述的制造方法，其特征在于，所述覆盖层为硅层。
16.根据权利要求1所述的制造方法，其特征在于，所述牺牲材料层的沉积温度范围为100℃至600℃，所述牺牲材料层的厚度范围为50至200埃。
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