CN108109900B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN108109900B
CN108109900B CN201611048954.5A CN201611048954A CN108109900B CN 108109900 B CN108109900 B CN 108109900B CN 201611048954 A CN201611048954 A CN 201611048954A CN 108109900 B CN108109900 B CN 108109900B
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oxide layer
layer
nitride barrier
semiconductor substrate
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CN108109900A (zh
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禹国宾
徐小平
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201611048954.5A priority Critical patent/CN108109900B/zh
Priority to EP17202874.8A priority patent/EP3327752B1/en
Priority to US15/821,349 priority patent/US10490674B2/en
Publication of CN108109900A publication Critical patent/CN108109900A/zh
Priority to US16/502,610 priority patent/US11069821B2/en
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Abstract

本发明公开了一种半导体装置及其制造方法，涉及半导体技术领域。其中，所述方法包括：提供半导体衬底，所述半导体衬底包括彼此间隔开的第一区域和第二区域，所述第一区域和所述第二区域的表面具有第一氧化物层；执行氮化处理，以在所述第一区域和所述第二区域的表面的第一氧化物层的顶部区域形成氮化物阻挡层；去除所述第二区域上经氮化处理后的第一氧化物层；执行氧化处理，以在所述第二区域的表面形成第二氧化物层。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体装置及其制造方法。
背景技术
NOR闪存存储器(NOR flash memory)被广泛用在嵌入式系统中来存储和读取程序。与NAND闪存存储器相比，NOR闪存存储器在读取数据的性能方面更优，并且支持芯片内执行(eXecute-In-Place，XIP)来直接运行程序。
然而，发明人发现：随着NOR闪存存储器的闪存单元密度的增加，有些区域的闪存器件的隧穿氧化层要比期望的厚度更大，这使得这些区域的闪存器件的阈值电压会增大。
发明内容
本发明的一个的目的在于提出一种半导体装置的制造方法，能够阻止特定区域的氧化层的厚度不期望地增大。
根据本发明的一个实施例，提供了一种半导体装置的制造方法，包括：提供半导体衬底，所述半导体衬底包括彼此间隔开的第一区域和第二区域，所述第一区域和所述第二区域的表面具有第一氧化物层；执行氮化处理，以在所述第一区域和所述第二区域的表面的第一氧化物层的顶部区域形成氮化物阻挡层；去除所述第二区域上经氮化处理后的第一氧化物层；执行氧化处理，以在所述第二区域的表面形成第二氧化物层。
在一个实施例中，所述半导体衬底还包括与所述第一区域和所述第二区域间隔开的第三区域，所述第三区域的表面上具有第三氧化物层；所述氮化处理还在所述第三氧化物层的顶部区域形成氮化物阻挡层；其中，所述第三氧化物层的厚度大于所述第二氧化物层的厚度。
在一个实施例中，所述提供半导体衬底包括：提供具有彼此间隔开的第一区域、第二区域和第三区域的半导体衬底；通过氧化工艺在所述第一区域、所述第二区域和所述第三区域的表面上形成第三氧化物层；去除所述第一区域和所述第二区域的表面上的第三氧化物层；通过氧化工艺在所述第一区域和所述第二区域的表面上形成第一氧化物层。
在一个实施例中，所述执行氮化处理包括：进行去耦等离子体氮化DPN工艺；进行氮化后退火PNA工艺。
在一个实施例中，所述去除所述第二区域上经氮化处理后的第一氧化物层包括：在执行氮化处理后的半导体衬底上形成掩模层；对所述掩模层进行图案化，以暴露所述第二区域上经氮化处理后的第一氧化物层；去除所述第二区域上经氮化处理后的第一氧化物层。
在一个实施例中，所述掩模层包括用于防止光刻胶中毒的保护层和在所述保护层上的光刻胶；所述方法还包括：去除剩余的掩模层；或者去除剩余的光刻胶，保留剩余的保护层。
在一个实施例中，所述保护层包括氧化硅、非晶碳或多晶硅。
在一个实施例中，所述氮化处理中氮的剂量为5×1015atoms/cm2至2×1016atoms/cm2。
在一个实施例中，所述氮化物阻挡层包括SiON。
在一个实施例中，所述氮化物阻挡层的厚度为3埃至50埃。
在一个实施例中，所述第一氧化物层为用于闪存器件的隧穿氧化物层。
在一个实施例中，所述方法还包括：在所述第一区域上的氮化物阻挡层上形成浮栅和控制栅。
根据本发明的另一个实施例，提供了一种半导体装置，包括：半导体衬底，所述半导体衬底包括彼此间隔开的第一区域和第二区域；在所述第一区域的表面上的第一氧化物层，所述第一氧化物层的顶部区域具有氮化物阻挡层；以及在所述第二区域的表面上的第二氧化物层。
在一个实施例中，所述半导体衬底还包括与所述第一区域和所述第二区域间隔开的第三区域；所述装置还包括：在所述第三区域的表面上的第三氧化物层，所述第三氧化物层的顶部区域具有氮化物阻挡层；其中，所述第三氧化物层的厚度大于所述第二氧化物层的厚度。
在一个实施例中，所述装置还包括：在所述氮化物阻挡层上用于防止光刻胶中毒的保护层。
在一个实施例中，所述保护层包括氧化硅、非晶碳或多晶硅。
在一个实施例中，所述氮化物阻挡层包括SiON。
在一个实施例中，所述氮化物阻挡层的厚度为3埃至50埃。
在一个实施例中，所述第一氧化物层为用于闪存器件的隧穿氧化物层。
在一个实施例中，所述装置还包括：在所述氮化物阻挡层上的浮栅和控制栅。
本发明提供的半导体装置的制造方法中，由于第一区域的第一氧化物层的表面形成有氮化物阻挡层，因此后续在第二区域形成第二氧化物层的氧化处理工艺中氮化物阻挡层可以阻止氧进入第一区域的第一氧化物层，从而使得第一区域的第一氧化物层的厚度不会继续增大，避免由于第一区域的第一氧化物层的厚度超过期望的厚度而影响器件(例如闪存器件)的阈值电压。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本发明的示例性实施例，并且连同说明书一起用于解释本发明的原理，在附图中：
图1是根据本发明一个实施例的半导体装置的制造方法的流程图；
图2-图5示出了根据本发明一个实施例的半导体装置的制造方法的各个阶段的截面图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本发明范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
发明人针对上述问题进行了深入研究，结果发现：不同的器件，例如高压器件(High Voltage)、低压器件(Low Voltage)、闪存器件等可能需要同时制造，在形成用于闪存器件的隧穿氧化层后，可能还需要形成用于其他器件的氧化层，而在形成用于其他器件的氧化层时可能会使得隧穿氧化层的厚度进一步增大，从而使得最终形成的闪存器件的阈值电压增大。据此，发明人提出了如下解决方案。
图1是根据本发明一个实施例的半导体装置的制造方法的流程图。图2-图5示出了根据本发明一个实施例的半导体装置的制造方法的各个阶段的截面图。下面结合图1、图2-图5对根据本发明一个实施例的半导体装置的制造方法进行说明。
首先，在步骤102，提供半导体衬底201。如图2所示，半导体衬底201包括彼此间隔开的第一区域211和第二区域221，第一区域211和第二区域221之间可以通过隔离结构202(例如浅沟槽隔离结构)隔离开。第一区域211和第二区域221的表面具有第一氧化物层203。
在一个实施例中，半导体衬底201还可以包括与第一区域211和第二区域221间隔开的第三区域231，第三区域231的表面上具有第三氧化物层204。这里，第一区域211可以是用于形成闪存器件的区域，第二区域221和第三区域231可以分别是用于形成低压器件和高压器件的区域。应理解，这里的低压器件和高压器件是相对的概念，低压器件的阈值电压低于高压器件的阈值电压。在一个实施例中，第一氧化物层203可以是用于闪存器件(例如NOR闪存存储器)的隧穿氧化物层，第三氧化物层204可以是用于高压器件的氧化物层。
在一个实施例中，可以通过如下方式来形成如图2所示的结构：首先，提供具有彼此间隔开的第一区域211、第二区域221和第三区域231的半导体衬底201。然后，通过氧化工艺在第一区域211、第二区域221和第三区域231的表面上形成第三氧化物层204。然后，去除第一区域211和第二区域221的表面上的第三氧化物层204，保留第三区域231的表面上的第三氧化物层204。之后，通过氧化工艺在第一区域211和第二区域221的表面上形成第一氧化物层203，从而形成了图2所示的结构。
接下来，在步骤104，执行氮化处理，以在第一区域221和第二区域231的表面的第一氧化物层203的顶部区域形成氮化物阻挡层301，例如氮氧化硅(SiON)等，如图3所示。在半导体衬底201包括第三区域231的情况下，氮化处理还在第三区域231上的第三氧化物层的顶部区域形成氮化物阻挡层301。
在一个实现方式中，执行氮化处理可以包括如下两个步骤：一是进行去耦等离子体氮化(DPN)工艺，二是进行氮化后退火(PNA)工艺。在一个实施例中，氮化处理中氮的剂量优选可以为5×1015atoms/cm2至2×1016atoms/cm2，例如7×1015atoms/cm2、9×1015atoms/cm2、1×1016atoms/cm2等。通过DPN和PNA工艺可以在第一氧化物层203的顶部区域(也即表面区域)形成很薄的一层氮化物阻挡层301。优选地，氮化物阻挡层301的厚度可以为3埃至50埃，例如10埃、30埃、40埃等。
然后，在步骤106，去除第二区域221上经氮化处理后的第一氧化物层，如图4所示。这里，去除的经氮化处理后的第一氧化物层包括第一氧化物层203及其表面上的氮化物阻挡层301。
在一个实现方式中，可以通过如下方式来去除第二区域221上经氮化处理后的第一氧化物层：
首先，在执行氮化处理后的半导体衬底201上形成掩模层。在一个实施例中，掩模层可以包括光刻胶。在另一个实施例中，掩模层可以包括用于防止光刻胶中毒的保护层和在保护层上的光刻胶，保护层的存在可以防止富氮的氮化物阻挡层使得光刻胶中毒。优选地，保护层可以包括氧化硅、非晶碳或多晶硅。例如，可以通过原子层沉积(ALD)、化学气相沉积(CVD)或炉管氧化等方式来形成保护层。然后，对掩模层进行图案化，以暴露第二区域上经氮化处理后的第一氧化物层。之后，去除第二区域上经氮化处理后的第一氧化物层。之后，可以去除剩余的掩模层。或者，也可以仅去除剩余的光刻胶，而保留剩余的保护层。
接下来，在步骤108，执行氧化处理，以在第二区域221的表面形成第二氧化物层501。这里，第二氧化物层501可以是用于形成低压器件的氧化层。第三氧化物层204的厚度大于第二氧化物层501的厚度。
如上描述了根据本发明一个实施例的半导体装置的制造方法。由于第一区域的第一氧化物层的表面形成有氮化物阻挡层，因此后续在第二区域形成第二氧化物层的氧化处理工艺中氮化物阻挡层可以阻止氧进入第一区域的第一氧化物层，从而使得第一区域的第一氧化物层的厚度不会继续增大，避免由于第一区域的第一氧化物层的厚度超过期望的厚度而影响器件(例如闪存器件)的阈值电压。
需要说明的是，本发明提供的方法中的第一氧化物层可以包括但不限于隧穿氧化物层。因此，本发明提供的方法并不限于闪存器件，也适于具有类似问题的其他类型的器件。
之后可以进行标准的闪存器件的制造工艺，例如，可以在第一区域上的氮化物阻挡层上形成浮栅和控制栅。还可以在第二区域的第二氧化物层上形成低压器件，在第三区域的第三氧化物层上形成高压器件，这里的低压器件和高压器件例如可以是逻辑器件等。由于这部分内容并非本发明关注的重点，在此不再赘述。
本发明还提供了一种半导体装置，如图5所示，半导体装置可以包括半导体衬底201，半导体衬底201包括彼此间隔开的第一区域211和第二区域221。第一区域211和第二区域221例如可以通过诸如浅沟槽隔离结构的隔离结构202间隔开。
半导体装置还可以包括在第一区域211的表面上的第一氧化物层203，第一氧化物层203的顶部区域具有氮化物阻挡层301，例如SiON。优选地，氮化物阻挡层301的厚度可以为3埃至50埃，例如10埃、30埃、40埃等。在一个实施例中，第一氧化物层203可以为用于闪存器件的隧穿氧化物层。
半导体装置还可以包括在第二区域221的表面上的第二氧化物层501。
在一个实施例中，参见图5，半导体衬底还可以包括与第一区域211和第二区域221间隔开的第三区域231。该实施例中，半导体装置还可以包括在第三区域231的表面上的第三氧化物层204。第三氧化物层204的顶部区域具有氮化物阻挡层301，例如SiON。这里，第三氧化物层204的厚度大于第二氧化物层501的厚度。
在一个实施例中，半导体装置还可以包括在氮化物阻挡层301上用于防止光刻胶中毒的保护层(未示出)，例如氧化硅、非晶碳或多晶硅。
在其他的实施例中，半导体装置还可以包括在第一区域211上的氮化物阻挡层301上的浮栅和控制栅(未示出)。
至此，已经详细描述了根据本发明实施例的半导体装置及其制造方法。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本发明的精神和范围。

Claims (16)

1.一种半导体装置的制造方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底包括彼此间隔开的第一区域和第二区域，所述第一区域和所述第二区域的表面具有第一氧化物层；
执行氮化处理，以在所述第一区域和所述第二区域的表面的第一氧化物层的顶部区域形成氮化物阻挡层；
去除所述第二区域上经氮化处理后的第一氧化物层；
执行氧化处理，以在所述第二区域的表面形成第二氧化物层；
其中，所述第一氧化物层为用于闪存器件的隧穿氧化物层，所述氮化物阻挡层包括SiON。
2.根据权利要求1所述的方法，其特征在于，所述半导体衬底还包括与所述第一区域和所述第二区域间隔开的第三区域，所述第三区域的表面上具有第三氧化物层；
所述氮化处理还在所述第三氧化物层的顶部区域形成氮化物阻挡层；
其中，所述第三氧化物层的厚度大于所述第二氧化物层的厚度。
3.根据权利要求2所述的方法，其特征在于，所述提供半导体衬底包括：
提供具有彼此间隔开的第一区域、第二区域和第三区域的半导体衬底；
通过氧化工艺在所述第一区域、所述第二区域和所述第三区域的表面上形成第三氧化物层；
去除所述第一区域和所述第二区域的表面上的第三氧化物层；
通过氧化工艺在所述第一区域和所述第二区域的表面上形成第一氧化物层。
4.根据权利要求1或2所述的方法，其特征在于，所述执行氮化处理包括：
进行去耦等离子体氮化工艺；
进行氮化后退火工艺。
5.根据权利要求1所述的方法，其特征在于，所述去除所述第二区域上经氮化处理后的第一氧化物层包括：
在执行氮化处理后的半导体衬底上形成掩模层；
对所述掩模层进行图案化，以暴露所述第二区域上经氮化处理后的第一氧化物层；
去除所述第二区域上经氮化处理后的第一氧化物层。
6.根据权利要求5所述的方法，其特征在于，所述掩模层包括用于防止光刻胶中毒的保护层和在所述保护层上的光刻胶；
所述方法还包括：
去除剩余的掩模层；或者
去除剩余的光刻胶，保留剩余的保护层。
7.根据权利要求6所述的方法，其特征在于，所述保护层包括氧化硅、非晶碳或多晶硅。
8.根据权利要求1所述的方法，其特征在于，所述氮化处理中氮的剂量为5×1015atoms/cm2至2×1016atoms/cm2。
9.根据权利要求1所述的方法，其特征在于，所述氮化物阻挡层的厚度为3埃至50埃。
10.根据权利要求1所述的方法，其特征在于，还包括：
在所述第一区域上的氮化物阻挡层上形成浮栅和控制栅。
11.一种半导体装置，其特征在于，包括：
半导体衬底，所述半导体衬底包括彼此间隔开的第一区域和第二区域；
在所述第一区域的表面上的第一氧化物层，所述第一氧化物层的顶部区域具有氮化物阻挡层；以及
在所述第二区域的表面上的第二氧化物层；
其中，所述第一氧化物层为用于闪存器件的隧穿氧化物层，所述氮化物阻挡层包括SiON。
12.根据权利要求11所述的装置，其特征在于，所述半导体衬底还包括与所述第一区域和所述第二区域间隔开的第三区域；
所述装置还包括：
在所述第三区域的表面上的第三氧化物层，所述第三氧化物层的顶部区域具有氮化物阻挡层；
其中，所述第三氧化物层的厚度大于所述第二氧化物层的厚度。
13.根据权利要求11或12所述的装置，其特征在于，还包括：
在所述氮化物阻挡层上用于防止光刻胶中毒的保护层。
14.根据权利要求13所述的装置，其特征在于，所述保护层包括氧化硅、非晶碳或多晶硅。
15.根据权利要求11或12所述的装置，其特征在于，所述氮化物阻挡层的厚度为3埃至50埃。
16.根据权利要求11所述的装置，其特征在于，还包括：
在所述氮化物阻挡层上的浮栅和控制栅。
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