JP4656854B2 - 半導体装置の製造方法 - Google Patents
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Description
本発明の一観点によれば、半導体基板の第1の半導体領域及び第2の半導体領域を覆う第1のマスクを形成し、前記半導体基板の第3の半導体領域に第1の不純物を注入する工程と、前記第2の半導体領域を覆う第2のマスクを形成し、前記第1の半導体領域及び前記第3の半導体領域に第2の不純物を注入する工程と、前記半導体基板に熱酸化法である第1の熱処理を行なうことにより、前記第1の半導体領域上に第1の膜厚を有するキャパシタ絶縁膜を形成し、前記第3の半導体領域上に前記第1の膜厚よりも厚い第2の膜厚を有する第1の酸化膜を形成し、第2の半導体領域上に前記第1の膜厚よりも薄い第3の膜厚を有する第2の酸化膜を形成する工程と、少なくとも前記第1の半導体領域を覆う第3のマスクを形成し、前記第2の酸化膜を除去するとともに、前記第1の酸化膜の一部も同時にエッチングして、膜厚が減少した前記第1の酸化膜を残存させる工程と、前記第2の酸化膜を除去した後、前記半導体基板に水素雰囲気中での第2の熱処理を行なう工程と、前記第2の熱処理の後、前記半導体基板に第3の熱処理を行い、前記第2の半導体領域にゲート絶縁膜を形成する工程と、前記キャパシタ絶縁膜上にキャパシタ電極を形成し、前記ゲート絶縁膜上にゲート電極を形成する工程とを有する半導体装置の製造方法が提供される。
[第1実施形態]
以下、本発明の第1実施形態による半導体装置の製造方法を図5と図6を用いて説明する。図5と図6は、本実施形態による半導体装置の製造方法を示す工程断面図である。
(評価結果)
図9は、nチャネルMISトランジスタにおけるVthのウェーハ面内の累積確率を示す図である。図中、縦軸は累積確率を示し、横軸はVthを示している。また、●は周辺砒素注入(図5(B)の注入)がない場合、▲は50keV,1.3E15cm−2の場合、○は20keV,1.3E15cm−2の場合、△は10keV,1.3E15cm−2の場合、□は周辺砒素注入(図5(B)の注入)がなく、水素アニールがない場合を示している。また全ての場合において図5(C)の砒素注入は50keV,1.3E15cm−2である。測定点数は、ウェーハ面内においてそれぞれ46点ずつである。
[変形例]
第1実施形態では、MISキャパシタを形成するためのイオン注入の回数が1回の例を説明したが、複数回のイオン注入により、不純物拡散層を形成しても良い。
[第2実施形態]
以下、本発明の第2実施形態による半導体装置の製造方法を図11を用いて説明する。図11は、本実施形態による半導体装置の製造方法を示す工程断面図である。図中、図5と図6において用いた符号と同一の符号は、同一のものを示すものとし、その説明を省略する。
12…素子分離領域
13…レジストパターン
14…不純物拡散領域
15…レジストパターン
16…不純物拡散領域
17…不純物拡散領域
18…容量絶縁膜
19…増速酸化膜
20…ゲート絶縁膜
21…熱酸化膜
22…レジストパターン
23…ゲート絶縁膜
24…キャパシタ電極
25…ゲート電極
26…ゲート電極
Claims (10)
- 半導体基板の第1の半導体領域に、第1のマスクを用いて第1のドーズ量の不純物イオンを注入し、キャパシタの下部電極となる第1の不純物拡散領域を形成するとともに、前記半導体基板の端部における第2の半導体領域に、前記第1のドーズ量の不純物イオンを注入して、第2の不純物拡散領域を形成する工程と、
前記第2の半導体領域に、第2のマスクを用いて、第2のドーズ量の不純物イオンを注入し、第3の不純物拡散領域を形成する工程と、
熱酸化法により、前記第1の不純物拡散領域上に第1の膜厚を有するキャパシタ絶縁膜を形成し、前記第2の半導体領域上に前記第1の膜厚よりも厚い第2の膜厚を有する酸化膜を形成し、前記半導体基板の第3の半導体領域上に前記第1の膜厚よりも薄い第3の膜厚を有する酸化膜を形成する工程と、
前記第3の膜厚を有する酸化膜を形成した後、前記第3の膜厚を有する酸化膜を選択的に除去するとともに、前記第2の膜厚を有する酸化膜の一部も同時にエッチングして、前記第2の膜厚が減少した前記酸化膜を残存させる工程と、
次いで、水素雰囲気中でアニールを行なう工程と、
次いで、前記第3の半導体領域上にゲート絶縁膜を形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記キャパシタ絶縁膜を形成する工程において、前記半導体基板の第4の半導体領域上に前記キャパシタ絶縁膜よりも薄い酸化膜を形成することを特徴とする半導体装置の製造方法。 - 請求項1又は2に記載の半導体装置の製造方法において、
前記第1のマスクと前記第2のマスクは、前記半導体基板の端部からの距離が異なることを特徴とする半導体装置の製造方法。 - 請求項1乃至3のいずれか1項に記載の半導体装置の製造方法において、
前記第1のドーズ量の不純物イオンを注入する工程は、
第1の注入エネルギーで前記不純物イオンを注入する工程と、
前記第1の注入エネルギーよりも高い第2の注入エネルギーで前記不純物イオンを注入する工程を有することを特徴とする半導体装置の製造方法。 - 請求項1乃至4のいずれか1項に記載の半導体装置の製造方法において、
前記第1の不純物拡散領域を形成した後、注入欠陥を除去するアニールを行なうことを特徴とする半導体装置の製造方法。 - 請求項1乃至5のいずれか1項に記載の半導体装置の製造方法において、
前記第2のドーズ量は3×1015cm-2以上であることを特徴とする半導体装置の製造方法。 - 請求項1乃至5のいずれか1項に記載の半導体装置の製造方法において、
前記第1のドーズ量は1.3×1015cm-2であることを特徴とする半導体装置の製造方法。 - 半導体基板の第1の半導体領域及び第2の半導体領域を覆う第1のマスクを形成し、前記半導体基板の第3の半導体領域に第1の不純物を注入する工程と、
前記第2の半導体領域を覆う第2のマスクを形成し、前記第1の半導体領域及び前記第3の半導体領域に第2の不純物を注入する工程と、
前記半導体基板に熱酸化法である第1の熱処理を行なうことにより、前記第1の半導体領域上に第1の膜厚を有するキャパシタ絶縁膜を形成し、前記第3の半導体領域上に前記第1の膜厚よりも厚い第2の膜厚を有する第1の酸化膜を形成し、第2の半導体領域上に前記第1の膜厚よりも薄い第3の膜厚を有する第2の酸化膜を形成する工程と、
少なくとも前記第1の半導体領域を覆う第3のマスクを形成し、前記第2の酸化膜を除去するとともに、前記第1の酸化膜の一部も同時にエッチングして、膜厚が減少した前記第1の酸化膜を残存させる工程と、
前記第2の酸化膜を除去した後、前記半導体基板に水素雰囲気中での第2の熱処理を行なう工程と、
前記第2の熱処理の後、前記半導体基板に第3の熱処理を行い、前記第2の半導体領域にゲート絶縁膜を形成する工程と、
前記キャパシタ絶縁膜上にキャパシタ電極を形成し、前記ゲート絶縁膜上にゲート電極を形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記第1の不純物のドーズ量は3×1015cm-2以上であることを特徴とする半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記第2の不純物のドーズ量は1.3×1015cm-2であることを特徴とする半導体装置の製造方法。
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JP2004039814A (ja) * | 2002-07-02 | 2004-02-05 | Fujitsu Ltd | 半導体集積回路装置およびその製造方法 |
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