JP2005294771A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000012535 impurity Substances 0.000 claims abstract description 81
- 239000003990 capacitor Substances 0.000 claims abstract description 62
- 238000009792 diffusion process Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 150000002500 ions Chemical class 0.000 claims abstract description 19
- 238000002513 implantation Methods 0.000 claims description 32
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 22
- 230000003647 oxidation Effects 0.000 claims description 22
- 239000001257 hydrogen Substances 0.000 claims description 21
- 229910052739 hydrogen Inorganic materials 0.000 claims description 21
- 238000000137 annealing Methods 0.000 claims description 20
- 239000012298 atmosphere Substances 0.000 claims description 11
- 230000007547 defect Effects 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 description 41
- 229910052785 arsenic Inorganic materials 0.000 description 31
- 238000005468 ion implantation Methods 0.000 description 26
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 19
- 239000010410 layer Substances 0.000 description 15
- -1 first Substances 0.000 description 13
- 238000000206 photolithography Methods 0.000 description 12
- 238000002955 isolation Methods 0.000 description 9
- 239000000126 substance Substances 0.000 description 7
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 4
- 230000001186 cumulative effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
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Abstract
【解決手段】半導体基板の第1の半導体領域に、第1のドーズ量の不純物イオンを注入して、キャパシタの下部電極となる第1の不純物拡散領域を形成する工程と、前記半導体基板の端部における第2の半導体領域に、第2のドーズ量の不純物イオンを注入して、第2の不純物拡散領域を形成する工程と、熱酸化法により、前記第1の不純物拡散領域上に第1の膜厚を有するキャパシタ絶縁膜を形成するとともに、前記第2の半導体領域上に、前記第1の膜厚よりも厚い第2の膜厚を有する酸化膜を形成する工程とを含む。
【選択図】図5
Description
[第1実施形態]
以下、本発明の第1実施形態による半導体装置の製造方法を図5と図6を用いて説明する。図5と図6は、本実施形態による半導体装置の製造方法を示す工程断面図である。
(評価結果)
図9は、nチャネルMISトランジスタにおけるVthのウェーハ面内の累積確率を示す図である。図中、縦軸は累積確率を示し、横軸はVthを示している。また、●は周辺砒素注入(図5(B)の注入)がない場合、▲は50keV,1.3E15cm−2の場合、○は20keV,1.3E15cm−2の場合、△は10keV,1.3E15cm−2の場合、□は周辺砒素注入(図5(B)の注入)がなく、水素アニールがない場合を示している。また全ての場合において図5(C)の砒素注入は50keV,1.3E15cm−2である。測定点数は、ウェーハ面内においてそれぞれ46点ずつである。
[変形例]
第1実施形態では、MISキャパシタを形成するためのイオン注入の回数が1回の例を説明したが、複数回のイオン注入により、不純物拡散層を形成しても良い。
[第2実施形態]
以下、本発明の第2実施形態による半導体装置の製造方法を図11を用いて説明する。図11は、本実施形態による半導体装置の製造方法を示す工程断面図である。図中、図5と図6において用いた符号と同一の符号は、同一のものを示すものとし、その説明を省略する。
12…素子分離領域
13…レジストパターン
14…不純物拡散領域
15…レジストパターン
16…不純物拡散領域
17…不純物拡散領域
18…容量絶縁膜
19…増速酸化膜
20…ゲート絶縁膜
21…熱酸化膜
22…レジストパターン
23…ゲート絶縁膜
24…キャパシタ電極
25…ゲート電極
26…ゲート電極
Claims (10)
- 半導体基板の第1の半導体領域に、第1のドーズ量の不純物イオンを注入して、キャパシタの下部電極となる第1の不純物拡散領域を形成する工程と、
前記半導体基板の端部における第2の半導体領域に、第2のドーズ量の不純物イオンを注入して、第2の不純物拡散領域を形成する工程と、
熱酸化法により、前記第1の不純物拡散領域上に第1の膜厚を有するキャパシタ絶縁膜を形成するとともに、前記第2の半導体領域上に、前記第1の膜厚よりも厚い第2の膜厚を有する酸化膜を形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 半導体基板の第1の半導体領域に、第1のマスクを用いて第1のドーズ量の不純物イオンを注入し、キャパシタの下部電極となる第1の不純物拡散領域を形成するとともに、前記半導体基板の端部における第2の半導体領域に、前記第1のドーズ量の不純物イオンを注入して、第2の不純物拡散領域を形成する工程と、
前記第2の半導体領域に、第2のマスクを用いて、第2のドーズ量の不純物イオンを注入し、第3の不純物拡散領域を形成する工程と、
熱酸化法により、前記第1の不純物拡散領域上に第1の膜厚を有するキャパシタ絶縁膜を形成するとともに、前記第2の半導体領域上に、前記第1の膜厚よりも厚い第2の膜厚を有する酸化膜を形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 半導体基板の第1の半導体領域に、第1のマスクを用いて第1のドーズ量の不純物イオンを注入し、キャパシタの下部電極となる第1の不純物拡散領域を形成するとともに、前記半導体基板の端部における第2の半導体領域に、前記第1のドーズ量の不純物イオンを注入して、第2の不純物拡散領域を形成する工程と、
第2の半導体領域に、第2のマスクを用いて、第2のドーズ量の不純物イオンを注入し、第3の不純物拡散領域を形成する工程と、
熱酸化法により、前記第1の不純物拡散領域上に第1の膜厚を有するキャパシタ絶縁膜を形成し、前記第2の半導体領域上に前記第1の膜厚よりも厚い第2の膜厚を有する酸化膜を形成し、第3の半導体領域上に前記第1の膜厚よりも薄い第3の膜厚を有する酸化膜を形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項3に記載の半導体装置の製造方法において、
前記キャパシタ絶縁膜を形成する工程において、第4の半導体領域上に前記キャパシタ絶縁膜よりも薄い酸化膜を形成することを特徴とする半導体装置の製造方法。 - 請求項3または4に記載の半導体装置の製造方法において、
前記第3の膜厚を有する酸化膜を形成した後、前記第3の膜厚を有する酸化膜を選択的に除去する工程をさらに有することを特徴とする半導体装置の製造方法。 - 請求項5に記載の半導体装置の製造方法において、
前記第3の膜厚を有する酸化膜を選択的に除去する際、前記第2の膜厚を有する酸化膜の一部も同時にエッチングし、
次いで、水素雰囲気中でアニールを行なう工程をさらに含むことを特徴とする半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記水素雰囲気中でアニールを行なう工程の後、 前記第3の半導体領域上にゲート絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。 - 請求項2乃至7のいずれか1項に記載の半導体装置の製造方法において、
前記第1のマスクと前記第2のマスクは、前記半導体基板の端部からの距離が異なることを特徴とする半導体装置の製造方法。 - 請求項1乃至8のいずれか1項に記載の半導体装置の製造方法において、
前記第1のドーズ量の不純物イオンを注入する工程は、
第1の注入エネルギーで前記不純物イオンを注入する工程と、
前記第1の注入エネルギーよりも高い第2の注入エネルギーで前記不純物イオンを注入する工程を有することを特徴とする半導体装置の製造方法。 - 請求項1乃至9のいずれか1項に記載の半導体装置の製造方法において、
前記第1の不純物拡散領域を形成した後、注入欠陥を除去するアニールを行なうことを特徴とする半導体装置の製造方法。
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JP2010165739A (ja) * | 2009-01-13 | 2010-07-29 | Toshiba Corp | 半導体装置の製造方法 |
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US7294554B2 (en) * | 2006-02-10 | 2007-11-13 | International Business Machines Corporation | Method to eliminate arsenic contamination in trench capacitors |
US7951897B2 (en) * | 2007-01-26 | 2011-05-31 | Bausch & Lomb Incorporated | Synthesis of cationic siloxane prepolymers |
US7521330B2 (en) * | 2007-06-04 | 2009-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for forming capacitor structures |
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CN103367141B (zh) * | 2012-04-09 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | 功函数测试方法 |
US9899372B1 (en) * | 2016-10-31 | 2018-02-20 | International Business Machines Corporation | Forming on-chip metal-insulator-semiconductor capacitor |
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JP2002184774A (ja) * | 2000-12-14 | 2002-06-28 | Mitsubishi Materials Silicon Corp | シリコン酸化膜の形成方法と半導体ウェーハ、及びmosデバイス用ウェーハの製造方法とmosデバイス用ウェーハ |
JP2003060097A (ja) * | 2001-08-17 | 2003-02-28 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2004006898A (ja) * | 1992-05-22 | 2004-01-08 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法および製造装置 |
JP2004039814A (ja) * | 2002-07-02 | 2004-02-05 | Fujitsu Ltd | 半導体集積回路装置およびその製造方法 |
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US6764930B2 (en) * | 2001-09-26 | 2004-07-20 | Agere Systems Inc. | Method and structure for modular, highly linear MOS capacitors using nitrogen implantation |
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JP2004006898A (ja) * | 1992-05-22 | 2004-01-08 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法および製造装置 |
JPH05326841A (ja) * | 1992-05-25 | 1993-12-10 | Nec Corp | 半導体装置の製造方法 |
JPH088401A (ja) * | 1994-06-17 | 1996-01-12 | Toyota Motor Corp | 半導体装置の製造方法 |
JPH0897363A (ja) * | 1994-07-27 | 1996-04-12 | Matsushita Electron Corp | Mosキャパシタおよびその製造方法 |
JPH1041403A (ja) * | 1996-07-22 | 1998-02-13 | Nec Corp | 半導体装置およびその製造方法 |
JPH118352A (ja) * | 1997-06-14 | 1999-01-12 | Toshiba Microelectron Corp | 半導体集積回路装置及びその製造方法 |
JP2002184774A (ja) * | 2000-12-14 | 2002-06-28 | Mitsubishi Materials Silicon Corp | シリコン酸化膜の形成方法と半導体ウェーハ、及びmosデバイス用ウェーハの製造方法とmosデバイス用ウェーハ |
JP2003060097A (ja) * | 2001-08-17 | 2003-02-28 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2004039814A (ja) * | 2002-07-02 | 2004-02-05 | Fujitsu Ltd | 半導体集積回路装置およびその製造方法 |
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JP2010165739A (ja) * | 2009-01-13 | 2010-07-29 | Toshiba Corp | 半導体装置の製造方法 |
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US20050221556A1 (en) | 2005-10-06 |
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