CN108109900A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN108109900A
CN108109900A CN201611048954.5A CN201611048954A CN108109900A CN 108109900 A CN108109900 A CN 108109900A CN 201611048954 A CN201611048954 A CN 201611048954A CN 108109900 A CN108109900 A CN 108109900A
Authority
CN
China
Prior art keywords
area
coating
nitride
oxide skin
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201611048954.5A
Other languages
English (en)
Other versions
CN108109900B (zh
Inventor
禹国宾
徐小平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201611048954.5A priority Critical patent/CN108109900B/zh
Priority to EP17202874.8A priority patent/EP3327752B1/en
Priority to US15/821,349 priority patent/US10490674B2/en
Publication of CN108109900A publication Critical patent/CN108109900A/zh
Priority to US16/502,610 priority patent/US11069821B2/en
Application granted granted Critical
Publication of CN108109900B publication Critical patent/CN108109900B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

本发明公开了一种半导体装置及其制造方法，涉及半导体技术领域。其中，所述方法包括：提供半导体衬底，所述半导体衬底包括彼此间隔开的第一区域和第二区域，所述第一区域和所述第二区域的表面具有第一氧化物层；执行氮化处理，以在所述第一区域和所述第二区域的表面的第一氧化物层的顶部区域形成氮化物阻挡层；去除所述第二区域上经氮化处理后的第一氧化物层；执行氧化处理，以在所述第二区域的表面形成第二氧化物层。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体装置及其制造方法。
背景技术
NOR闪存存储器(NOR flash memory)被广泛用在嵌入式系统中来存储和读取程序。与NAND闪存存储器相比，NOR闪存存储器在读取数据的性能方面更优，并且支持芯片内执行(eXecute-In-Place，XIP)来直接运行程序。
然而，发明人发现：随着NOR闪存存储器的闪存单元密度的增加，有些区域的闪存器件的隧穿氧化层要比期望的厚度更大，这使得这些区域的闪存器件的阈值电压会增大。
发明内容
本发明的一个的目的在于提出一种半导体装置的制造方法，能够阻止特定区域的氧化层的厚度不期望地增大。
根据本发明的一个实施例，提供了一种半导体装置的制造方法，包括：提供半导体衬底，所述半导体衬底包括彼此间隔开的第一区域和第二区域，所述第一区域和所述第二区域的表面具有第一氧化物层；执行氮化处理，以在所述第一区域和所述第二区域的表面的第一氧化物层的顶部区域形成氮化物阻挡层；去除所述第二区域上经氮化处理后的第一氧化物层；执行氧化处理，以在所述第二区域的表面形成第二氧化物层。
在一个实施例中，所述半导体衬底还包括与所述第一区域和所述第二区域间隔开的第三区域，所述第三区域的表面上具有第三氧化物层；所述氮化处理还在所述第三氧化物层的顶部区域形成氮化物阻挡层；其中，所述第三氧化物层的厚度大于所述第二氧化物层的厚度。
在一个实施例中，所述提供半导体衬底包括：提供具有彼此间隔开的第一区域、第二区域和第三区域的半导体衬底；通过氧化工艺在所述第一区域、所述第二区域和所述第三区域的表面上形成第三氧化物层；去除所述第一区域和所述第二区域的表面上的第三氧化物层；通过氧化工艺在所述第一区域和所述第二区域的表面上形成第一氧化物层。
在一个实施例中，所述执行氮化处理包括：进行去耦等离子体氮化DPN工艺；进行氮化后退火PNA工艺。
在一个实施例中，所述去除所述第二区域上经氮化处理后的第一氧化物层包括：在执行氮化处理后的半导体衬底上形成掩模层；对所述掩模层进行图案化，以暴露所述第二区域上经氮化处理后的第一氧化物层；去除所述第二区域上经氮化处理后的第一氧化物层。
在一个实施例中，所述掩模层包括用于防止光刻胶中毒的保护层和在所述保护层上的光刻胶；所述方法还包括：去除剩余的掩模层；或者去除剩余的光刻胶，保留剩余的保护层。
在一个实施例中，所述保护层包括氧化硅、非晶碳或多晶硅。
在一个实施例中，所述氮化处理中氮的剂量为5×1015atoms/cm2至2×1016atoms/cm2。
在一个实施例中，所述氮化物阻挡层包括SiON。
在一个实施例中，所述氮化物阻挡层的厚度为3埃至50埃。
在一个实施例中，所述第一氧化物层为用于闪存器件的隧穿氧化物层。
在一个实施例中，所述方法还包括：在所述第一区域上的氮化物阻挡层上形成浮栅和控制栅。
根据本发明的另一个实施例，提供了一种半导体装置，包括：半导体衬底，所述半导体衬底包括彼此间隔开的第一区域和第二区域；在所述第一区域的表面上的第一氧化物层，所述第一氧化物层的顶部区域具有氮化物阻挡层；以及在所述第二区域的表面上的第二氧化物层。
在一个实施例中，所述半导体衬底还包括与所述第一区域和所述第二区域间隔开的第三区域；所述装置还包括：在所述第三区域的表面上的第三氧化物层，所述第三氧化物层的顶部区域具有氮化物阻挡层；其中，所述第三氧化物层的厚度大于所述第二氧化物层的厚度。
在一个实施例中，所述装置还包括：在所述氮化物阻挡层上用于防止光刻胶中毒的保护层。
在一个实施例中，所述保护层包括氧化硅、非晶碳或多晶硅。
在一个实施例中，所述氮化物阻挡层包括SiON。
在一个实施例中，所述氮化物阻挡层的厚度为3埃至50埃。
在一个实施例中，所述第一氧化物层为用于闪存器件的隧穿氧化物层。
在一个实施例中，所述装置还包括：在所述氮化物阻挡层上的浮栅和控制栅。
本发明提供的半导体装置的制造方法中，由于第一区域的第一氧化物层的表面形成有氮化物阻挡层，因此后续在第二区域形成第二氧化物层的氧化处理工艺中氮化物阻挡层可以阻止氧进入第一区域的第一氧化物层，从而使得第一区域的第一氧化物层的厚度不会继续增大，避免由于第一区域的第一氧化物层的厚度超过期望的厚度而影响器件(例如闪存器件)的阈值电压。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本发明的示例性实施例，并且连同说明书一起用于解释本发明的原理，在附图中：
图1是根据本发明一个实施例的半导体装置的制造方法的流程图；
图2-图5示出了根据本发明一个实施例的半导体装置的制造方法的各个阶段的截面图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本发明范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
发明人针对上述问题进行了深入研究，结果发现：不同的器件，例如高压器件(High Voltage)、低压器件(Low Voltage)、闪存器件等可能需要同时制造，在形成用于闪存器件的隧穿氧化层后，可能还需要形成用于其他器件的氧化层，而在形成用于其他器件的氧化层时可能会使得隧穿氧化层的厚度进一步增大，从而使得最终形成的闪存器件的阈值电压增大。据此，发明人提出了如下解决方案。
图1是根据本发明一个实施例的半导体装置的制造方法的流程图。图2-图5示出了根据本发明一个实施例的半导体装置的制造方法的各个阶段的截面图。下面结合图1、图2-图5对根据本发明一个实施例的半导体装置的制造方法进行说明。
首先，在步骤102，提供半导体衬底201。如图2所示，半导体衬底201包括彼此间隔开的第一区域211和第二区域221，第一区域211和第二区域221之间可以通过隔离结构202(例如浅沟槽隔离结构)隔离开。第一区域211和第二区域221的表面具有第一氧化物层203。
在一个实施例中，半导体衬底201还可以包括与第一区域211和第二区域221间隔开的第三区域231，第三区域231的表面上具有第三氧化物层204。这里，第一区域211可以是用于形成闪存器件的区域，第二区域221和第三区域231可以分别是用于形成低压器件和高压器件的区域。应理解，这里的低压器件和高压器件是相对的概念，低压器件的阈值电压低于高压器件的阈值电压。在一个实施例中，第一氧化物层203可以是用于闪存器件(例如NOR闪存存储器)的隧穿氧化物层，第三氧化物层204可以是用于高压器件的氧化物层。
在一个实施例中，可以通过如下方式来形成如图2所示的结构：首先，提供具有彼此间隔开的第一区域211、第二区域221和第三区域231的半导体衬底201。然后，通过氧化工艺在第一区域211、第二区域221和第三区域231的表面上形成第三氧化物层204。然后，去除第一区域211和第二区域221的表面上的第三氧化物层204，保留第三区域231的表面上的第三氧化物层204。之后，通过氧化工艺在第一区域211和第二区域221的表面上形成第一氧化物层203，从而形成了图2所示的结构。
接下来，在步骤104，执行氮化处理，以在第一区域221和第二区域231的表面的第一氧化物层203的顶部区域形成氮化物阻挡层301，例如氮氧化硅(SiON)等，如图3所示。在半导体衬底201包括第三区域231的情况下，氮化处理还在第三区域231上的第三氧化物层的顶部区域形成氮化物阻挡层301。
在一个实现方式中，执行氮化处理可以包括如下两个步骤：一是进行去耦等离子体氮化(DPN)工艺，二是进行氮化后退火(PNA)工艺。在一个实施例中，氮化处理中氮的剂量优选可以为5×1015atoms/cm2至2×1016atoms/cm2，例如7×1015atoms/cm2、9×1015atoms/cm2、1×1016atoms/cm2等。通过DPN和PNA工艺可以在第一氧化物层203的顶部区域(也即表面区域)形成很薄的一层氮化物阻挡层301。优选地，氮化物阻挡层301的厚度可以为3埃至50埃，例如10埃、30埃、40埃等。
然后，在步骤106，去除第二区域221上经氮化处理后的第一氧化物层，如图4所示。这里，去除的经氮化处理后的第一氧化物层包括第一氧化物层203及其表面上的氮化物阻挡层301。
在一个实现方式中，可以通过如下方式来去除第二区域221上经氮化处理后的第一氧化物层：
首先，在执行氮化处理后的半导体衬底201上形成掩模层。在一个实施例中，掩模层可以包括光刻胶。在另一个实施例中，掩模层可以包括用于防止光刻胶中毒的保护层和在保护层上的光刻胶，保护层的存在可以防止富氮的氮化物阻挡层使得光刻胶中毒。优选地，保护层可以包括氧化硅、非晶碳或多晶硅。例如，可以通过原子层沉积(ALD)、化学气相沉积(CVD)或炉管氧化等方式来形成保护层。然后，对掩模层进行图案化，以暴露第二区域上经氮化处理后的第一氧化物层。之后，去除第二区域上经氮化处理后的第一氧化物层。之后，可以去除剩余的掩模层。或者，也可以仅去除剩余的光刻胶，而保留剩余的保护层。
接下来，在步骤108，执行氧化处理，以在第二区域221的表面形成第二氧化物层501。这里，第二氧化物层501可以是用于形成低压器件的氧化层。第三氧化物层204的厚度大于第二氧化物层501的厚度。
如上描述了根据本发明一个实施例的半导体装置的制造方法。由于第一区域的第一氧化物层的表面形成有氮化物阻挡层，因此后续在第二区域形成第二氧化物层的氧化处理工艺中氮化物阻挡层可以阻止氧进入第一区域的第一氧化物层，从而使得第一区域的第一氧化物层的厚度不会继续增大，避免由于第一区域的第一氧化物层的厚度超过期望的厚度而影响器件(例如闪存器件)的阈值电压。
需要说明的是，本发明提供的方法中的第一氧化物层可以包括但不限于隧穿氧化物层。因此，本发明提供的方法并不限于闪存器件，也适于具有类似问题的其他类型的器件。
之后可以进行标准的闪存器件的制造工艺，例如，可以在第一区域上的氮化物阻挡层上形成浮栅和控制栅。还可以在第二区域的第二氧化物层上形成低压器件，在第三区域的第三氧化物层上形成高压器件，这里的低压器件和高压器件例如可以是逻辑器件等。由于这部分内容并非本发明关注的重点，在此不再赘述。
本发明还提供了一种半导体装置，如图5所示，半导体装置可以包括半导体衬底201，半导体衬底201包括彼此间隔开的第一区域211和第二区域221。第一区域211和第二区域221例如可以通过诸如浅沟槽隔离结构的隔离结构202间隔开。
半导体装置还可以包括在第一区域211的表面上的第一氧化物层203，第一氧化物层203的顶部区域具有氮化物阻挡层301，例如SiON。优选地，氮化物阻挡层301的厚度可以为3埃至50埃，例如10埃、30埃、40埃等。在一个实施例中，第一氧化物层203可以为用于闪存器件的隧穿氧化物层。
半导体装置还可以包括在第二区域221的表面上的第二氧化物层501。
在一个实施例中，参见图5，半导体衬底还可以包括与第一区域211和第二区域221间隔开的第三区域231。该实施例中，半导体装置还可以包括在第三区域231的表面上的第三氧化物层204。第三氧化物层204的顶部区域具有氮化物阻挡层301，例如SiON。这里，第三氧化物层204的厚度大于第二氧化物层501的厚度。
在一个实施例中，半导体装置还可以包括在氮化物阻挡层301上用于防止光刻胶中毒的保护层(未示出)，例如氧化硅、非晶碳或多晶硅。
在其他的实施例中，半导体装置还可以包括在第一区域211上的氮化物阻挡层301上的浮栅和控制栅(未示出)。
至此，已经详细描述了根据本发明实施例的半导体装置及其制造方法。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本发明的精神和范围。

Claims (20)

1.一种半导体装置的制造方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底包括彼此间隔开的第一区域和第二区域，所述第一区域和所述第二区域的表面具有第一氧化物层；
执行氮化处理，以在所述第一区域和所述第二区域的表面的第一氧化物层的顶部区域形成氮化物阻挡层；
去除所述第二区域上经氮化处理后的第一氧化物层；
执行氧化处理，以在所述第二区域的表面形成第二氧化物层。
2.根据权利要求1所述的方法，其特征在于，所述半导体衬底还包括与所述第一区域和所述第二区域间隔开的第三区域，所述第三区域的表面上具有第三氧化物层；
所述氮化处理还在所述第三氧化物层的顶部区域形成氮化物阻挡层；
其中，所述第三氧化物层的厚度大于所述第二氧化物层的厚度。
3.根据权利要求2所述的方法，其特征在于，所述提供半导体衬底包括：
提供具有彼此间隔开的第一区域、第二区域和第三区域的半导体衬底；
通过氧化工艺在所述第一区域、所述第二区域和所述第三区域的表面上形成第三氧化物层；
去除所述第一区域和所述第二区域的表面上的第三氧化物层；
通过氧化工艺在所述第一区域和所述第二区域的表面上形成第一氧化物层。
4.根据权利要求1或2所述的方法，其特征在于，所述执行氮化处理包括：
进行去耦等离子体氮化工艺；
进行氮化后退火工艺。
5.根据权利要求1所述的方法，其特征在于，所述去除所述第二区域上经氮化处理后的第一氧化物层包括：
在执行氮化处理后的半导体衬底上形成掩模层；
对所述掩模层进行图案化，以暴露所述第二区域上经氮化处理后的第一氧化物层；
去除所述第二区域上经氮化处理后的第一氧化物层。
6.根据权利要求5所述的方法，其特征在于，所述掩模层包括用于防止光刻胶中毒的保护层和在所述保护层上的光刻胶；
所述方法还包括：
去除剩余的掩模层；或者
去除剩余的光刻胶，保留剩余的保护层。
7.根据权利要求6所述的方法，其特征在于，所述保护层包括氧化硅、非晶碳或多晶硅。
8.根据权利要求1所述的方法，其特征在于，所述氮化处理中氮的剂量为5×1015atoms/cm2至2×1016atoms/cm2。
9.根据权利要求1所述的方法，其特征在于，所述氮化物阻挡层包括SiON。
10.根据权利要求1所述的方法，其特征在于，所述氮化物阻挡层的厚度为3埃至50埃。
11.根据权利要求1所述的方法，其特征在于，所述第一氧化物层为用于闪存器件的隧穿氧化物层。
12.根据权利要求1所述的方法，其特征在于，还包括：
在所述第一区域上的氮化物阻挡层上形成浮栅和控制栅。
13.一种半导体装置，其特征在于，包括：
半导体衬底，所述半导体衬底包括彼此间隔开的第一区域和第二区域；
在所述第一区域的表面上的第一氧化物层，所述第一氧化物层的顶部区域具有氮化物阻挡层；以及
在所述第二区域的表面上的第二氧化物层。
14.根据权利要求13所述的装置，其特征在于，所述半导体衬底还包括与所述第一区域和所述第二区域间隔开的第三区域；
所述装置还包括：
在所述第三区域的表面上的第三氧化物层，所述第三氧化物层的顶部区域具有氮化物阻挡层；
其中，所述第三氧化物层的厚度大于所述第二氧化物层的厚度。
15.根据权利要求13或14所述的装置，其特征在于，还包括：
在所述氮化物阻挡层上用于防止光刻胶中毒的保护层。
16.根据权利要求15所述的装置，其特征在于，所述保护层包括氧化硅、非晶碳或多晶硅。
17.根据权利要求13或14所述的装置，其特征在于，所述氮化物阻挡层包括SiON。
18.根据权利要求13或14所述的装置，其特征在于，所述氮化物阻挡层的厚度为3埃至50埃。
19.根据权利要求13所述的装置，其特征在于，所述第一氧化物层为用于闪存器件的隧穿氧化物层。
20.根据权利要求13所述的装置，其特征在于，还包括：
在所述氮化物阻挡层上的浮栅和控制栅。
CN201611048954.5A 2016-11-24 2016-11-24 半导体装置及其制造方法 Active CN108109900B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201611048954.5A CN108109900B (zh) 2016-11-24 2016-11-24 半导体装置及其制造方法
EP17202874.8A EP3327752B1 (en) 2016-11-24 2017-11-21 A semiconductor device and manufacturing method thereof
US15/821,349 US10490674B2 (en) 2016-11-24 2017-11-22 Semiconductor device and manufacturing method thereof
US16/502,610 US11069821B2 (en) 2016-11-24 2019-07-03 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611048954.5A CN108109900B (zh) 2016-11-24 2016-11-24 半导体装置及其制造方法

Publications (2)

Publication Number Publication Date
CN108109900A true CN108109900A (zh) 2018-06-01
CN108109900B CN108109900B (zh) 2021-04-09

Family

ID=60450448

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611048954.5A Active CN108109900B (zh) 2016-11-24 2016-11-24 半导体装置及其制造方法

Country Status (3)

Country Link
US (2) US10490674B2 (zh)
EP (1) EP3327752B1 (zh)
CN (1) CN108109900B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113488436A (zh) * 2021-09-06 2021-10-08 晶芯成(北京)科技有限公司 一种半导体结构及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020073925A1 (en) * 1999-04-22 2002-06-20 David B. Noble Apparatus and method for exposing a substrate to plasma radicals
US20030008526A1 (en) * 2001-01-16 2003-01-09 International Business Machines Corporation Method of forming variable oxide thicknesses across semiconductor chips
US6855627B1 (en) * 2002-12-04 2005-02-15 Advanced Micro Devices, Inc. Method of using amorphous carbon to prevent resist poisoning
JP2008016499A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置およびその製造方法
US20110003467A1 (en) * 2009-07-06 2011-01-06 Elpida Memory, Inc. Method of manufacturing semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759302B1 (en) * 2002-07-30 2004-07-06 Taiwan Semiconductor Manufacturing Company Method of generating multiple oxides by plasma nitridation on oxide
JP4190940B2 (ja) * 2003-05-13 2008-12-03 エルピーダメモリ株式会社 半導体装置の製造方法
EP2412031A2 (en) * 2009-03-25 2012-02-01 Dow Global Technologies LLC Method of forming a protective layer on thin-film photovoltaic articles and articles made with such a layer
CN102237365B (zh) * 2010-04-28 2013-01-02 中国科学院微电子研究所 一种闪存器件及其制造方法
CN106887408B (zh) * 2015-12-15 2019-12-17 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020073925A1 (en) * 1999-04-22 2002-06-20 David B. Noble Apparatus and method for exposing a substrate to plasma radicals
US20030008526A1 (en) * 2001-01-16 2003-01-09 International Business Machines Corporation Method of forming variable oxide thicknesses across semiconductor chips
US6855627B1 (en) * 2002-12-04 2005-02-15 Advanced Micro Devices, Inc. Method of using amorphous carbon to prevent resist poisoning
JP2008016499A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置およびその製造方法
US20110003467A1 (en) * 2009-07-06 2011-01-06 Elpida Memory, Inc. Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113488436A (zh) * 2021-09-06 2021-10-08 晶芯成(北京)科技有限公司 一种半导体结构及其制造方法
CN113488436B (zh) * 2021-09-06 2021-12-21 晶芯成(北京)科技有限公司 一种半导体结构及其制造方法

Also Published As

Publication number Publication date
US20190326441A1 (en) 2019-10-24
EP3327752A1 (en) 2018-05-30
US10490674B2 (en) 2019-11-26
US20180145182A1 (en) 2018-05-24
EP3327752B1 (en) 2019-07-03
US11069821B2 (en) 2021-07-20
CN108109900B (zh) 2021-04-09

Similar Documents

Publication Publication Date Title
US8198667B2 (en) Semiconductor memory device and method for manufacturing same
KR101904413B1 (ko) 스페이서 이중 패턴화를 위한 자기 정렬 낸드 플래시 선택 게이트 워드라인
US8593001B2 (en) Patterned semiconductor bases
US8569130B2 (en) Forming air gaps in memory arrays and memory arrays with air gaps thus formed
TW200845125A (en) Semiconductor constructions, methods of forming multiple lines, and methods of forming high density structures and low density structures with a single photomask
CN106653758B (zh) 快闪存储器的制作方法
JP2009200460A (ja) 半導体素子およびその製造方法
US8680671B2 (en) Self-aligned double patterning for memory and other microelectronic devices
TWI376770B (en) Method of manufacturing sidewall spacers on a memory device, and device comprising same
CN108109900A (zh) 半导体装置及其制造方法
CN107958908A (zh) Sonos器件的形成方法
US6716694B2 (en) Semiconductor devices and methods for manufacturing semiconductor devices
CN108630700A (zh) 闪存器件及其制造方法
US20080087954A1 (en) Semiconductor device having nitridated oxide layer and method therefor
US9748360B2 (en) Manufacturing method of semiconductor device
TW200933747A (en) Selective silicide formation using resist etch back
JP6474349B2 (ja) 高電圧ゲート形成
TW201036111A (en) Method for fabricating nonvolatile memory device
CN106024718A (zh) 可优化去胶工艺的sonos存储器制造方法
JP5774720B2 (ja) エッジに丸みを付けた電界効果トランジスタおよび製造方法
US20090194804A1 (en) Non-volatile memory cell
JPH09129758A (ja) 半導体集積回路装置の製造方法
JP2001035944A (ja) フラッシュメモリ素子、その製造方法及び消去方法
JP2001284469A (ja) 半導体装置の製造方法
KR20100073397A (ko) 플래시 메모리 제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant