CN110854075B - Cmos器件制造方法 - Google Patents

Cmos器件制造方法 Download PDF

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CN110854075B
CN110854075B CN201911107530.5A CN201911107530A CN110854075B CN 110854075 B CN110854075 B CN 110854075B CN 201911107530 A CN201911107530 A CN 201911107530A CN 110854075 B CN110854075 B CN 110854075B
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silicon nitride
nitride film
ion implantation
side wall
ald
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CN110854075A (zh
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李润领
陈雪飞
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

本申请公开了一种CMOS器件的制造方法，涉及半导体制造领域。该方法包括在衬底上形成栅极结构和栅极侧墙，所述栅极侧墙为氮化硅材料；沉积ALD氮化硅薄膜，所述ALD氮化硅薄膜覆盖所述衬底表面、所述栅极结构以及所述栅极侧墙；进行离子注入光刻工艺，形成离子注入区图案；解决了现有工艺中，氮化硅侧墙形成后，进行光刻工艺时光刻胶容易出现缺角的问题；达到了避免光刻胶出现倒角、缺角显现，保证离子注入区图案准确性的效果。

Description

CMOS器件制造方法
技术领域
本申请涉及半导体制造领域，具体涉及一种CMOS器件制造方法。
背景技术
在集成电路制造主流工艺中，栅极侧墙通常采用氮化硅材料，而光刻工艺中使用的光刻胶对含氮材料较为敏感，氮化硅材料容易引起光刻胶变性从而产生倒角现象。现有工艺为了解决倒角现象，通常在光刻之前采用氧气等离子体进行界面处理。
然而，在45/40nm及其以下技术节点，由于有源区和浅沟槽隔离的光反射作用，氧气等离子体进行界面处理容易产生光刻胶底部的缺角问题，甚至导致图案失真，影响诸如轻掺杂漏(LDD)/卤素离子注入、S/D(源/漏)离子注入之类的离子注入定义的区域，进而影响器件性能。
发明内容
本申请提供了一种CMOS器件制造方法，可以解决相关技术中光刻胶缺角造成离子注入区图案失真的问题。
一方面，本申请实施例提供了一种CMOS器件制造方法，该方法包括：
在衬底上形成栅极结构和栅极侧墙，栅极侧墙为氮化硅材料；
沉积ALD氮化硅薄膜，ALD氮化硅薄膜覆盖衬底表面、栅极结构以及栅极侧墙；
进行离子注入光刻工艺，形成离子注入区图案。
可选的，ALD氮化硅薄膜的厚度为10至50埃。
可选的，沉积ALD氮化硅薄膜时的反应温度为300摄氏度至700摄氏度。
可选的，在衬底上形成栅极结构和栅极侧墙之前，还包括：
在衬底上形成浅沟槽隔离，浅沟槽隔离用于定义有源区。
可选的，衬底上制作有PMOS器件和/或NMOS器件。
可选的，在进行离子注入光刻工艺，形成离子注入区图案之后，还包括：
进行离子注入工艺。
可选的，ALD氮化硅薄膜的材料为纯氮化硅或掺杂碳的氮化硅或掺杂硼的氮化硅。
可选的，该方法应用于40nm及40nm以下技术节点。
本申请技术方案，至少包括如下优点：
通过在衬底上形成栅极结构和氮化硅栅极侧墙，沉积ALD氮化硅薄膜，ALD氮化硅薄膜覆盖衬底表面、栅极结构和氮化硅栅极侧墙，进行离子注入光刻工艺，形成离子注入区图案；解决了现有工艺中，氮化硅侧墙形成后，进行光刻工艺时光刻胶容易出现缺角的问题；达到了避免光刻胶出现倒角、缺角显现，保证离子注入区图案准确性的效果。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种制作有栅极结构和栅极侧墙的半导体器件的示意图；
图2是现有技术中光刻工艺前进行氧气等离子体界面处理工艺的示意图；
图3是现有技术中光刻工艺后产生的缺角示意图；
图4是本申请实施例提供的一种CMOS器件制造方法的流程图；
图5是本申请实施例中沉积ALD薄膜后的示意图；
图6是本申请实施例中光刻工艺后示意图；
图7是本申请实施例提供的另一种CMOS器件制造方法的流程图；
其中，11：衬底，12：阱注入区；13：浅沟槽隔离；14：栅极结构；15：栅极侧墙；16：光刻胶；17：缺角；18：ALD氮化硅薄膜。
具体实施方式
下面将结合附图，对本申请中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电气连接；可以是直接相连，也可以通过中间媒介间接相连，还可以是两个元件内部的连通，可以是无线连接，也可以是有线连接。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
在CMOS器件制造过程中，进行光刻工艺之前，在衬底11上形成栅极14和栅极侧墙15，如图1所示。栅极侧墙15为氮化硅材料，由于光刻工艺中的光刻胶对含氮材料敏感，栅极侧墙15容易导致光刻胶变性而产生倒角现象，因此，现有工艺通常在光刻工艺之前采用氧气(O2)等离子体进行界面处理，如图2所示。
在40nm及以下技术节点，由于有源区和浅沟槽隔离的光反射作用，氧气等离子体进行界面处理容易令光刻胶16的底部产生缺角17，如图3所示。
为了解决现有的光刻工艺中光刻胶容易因有源区和浅沟槽隔离出现缺角，导致离子注入区图案的问题，本申请实施例提供了一种CMOS器件制造方法，如图4所示，该CMOS器件制造方法可以包括如下几个步骤：
步骤401，在衬底上形成栅极结构和栅极侧墙，栅极侧墙为氮化硅材料。
如图1所示，衬底11上包括阱注入区12、浅沟槽隔离13，衬底11表面形成了栅极结构14和栅极侧墙15。
步骤402，沉积ALD氮化硅薄膜，ALD氮化硅薄膜覆盖衬底表面、栅极结构以及栅极侧墙。
利用ALD(原子层沉积)技术沉积ALD氮化硅薄膜。
如图5所示，沉积ALD氮化硅薄膜18，ALD氮化硅薄膜18覆盖衬底11表面、栅极结构14和栅极侧墙15。
步骤403，进行离子注入光刻工艺，形成离子注入区图案。
根据离子注入区的位置，进行离子注入之前的光刻工艺，在衬底表面形成离子注入区图案。
由于ALD氮化硅薄膜化学键饱和度高，释放氮量较少，在衬底上旋涂光刻胶后，光刻胶会与ALD氮化硅薄膜释放出来的氮元素发生反应，导致氮化硅薄膜表面的光刻胶适量中毒，这样来自衬底的反射光不会使光刻胶底部过曝，防止光刻胶底部产生倒角，解决了光刻胶的缺角问题，避免形成的离子注入区图案失真。
如图6所示，进行离子注入光刻工艺后，光刻胶16底部没有缺角现象。
综上所述，本申请实施例通过在衬底上形成栅极结构和氮化硅栅极侧墙，沉积ALD氮化硅薄膜，ALD氮化硅薄膜覆盖衬底表面、栅极结构和氮化硅栅极侧墙，进行离子注入光刻工艺，形成离子注入区图案；解决了现有工艺中，氮化硅侧墙形成后，进行光刻工艺时光刻胶容易出现缺角的问题；达到了避免光刻胶出现倒角、缺角显现，保证离子注入区图案准确性的效果。
请参考图7，其示出了本申请实施例示出的另一种CMOS器件制造方法，如图7所示，该CMOS器件制造方法可以包括如下几个步骤：
步骤701，在衬底上形成浅沟槽隔离。
浅沟槽隔离用于定义有源区，有源区用于制作PMOS器件和/或NMOS器件。
可选的，衬底上制作有多个NMOS器件和/或PMOS器件。
步骤702，在衬底上上形成栅极结构和栅极侧墙，栅极侧墙为氮化硅材料。
步骤703，沉积ALD氮化硅薄膜，ALD氮化硅薄膜覆盖衬底表面、栅极结构以及栅极侧墙。
可选的，ALD氮化硅薄膜的厚度为10至50埃。
可选的，沉积ALD氮化硅薄膜时的反应温度为300摄氏度至700摄氏度。
可选的，ALD氮化硅薄膜的材料为纯氮化硅，或掺杂碳的氮化硅，或掺杂硼的氮化硅。
步骤704，进行离子注入光刻工艺，形成离子注入区图案。
需要说明的是，在进行离子注入光刻工艺之前，由于已经沉积了ALD氮化硅薄膜，可以不再利用氧气等离子体进行界面处理。
步骤705，进行离子注入工艺。
进行离子注入工艺时，不去除沉积的ALD氮化硅薄膜。在CMOS制造工艺中，会出现多次离子注入光刻工艺和离子注入工艺，不去除ALD氮化硅薄膜可以令ALD氮化硅薄膜在每次离子注入光刻工艺过程中起作用，避免光刻胶产生倒角、缺角现象。
需要说明的是，步骤704至步骤705可以在步骤703之后重复执行，重复执行的次数根据实际情况确定，本申请实施例对此不作限定。
综上所述，本申请实施例通过在衬底上形成浅沟槽隔离、栅极结构和氮化硅栅极侧墙，沉积ALD氮化硅薄膜，ALD氮化硅薄膜覆盖衬底表面、栅极结构和氮化硅栅极侧墙，进行离子注入光刻工艺，形成离子注入区图案；解决了现有工艺中，氮化硅侧墙形成后，进行光刻工艺时光刻胶容易出现缺角的问题；达到了在不增加成本和工艺复杂度的前提下避免光刻胶出现倒角、缺角现象，保证离子注入区图案准确性的效果。
需要说明的是，本申请实施例提供的CMOS器件制造方法主要应用于40nm及40nm以下技术节点，本申请实施例提供的CMOS器件制造方法也可以用于40nm及40nm以下技术节点以外的其他技术节点，本申请实施例对此不作限定。
在一个例子中，在PMOS器件的氮化硅栅极侧墙形成后，沉积ALD氮化硅薄膜，去掉氧气等离子体界面处理工艺，直接进行离子注入光刻工艺，可以解决由于衬底反光导致的光刻胶缺角现象和图案失真问题。
在另一个例子中，在NMOS器件的氮化硅栅极侧墙形成后，沉积ALD氮化硅薄膜，去掉氧气等离子体界面处理工艺，直接进行离子注入光刻工艺，可以解决由于衬底反光导致的光刻胶缺角现象和图案失真问题。
在又一个例子中，在N/P MOS器件的重掺杂氮化硅栅极侧墙形成后，沉积ALD氮化硅薄膜，去掉氧气等离子体界面处理工艺，直接进行离子注入光刻工艺，可以解决由于衬底反光导致的光刻胶缺角现象和图案失真问题。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请创造的保护范围之中。

Claims (6)

1.一种CMOS器件制造方法，其特征在于，所述方法包括：
在衬底上形成浅沟槽隔离，所述浅沟槽隔离用于定义有源区；
形成栅极结构和栅极侧墙，所述栅极侧墙为氮化硅材料，其中栅极侧墙不延伸到所述浅沟槽隔离的表面；
沉积ALD氮化硅薄膜，所述ALD氮化硅薄膜覆盖所述有源区表面、所述浅沟槽隔离表面、所述栅极结构以及所述栅极侧墙；
在所述ALD氮化硅薄膜上形成光刻胶，进行离子注入光刻工艺，形成离子注入区图案；
进行离子注入工艺，其中，进行离子注入工艺时，不去除沉积的所述ALD氮化硅薄膜以保护图案化的所述光刻胶不出现缺角。
2.根据权利要求1所述的方法，其特征在于，所述ALD氮化硅薄膜的厚度为10至50埃。
3.根据权利要求1所述的方法，其特征在于，沉积所述ALD氮化硅薄膜时的反应温度为300摄氏度至700摄氏度。
4.根据权利要求1所述的方法，其特征在于，所述衬底上制作有PMOS器件和/或NMOS器件。
5.根据权利要求1所述的方法，其特征在于，所述ALD氮化硅薄膜的材料为纯氮化硅或掺杂碳的氮化硅或掺杂硼的氮化硅。
6.根据权利要求1所述的方法，其特征在于，所述方法应用于40nm及40nm以下技术节点。
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