TW202238681A - 半導體裝置的形成方法 - Google Patents
半導體裝置的形成方法 Download PDFInfo
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- TW202238681A TW202238681A TW111101362A TW111101362A TW202238681A TW 202238681 A TW202238681 A TW 202238681A TW 111101362 A TW111101362 A TW 111101362A TW 111101362 A TW111101362 A TW 111101362A TW 202238681 A TW202238681 A TW 202238681A
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Abstract
一種形成半導體裝置的方法,包括;形成第一磊晶層於基板上方,以形成晶圓;沉積介電層於第一磊晶層上方;圖案化介電層以形成開口;透過開口蝕刻第一磊晶層,以形成凹槽;形成第二磊晶層於凹槽中;蝕刻介電層,以露出第一磊晶層的頂表面;及平坦化第一磊晶層的露出的頂表面及第二磊晶層的頂表面。
Description
本揭露是有關於一種半導體裝置的形成方法,且特別是有關於一種具有磊晶層的半導體裝置的形成方法。
半導體裝置用於各式各樣的電子應用中,例如個人電腦、手機、數位相機、與其他電子裝置。半導體裝置的製造一般是透過於半導體基板上方依序沉積絕緣或介電層、導電層、以及半導體層的材料,並利用微影圖案化各種材料層以於半導體裝置上形成電路組件與元件。
半導體工業藉由逐步縮減最小部件尺寸來不斷增加各種電子元件(例如,電晶體、二極體、電阻、電容等)的積體密度,允許將多個元件整合於一給定的面積中。
本發明實施例提供一種半導體裝置的形成方法,包括:形成第一磊晶層於基板上方,以形成晶圓;沉積介電層於第一磊晶層上方;圖案化介電層以形成開口;透過開口蝕刻第一磊晶層,以形成凹槽;形成第二磊晶層於凹槽中;蝕刻介電層,以露出第一磊晶層的頂表面;及平坦化第一磊晶層的露出的頂表面及第二磊晶層的頂表面。
本發明實施例提供一種半導體裝置的形成方法,包括:形成第一摻雜區及第二摻雜區於基板的頂部;成長第一磊晶層於基板上方,其中第一磊晶層直接接觸第一摻雜區及第二摻雜區;沉積硬遮罩層於第一磊晶層上方;蝕刻硬遮罩層的第一部分中的開口,以露出第一磊晶層的第一頂表面;透過開口蝕刻第一磊晶層以形成凹槽,其中凹槽位於第一摻雜區正上方;成長第二磊晶層於凹槽中;移除硬遮罩層的多個剩餘部分以露出第一磊晶層的第二頂表面,其中第二磊晶層的頂表面高於第一磊晶層的露出的第二頂表面;及平坦化第二磊晶層的頂表面及第一磊晶層的露出的第二頂表面。
本發明實施例提供一種半導體裝置的形成方法,包括:形成第一磊晶層於基板上方;形成凹槽於第一磊晶層中;形成第二磊晶層於凹槽中;及平坦化第一磊晶層的頂表面及第二磊晶層的頂表面,其中平坦化第一磊晶層的頂表面及第二磊晶層的頂表面的步驟包括使用化學機械拋光(chemical mechanical polish, CMP)漿料,CMP漿料包括選擇性地降低第一磊晶層的移除速率的聚合物,其中漿料包括具有約0.5至約1.5重量百分比的範圍之濃度的磨料。
以下揭露提供了許多的實施例或範例,用於實施所提供的標的物之不同元件。各元件及其配置的具體範例描述如下,以簡化本發明實施例之說明。當然,這些僅僅是範例,並非用以定義本發明實施例。舉例而言,敘述中若提及第一元件形成在第二元件上方或之上,可能包含第一及第二元件直接接觸的實施例,也可能包含額外的元件形成在第一及第二元件之間,使得它們不直接接觸的實施例。此外,本發明實施例可能在各種範例中重複參考數值以及∕或字母。如此重複是為了簡明及清楚之目的,而非用以表示所討論的不同實施例及∕或配置之間的關係。
再者,本文可能用到與空間相對用詞,例如「在……之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞,是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
各種實施例包括應用於但不限於包括位於基板上方之第一磊晶層的晶圓的方法。晶圓可包括提供對準標記(alignment marks)的溝槽。各種實施例包括在第一磊晶層上方沉積硬遮罩層並且圖案化硬遮罩層以形成開口。透過開口在第一磊晶層中形成凹槽,並且沉積第二磊晶層以填充凹槽。然後移除硬遮罩層,隨後進行化學機械拋光(chemical-mechanical polishing, CMP)製程,以移除第二磊晶層的多餘部分。本文揭露的實施例允許了在CMP製程期間在第一磊晶層及第二磊晶層的頂表面上更平衡及均勻的負載效應(loading effect)。因此,在CMP製程期間,第一磊晶層的拋光速率更接近於第二磊晶層的拋光速率。此外,硬遮罩層在CMP製程期間為潛在的划痕源(scratch source),因此在CMP製程之前將其移除會導致在CMP製程之後第一磊晶層及第二磊晶層頂表面上的表面划痕的數量減少。這些划痕可能會在後續製程中導致不良影響,例如造成在晶圓的外周(outer perimeter)上的鰭片損壞或圖案化失敗。
本文揭露的各種實施例也包括使用CMP漿料,上述CMP漿料具有允許更容易地從對準標記溝槽的底部及從晶圓的表面移除漿料的成分。保持未移除的泥漿(例如,在對準標記溝槽的底部及晶圓上的其他地方)可能具有不良的影響,例如在隨後的圖案化製程期間在晶圓的外周上剝離(peeling)。這些剝離缺陷可由沉積在未移除的漿料殘留物或缺陷上方的膜所形成。通過使用實施例CMP漿料,可減少這種剝離缺陷。本文揭露的實施例也允許了晶圓的頂表面在CMP製程之後具有更均勻的形貌,以及允許晶圓的外周在進一步製程中降低最小幾何部件的尺寸(臨界尺寸(critical dimension, CD))變異。
第1圖係根據一些實施例,以三維視圖繪示出FinFET的示例。FinFET包括位於基板50(例如,半導體基板)上的鰭片52。隔離區56設置在基板50中,並且鰭片52突出於(protrude above)相鄰的隔離區56上方及之間。儘管將隔離區56描述/繪示為與基板50分離,但是如本文所使用的,術語"基板"可僅指半導體基板或包括隔離區的半導體基板。此外,儘管鰭片52被繪示為與基板50為相同的單一連續材料,但是鰭片52及/或基板50可包括單一材料或複數個材料。在這種情況下,鰭片52指的是延伸於相鄰的隔離區56之間的部分。
閘極介電層 92 沿著側壁並位於鰭片52的頂表面上方,並且閘極電極94位於閘極介電層92上方。源極/汲極區82設置在鰭片52相對於閘極介電層92及閘極電極94的兩側。第1圖進一步繪示了在後文的圖中所使用的參考剖面。剖面A-A沿著閘極電極94的縱軸並且在例如垂直於FinFET的源極/汲極區82之間的電流的方向上。剖面B-B垂直於剖面A-A,且沿著鰭片52的縱軸並且在例如FinFET的源極/汲極區82之間的電流流動的方向上。剖面C-C平行於剖面A-A,並且延伸穿過FinFET的源極/汲極區。為清楚起見,隨後的圖參考了這些參考剖面。
本文討論的一些實施例是在使用閘極後製(gate-last)製程形成之FinFETs的情境下討論的。在其他實施例中,可使用閘極先製(gate-first)製程。此外,一些實施例考量了在平面裝置中使用的面向,上述平面裝置例如平面FETs。
第3圖至第11B圖及第12圖至第39B圖係根據一些實施例,繪示製造FinFETs的中間階段的剖面圖。第3圖至第11A圖及第12圖至第19圖繪示出第1圖中所示的參考剖面A-A,但差別在於繪示了複數個鰭片/FinFETs。第20A圖、第21A圖、第22A圖、第23A圖、第24A圖、第25A圖、第28A圖、第29A圖、第30A圖、第31A圖、第32A圖、第33A圖、第34A圖、第35A圖、第36A圖、第37A圖、第38A圖、及第39A圖係沿著第1圖中所示的參考剖面A-A繪示,且第20B圖、第21B圖、第22B圖、第23B圖、第24B圖、第25B圖、第28B圖、第29B圖、第30B圖、第31B圖、第32B圖、第33B圖、第34B圖、第35B圖、第35C圖、第36B圖、第37B圖、第38B圖、及第39B圖係沿著第1圖中所示的類似剖面B-B繪示,但差別在於繪示了複數個鰭片/FinFETs。第26A圖至第27B圖係沿著第1圖中所示的參考剖面C-C繪示,但差別在於繪示了複數個鰭片/FinFETs。
第2圖繪示出形式為塊體半導體晶圓20的基板50的俯視圖。在一些實施例中,基板50可為絕緣體上覆半導體(semiconductor-on-insulator)晶圓。再者,基板50可由矽(silicon, Si)或另一種元素半導體所製成,上述元素半導體例如(i)鍺(germanium, Ge);(ii) 化合物半導體,包括矽鍺 (silicon germanium, SiGe)、碳化矽(silicon carbide, SiC)、砷化鎵 (gallium arsenide, GaAs)、磷化鎵(gallium phosphide, GaP)、磷化銦(indium phosphide, InP)、砷化銦(indium arsenide, InAs)、及/或銻化銦(indium antimonide, InSb); (iii)合金半導體,包括矽鍺(silicon germanium, SiGe)、磷砷化鎵(gallium arsenide phosphide, GaAsP)、砷化鋁銦 (aluminum indium arsenide, AlInAs)、砷化鋁鎵(aluminum gallium arsenide, AlGaAs)、砷化鎵銦(gallium indium arsenide, GaInAs)、磷化鎵銦(gallium indium phosphide, GaInP)、及/或磷砷化鎵銦(gallium indium arsenide phosphide, GaInAsP);或(iv)其組合。出於例示性目的,基板50是在矽(例如,單晶)的情境下討論的。基於本文的揭露,可使用如前文所述的其他材料。這些材料在本揭露的精神及範圍內。
可將晶圓20圖案化以形成對準標記30。對準標記30可包括蝕刻到晶圓20中的溝槽,上述溝槽被圖案化為例如矩形(rectangles)或十字形(crosses)的幾何形狀。對準標記30用於對準晶圓20,使得後續層相對於下方部件形成在正確的位置。對準標記30經歷了與晶圓20的其餘部分所經歷的製程步驟相同。如後文更詳細描述地,這些製程步驟可包括導體及絕緣體的沉積、蝕刻、拋光、研磨等。
第3圖為晶圓20的一部分的剖面圖,繪示出基板 50及第1圖中所示的剖面A-A。介電層210沉積在基板50上。介電層 210可包括介電材料,例如氧化矽等。可根據可接受的技術來沉積或熱成長介電層210。在一些實施例中,介電層210可具有介於約3nm至約15nm之範圍的厚度。舉例而言,如果介電層210具有小於3nm的厚度,則在隨後的佈植步驟(描述於第4圖至第5圖中)期間可能發生對基板50的表面損壞,且如果介電層210的厚度大於15nm,則在隨後的佈植步驟(描述於第4圖至第5圖中)期間佈植摻質的深度可能太淺(shallow)。根據一些實施例,介電層210可保護基板50的頂表面免受污染,防止在隨後進行的離子佈植製程期間對基板50的過度損壞(例如,如下方的第4圖至第5圖中所述),並且可在離子佈植製程期間控制摻質的深度。
第4圖繪示出在介電層210上方沉積光阻層300。在沉積之後,可圖案化光阻層300,使得在介電層210的一部分上方形成開口310。隨後,透過開口310進行離子佈植,以例如在基板50中形成n型區320。在一些實施例中,因為光阻層300可當作佈植遮罩,所以n型區320與開口310實質上對齊。在一些實施例中,n型摻質可包括砷(arsenic, As)、銻(antimony, Sb)、磷(phosphorous, P)等。在一些實施例中,n型區320中的n型摻質濃度在5x10
16原子/cm
3至約1x10
19原子/cm
3的範圍。n型區320可具有約100nm至約500nm的深度。在形成n型區320之後,可移除光阻層300。
第5圖繪示出p型區400形成於基板50中並鄰近於n型區320。首先,在介電層210上方沉積並圖案化光阻層360,定義了穿過光阻層360的開口350。在一些實施例中,可通過離子佈植製程使用p型摻質來創建p型區,上述p型摻質例如硼(boron, B)等。在一些實施例中,p型區400可具有在約5x10
16原子/cm
3至約1x10
19原子/cm
3之範圍的摻質濃度。
在形成n型區320及p型區400之後,可使用濕清潔製程、灰化製程等來移除任何剩餘的光阻層。在一些實施例中,進行退火步驟以電性活化(electrically activate)摻質(例如,將摻質從間隙位置(interstitial sites)移動到矽晶格位置)並修復在離子佈植步驟期間發生的任何矽晶體損壞。舉例而言,晶體損壞修復可在約500°C下進行並且摻質活化可在約950°C下進行。退火步驟可在退火爐(annealing furnace)中或快速熱退火(rapid thermal anneal, RTA)腔室中進行。根據一些實施例,可在摻質活化退火之後移除介電層210。
在第6圖中,磊晶半導體層410形成在基板50上。半導體層410可包括半導體材料,例如矽等。在一些實施例中,半導體層410可具有約30nm至約100nm之範圍的厚度。可使用例如化學氣相沉積(chemical vapor deposition, CVD)等製程來沉積半導體層410。用於形成半導體層410的來源氣體(source gases)可包括矽烷(silane, SiH
4)、四氯化矽(silicon tetrachloride, SiCl
4)、三氯矽烷(trichlorosilane, TCS)、二氯矽烷(dichlorosilane, SiH
2Cl
2或DSC)等。氫氣(hydrogen, H
2)可用作還原上述來源氣體的反應氣體。半導體層410的沉積期間的沉積溫度取決於所使用的氣體,上述沉積溫度可在約700℃至約1250℃的範圍,但在其他實施例中可使用其他溫度。舉例而言,相較於具有更多氯原子的來源氣體,例如SiCl
4或TCS,具有更少氯原子的來源氣體(例如,DSC)可能需要更低的形成溫度。
根據一些實施例,硬遮罩層420可形成在半導體層410之上。硬遮罩層420可具有10nm至約50nm之範圍的厚度T1。在一些實施例中,硬遮罩層420可為例如SiO
2等的氧化物層。替換地,硬遮罩層420可為氮化物層,例如Si
3N
4、氮氧化物(oxynitride)層等。可根據可接受的技術來沉積或熱成長硬遮罩層420。
第7圖繪示了在半導體層410中形成凹槽500。在一些實施例中,凹槽500可與n型區320對齊。例如通過光學微影可實現凹槽500與n型區320的對齊。舉例而言,可在硬遮罩層420上沉積光阻,然後對其進行圖案化以形成開口。可使用曝光、顯影、及/或清潔製程的組合來將光阻圖案化。然後將光阻的圖案轉移至硬遮罩層420。然後將硬遮罩層420用作遮罩來定義凹槽500。可使用一種或多種乾式及/或濕式蝕刻製程來實現轉移光阻的圖案。舉例而言,可使用一種或多種電漿蝕刻製程來將光阻的圖案轉移至硬遮罩層420及半導體層410,以定義凹槽500。一種或多種電漿蝕刻製程可輕微地蝕刻硬遮罩層420,這可加寬(widen)硬遮罩層420中的開口。可將半導體層410中凹槽500的圖案化定時(timed),使得半導體層410的半導體區510並未被移除。區域510可設置在n型區320之上。根據一些實施例,位於n型區320之上的剩餘半導體區510的厚度可在5nm至約10nm的範圍。在一些實施例中,蝕刻製程可使用不同的蝕刻化學物質來蝕刻硬遮罩層420及半導體層410。
在一些實施例中,凹槽500具有寬度Wl及高度Hl。寬度W1可在100nm至約500nm的範圍並且可實質上等於(例如,在製造公差內)n型區320的寬度。在一些實施例中,凹槽500可具有高度H1,這等於半導體層410的厚度與位於凹槽500底部的半導體區510的厚度之間的差值。
第8圖繪示出在凹槽500的露出表面上形成晶種層460。根據一些實施例,晶種層460不能成長在硬遮罩層420上;舉例而言,晶種層460不能在SiO
2或Si
3N
4上成長。根據一些實施例,晶種層460可為具有約3nm至約10nm之範圍的厚度的Si層、Si:C層、SiGe層、或其組合。舉例而言,晶種層460可為Si/Si:C/SiGe、Si/SiGe、或Si:C/SiGe。根據一些實施例,Si:C中的碳摻質的原子百分比(at. %)可為約0.01 at. % 至約 2 at.%。在一些實施例中,晶種層460的厚度不足以填充凹槽500。因此,晶種層460覆蓋凹槽500的露出表面並且不能填充凹槽500。可通過CVD製程等來沉積晶種層460。舉例而言,可在H
2、N
2等存在下使用SiH
4、DCS、或其組合來形成包含矽的晶種層460。下列的組合可用於形成包括矽鍺(silicon germanium)的晶種層460:(i)SiH
4、二矽烷(disilane, Si
2H
6)、鍺烷(germane, GeH
4)、或鹽酸(hydrochloric acid, HCl),以及(ii)H
2、N
2、He、Ar等。
第9圖繪示了在晶種層460上形成磊晶層700,以填充凹槽500。可用於成長磊晶層700的前驅物氣體可包括下列的組合:(i)SiH
4、Si
2H
6、SiH
2Cl
2、GeH
4、或HCl,以及(ii) H
2、N
2、Ar 等。在一些實施例中,以原子百分比(at.%)表示的鍺濃度在磊晶層700的整個厚度上為定值並且可在約10at. %至約 50at. %的範圍。在一些實施例中,磊晶層700可包括第一子層及第二子層,上述第一子層具有高達約0至10at. %之Ge濃度,上述第二子層在磊晶層700的整個厚度範圍具有固定的Ge濃度,範圍約10at. %至約 50at. %。第一子層的厚度可在約2nm至約10nm的範圍。
磊晶層700可能不會在硬遮罩層420上成長。舉例而言,包括矽鍺的磊晶層700通常不在SiO
2或Si
3N
4上成長。根據一些實施例,在成長磊晶層700之後,凹槽500的側壁可相對於凹槽500的底表面實質上垂直;舉例而言,凹槽500的底表面與凹槽500的側壁之間的夾角可介於約90°至約100°之間。由於磊晶層700的材料(例如,矽鍺)及半導體層410的材料(例如,矽)之間的晶格不匹配(lattice mismatch),磊晶層700可被應變及/或將應變施加到下方的半導體層410。 在隨後的製程步驟中,磊晶層700及半導體層410的部分可被圖案化為PFET的通道區。
第10圖繪示出硬遮罩層420的移除。在一些實施例中,通過使用例如稀氫氟(dilute hydrofluoric, dHF)酸進行蝕刻製程610來移除硬遮罩層420。在其他實施例中,可使用不同的蝕刻劑。dHF酸(或其他蝕刻劑)允許硬遮罩層420對半導體層410及磊晶層700的材料選擇性地蝕刻。因此,可移除硬遮罩層420而並未顯著地侵蝕(attacking)下方的半導體層410或磊晶層700。
在第11A圖及第11B圖中,進行CMP製程614以將磊晶層700及半導體層410平坦化。在CMP操作期間,可移除磊晶層700及半導體層410的一部分。在CMP製程614之後,如第11A圖所示,半導體層410及磊晶層700的頂表面為齊平的。因為在進行CMP製程614之前移除了硬遮罩層420(先前在第10圖中示出),所以在CMP製程614期間磊晶層700及半導體層410的頂表面上更平衡及均勻的負載效應是可能的。這允許磊晶層700的拋光速率在CMP製程614期間更接近於半導體層410的拋光速率。此外,硬遮罩層420在CMP製程614期間是潛在的划痕源,因此在CMP製程614之前將硬遮罩層420移除(先前在第10圖中示出)導致在CMP製程614之後磊晶層700及半導體層410的頂表面上的表面划痕的數量減少。舉例而言,在CMP製程614之後,晶圓20的表面可具有 4x10
1或更少的表面划痕。
第11B圖繪示出晶圓20的剖面圖。在第11B圖中,通過進行CMP製程614將磊晶層700及半導體層410平坦化。CMP製程614可使用反應性化學CMP漿料中的研磨材料結合拋光墊來拋光晶圓20。晶圓20被固定(positioned),使得磊晶層700及半導體層410的待拋光表面面向(例如,向下)朝向拋光墊的方向,上述拋光墊位於晶圓20下方。施加向下的力或壓力以促使晶圓20與拋光墊接觸。在化學機械平坦化製程期間,晶圓20在拋光墊上旋轉,因此賦予(imparting)機械研磨作用以達到晶圓 20之接觸表面的平坦化或拋光。CMP漿料可具有允許更容易地從對準標記30的溝槽底部及從晶圓20的表面移除漿料的成分。保持未移除的漿料(例如,在對準標記30的溝槽的底部及晶圓20上的其他地方)可能具有不良的影響,例如在隨後的圖案化製程期間在晶圓20的外周上剝離。這些剝離缺陷可由沉積在未移除的漿料殘留物或缺陷上方的膜所形成。這可能是由於下方的漿料殘留物或缺陷導致沉積在漿料殘留物或缺陷上的薄膜部分不穩定。
CMP漿料可包括用於在CMP製程614期間調節CMP拋光速率及調節負載效應的各種元素。CMP漿料可包括在約0.5重量%(wt%)至約1.5重量%之範圍的濃度的磨料(abrasive),其中磨料可具有約25nm至約45nm之範圍的平均磨料尺寸。較高的磨料濃度可能會導致較高的CMP拋光速率。CMP漿料可具有在0至9之範圍的pH並且可包含無機pH調節劑(pH adjustor)。pH值可用於調節每一個上磊晶層700及半導體層410上的拋光速率以獲得實質上平坦的表面。CMP漿料也可包含聚合物Si抑製劑,例如聚乙二醇(polyethylene glycol, PEG)等。聚合物Si抑製劑的濃度可在約10%至約40%的範圍。在CMP製程期間,相較於其他元素的移除速率,Si抑制劑可有助於選擇性地降低Si移除速率。此外,CMP漿料也可包含聚合物SiGe抑製劑,上述聚合物SiGe抑製劑可包括以約10%至約40%之範圍的濃度存在的聚乙二醇(polyethylene glycol, PEG)等。CMP漿料可包括增強劑(enhancer),在平坦化期間增加材料移除速率。增強劑可包括以約5%至約35%之範圍的濃度存在的乳酸(lactic acid)、乙酸(acetic acid)、甲酸(formic acid)、檸檬酸(citric acid)、草酸(oxalic acid)等。
通過在CMP製程614期間使用具有上述成分的CMP漿料,在CMP製程614之後從對準標記30的溝槽底部及晶圓20的表面移除漿料變得更容易。這減少了在後續圖案化製程期間所形成的剝離缺陷的數量。這是因為保持未移除的漿料(例如,在對準標記30的溝槽的底部及晶圓20上的其他地方)可能在隨後的圖案化製程期間具有不良的影響,例如在晶圓20的外周上剝離。這些剝離缺陷可由沉積在未移除的漿料殘留物或缺陷上方的膜所形成。這可能是由於下方的漿料殘留物或缺陷導致沉積在漿料殘留物或缺陷上的薄膜部分不穩定的結果。
CMP製程614移除材料並且傾向於使不規則形貌變平(even out),使得晶圓20的拋光表面平坦或實質上平坦(例如,在製造公差內)。舉例而言,在CMP製程614之後,晶圓20外周處的拋光頂表面在實質上接近晶圓20中心處的拋光頂表面的水平。在CMP製程614完成之後,晶圓20的拋光表面的最高點及晶圓20的拋光表面的最低點之間的差異可高達12nm或更高。此外,CMP製程614允許晶圓20的外周在進行進一步的製程步驟之後降低最小幾何部件的尺寸(臨界尺寸CD)變異。再者,通過在CMP製程614之前移除硬遮罩層420(先前在第10圖中示出)結合在CMP製程614期間使用CMP漿料,可減少CMP製程614對拋光時間的敏感度。
在CMP製程614之後,進行濕式清潔,以移除晶圓20上任何剩餘的漿料顆粒及殘留物。在濕式清潔之後,總共多達8xl0
2漿料顆粒可在對準標記30之溝槽的底部保持未被移除。
第11C圖繪示了在CMP製程614完成之後所測量的數據軌跡140及150。軌跡140繪示出磊晶層700的拋光頂表面及半導體層410的拋光頂表面沿著晶圓20的不同半徑位置之間的高度差值(右側y軸刻度)。半徑位置從x軸上的“0”mm至“150”mm,上述“0”mm對應於晶圓20的中心,上述“150”mm對應於晶圓20的邊緣。在CMP製程614完成之後,進行多個後續製程步驟。軌跡150繪示出在對晶圓20進行多個後續製程步驟之後磊晶層700上的最小幾何部件的尺寸(臨界尺寸CD)與半導體層410上的最小幾何部件的尺寸之間沿著晶圓20的不同半徑位置之間的差值(左側的y軸刻度)。軌跡140及150顯示作為CMP製程614的結果,晶圓20的拋光頂表面從晶圓20 的中心到晶圓20的外周具有更均勻的形貌。此外,晶圓20的外周在進一步製程時降低最小幾何部件的尺寸(臨界尺寸CD)變異。因此,通過使用實施例CMP漿料提高了晶圓20中的臨界尺寸(critical dimension, CD)均勻性。
第12圖繪示出在CMP製程614完成之後晶圓20的一部分的剖面圖。在CMP製程614之後,半導體層410及磊晶層700的拋光的頂表面為齊平的。磊晶層700的拋光的頂表面在n型區320的頂表面之上具有高度H2。高度H2可在30nm至約80nm的範圍。半導體層410的拋光的頂表面可以相同的高度H2位於p型區400的頂表面之上。舉例而言,大於80nm的高度H2可能導致更多的誘導差排缺陷(induced dislocation defects)在磊晶層700中,且小於30nm的高度H2可能導致後續形成的FinFETs(如第38A圖至第39B圖中所述)具有不足的通道體積,這將對裝置性能產生負面影響。
第13圖繪示出在磊晶層700及半導體層410的平坦化的表面上方沉積半導體層810。半導體層810可包括半導體材料,例如矽等。在一些實施例中,半導體層810的厚度範圍可從約1nm至約10nm,並且可用類於成長半導體層410的類似方法來成長半導體層810。隨後,可沉積介電層820及介電層830在半導體層810上方。介電層820可包括介電材料,例如氧化矽等。可根據可接受的技術來沉積或熱成長介電層820。介電層830可包括可通過CVD製程等來沉積的介電材料,例如氮化矽等。半導體層810、介電層820、及介電層830可在後續蝕刻製程期間保護磊晶層700及半導體層410。
第14圖係根據一些實施例,繪示了被蝕刻以形成鰭片52之堆疊800的部分(如第13圖所示),其可包括由n型區320所製成的底部、由半導體區510所製成的中間部、及由晶種層460及磊晶層700所製成的頂部。在一些實施例中,鰭片52也可形成為包括由p型區400所製成的底部部分及由半導體層410所製成的頂部。第14圖也繪示出區域50N及區域50P。區域50N可用於形成n型裝置,例如NMOS電晶體,例如n型FinFETs。區域50P可用於形成p型裝置,例如PMOS電晶體,例如p型FinFETs。區域50N可與區域50P實體分離(如分隔器51所示),並且可設置任何數量的裝置部件(例如,其他主動裝置、摻雜區、隔離結構等)於區域50N及區域50P之間。
鰭片52可通過任何合適的方法來圖案化。例如,鰭片52可使用一種或多種光學微影製程被圖案化,包括雙重圖案化或多重圖案化製程。通常,雙重圖案化或多重圖案化製程結合了光學微影及自對準製程,從而允許創建例如節距小於使用單一直接光學微影製程所獲得的節距的圖案。舉例而言,犧牲層形成在介電層830上方並使用光學微影製程來圖案化。使用自對準製程在圖案化的犧牲層旁邊(alongside)形成間隔物。然後移除犧牲層,然後可使用剩餘的間隔物來圖案化鰭片。
根據一些實施例,鰭片結構900可包括n型區320的底部、半導體區510的中間部、以及晶種層460及磊晶層700的頂部。鰭片結構910可包括由p型區400所製成的底部及由半導體層410所製成的頂部。位於鰭片結構900及鰭片結構910中之鰭片52的數量為例示性的而非限制性的。因此,取決於鰭片節距及每個鰭片的期望寬度,更少或額外的鰭片是可能的。
第15圖繪示出在鰭片結構900及鰭片結構910上方沉積介電襯層920,以覆蓋鰭片結構900及鰭片結構910的側壁表面、以及p型區400及n型區320的水平表面。介電襯層920可例如為氮化矽等。可通過CVD製程等來形成介電襯層。在一些實施例中,介電襯層920可在後續製程期間為鰭片結構900及鰭片結構910提供結構支撐。
第16圖繪示出形成在鰭片結構900及鰭片結構910上方以填充鰭片52之間的空間的絕緣材料54。絕緣材料54可為氧化物,例如氧化矽、氮化物等、或其組合,並且可通過高密度電漿化學氣相沉積(high density plasma chemical vapor deposition, HDP-CVD)、流動式CVD(flowable CVD, FCVD)(例如, CVD基(CVD-based)材料在遠端電漿系統中的沉積及後固化(post curing),以使其轉化為另一種材料,例如氧化物)等、或其組合。可使用通過任何可接受的製程所形成的其他絕緣材料。在所繪示的實施例中,絕緣材料54是通過FCVD製程所形成的氧化矽。一旦形成絕緣材料,就可進行退火製程。在一實施例中,形成絕緣材料54,使得多餘的絕緣材料54覆蓋鰭片52、半導體層810、介電層820、及介電層830。雖然絕緣材料54被繪示為單層,但是一些實施例可利用複數個層。舉例而言,在一些實施例中,可首先沿著p型區400及n型區320以及鰭片52的表面形成襯層(未繪示)。之後,例如前文討論的那些填充材料可形成在襯層上方。
第17圖繪示出用於移除位於鰭片結構900及鰭片結構910上方之絕緣材料54的一部分的CMP製程。此外,也可移除半導體層810、介電層820、及介電層830。在一些實施例中,CMP製程可在介電襯層920上停止。此外,也可將介電襯層920凹蝕至絕緣材料54的水平。
第18繪示了在n型區320及p型區400的水平處凹蝕絕緣材料54的後續回蝕刻製程。凹蝕絕緣材料54以形成淺溝槽隔離(Shallow Trench Isolation, STI)區56。將絕緣材料54凹蝕,使得位於區域50N及區域50P中之鰭片52的上部從相鄰的STI區56之間突出。再者,STI區56的頂表面可具有如圖所示的平坦表面、凸表面、凹表面(例如碟狀)、或其組合。可藉由適當的蝕刻將STI區56的頂表面形成為平坦的、凸的、及/或凹的。可使用可接受的蝕刻製程來將STI區56凹蝕,例如對絕緣材料54具有選擇性的蝕刻製程(例如,相較於蝕刻鰭片52之材料的速率,以更快的速率蝕刻絕緣材料54的材料)。舉例而言,可通過使用例如稀氫氟(dilute hydrofluoric, dHF)酸的合適蝕刻製程來移除化學氧化物。
在替代實施例中,可在p型區400上方的區域50N中製造n型鰭式場效應電晶體 (n-type Fin Field-Effect Transistor, NFET) 中的應變通道(strained channel)。舉例而言,這可通過在鰭片結構910中形成鰭片52來實現,上述鰭片結構910包括成長在矽晶種層上的碳摻雜矽(Si:C)的磊晶層。
再者,在第18圖中,可在鰭片52中形成適當的井(未繪示)。在一些實施例中,可在區域50N中形成P井,並且可在區域50P中形成N井。在一些實施例中,在區域50N及區域50P中皆形成P井或N井。
在具有不同井類型的實施例中,區域50N及區域50P的不同佈植步驟可使用光阻或其他遮罩(未繪示)來實現。例如,可在區域50N中的鰭片52及STI區域56上方形成光阻。圖案化光阻以暴露基板50的區域50P,例如PMOS區。可藉由使用旋塗技術來形成光阻,並且可使用可接受的光學微影技術來將光阻圖案化。一旦將光阻圖案化,在區域50P中進行n型雜質(impurity)佈植,並且光阻可用作遮罩以實質上防止將n型雜質佈植至區域50N中,例如NMOS區。n型雜質可為佈植到該區域中的磷、砷等,其濃度等於或小於10
18cm
-3,例如在約10
17cm
-3至約10
18cm
-3之間。在佈植之後,例如藉由可接受的灰化製程來移除光阻。
在佈植區域50P之後,在區域50P中的鰭52及STI 區56上方形成光阻。將光阻圖案化以露出基板50的區域50N,例如NMOS區。光阻可通過使用旋塗技術形成並且可使用可接受的光學微影技術進行圖案化。一旦將光阻圖案化,可在區域50N中進行p型雜質佈植,並且光阻可用作遮罩以實質上防止將p型雜質佈植至區域50P中,例如PMOS區。p型雜質可為硼、BF
2等,將p型雜質佈植於區域中的濃度等於或小於10
18cm
-3,例如在約10
17cm
-3至約10
18cm
-3之間。在佈植之後,可例如藉由可接受的灰化製程來移除光阻。
在區域50N及區域50P的佈植之後,可進行退火以活化佈植的p型及/或n型雜質。在一些實施例中,可在成長期間將磊晶鰭片的成長材料原位摻雜,儘管原位摻雜及佈植摻雜可一起使用,但原位摻雜可避免佈植。
在第19圖中,在鰭片52上形成虛設介電層60。虛設介電層60可為例如氧化矽、氮化矽、其組合等,並且可根據可接受的技術沉積或熱成長(thermally grown)虛設介電層60。在虛設介電層60上方形成虛設閘極層62,在虛設閘極層62上方形成遮罩層64。虛設閘極層62可沉積在虛設介電層60上方,然後例如藉由CMP將其平坦化。遮罩層64可沉積在虛設閘極層62上方。虛設閘極層62可為導電材料,並且可選自包括下列材料的群組:多晶矽(polycrystalline-silicon, polysilicon)、多晶矽鍺(polycrystalline silicon-germanium, poly- SiGe)、金屬氮化物、金屬矽化物、金屬氧化物、及金屬。在一實施例中,非晶矽被沉積及再結晶以產生多晶矽。可藉由物理氣相沉積(physical vapor deposition, PVD)、CVD、濺鍍沉積、或用於沉積導電材料的其他已知技術來沉積虛設閘極層62。虛設閘極層62可由對隔離區的蝕刻具有高蝕刻選擇性的其他材料所製成。遮罩層64可包括例如SiN、SiON等。在此示例中,橫跨(across)區域50N及區域50P形成單一虛設閘極層62及單一遮罩層64。在一些實施例中,可在區域50N及區域50P中形成分開的虛設閘極層,並且可在區域50N及區域50P中形成分開的遮罩層。應注意的是,僅出於說明的目的,繪示虛設介電層60僅覆蓋鰭片52。在一些實施例中,可沉積虛設介電層60,使得虛設介電層60覆蓋STI區56,上述虛設介電層60延伸於虛設閘極層62及STI區56之間。
第20A圖至第39B圖繪示出製造實施例裝置中的各種額外步驟。第20A圖及第20B圖繪示了區域50P中的部件,並且第21A圖及第21B圖繪示了區域50N中的部件。在第20A圖至第21B圖中,可使用可接受的光學微影及蝕刻技術來圖案化遮罩層64以形成遮罩74。然後可將遮罩74的圖案轉移至虛設閘極層62。在一些實施例中(未繪示),遮罩74的圖案也可通過可接受的蝕刻技術轉移至虛設介電層60,以形成虛設閘極72。虛設閘極72覆蓋鰭片52的相應通道區58。遮罩74的圖案可用於將每個虛設閘極72與鄰近的虛設閘極實體地間隔開。虛設閘極72也可具有長度方向實質上垂直於相應磊晶鰭片52的長度方向。
此外,在第20A圖至第21B圖中,可在虛設閘極 72、遮罩74、及/或鰭片52的露出表面上形成閘極密封(seal)間隔物 80。熱氧化或沉積然後進行非等向性蝕刻可形成閘極密封間隔物 80。
在形成閘極密封間隔物80之後,可進行用於輕摻雜源極/汲極(lightly doped source/drain, LDD)區(未明確繪示) 的佈植。在具有不同裝置類型的實施例中,類似於前文在第18圖中討論的佈植,可在區域50N上方形成例如光阻的遮罩,同時露出區域50P且適當類型(例如,n 型或p型)雜質可佈植到區域50P中露出的鰭片52中。然後可移除遮罩。隨後,可在露出區域50N的同時在區域50P上方形成例如光阻的遮罩,並且可將適當類型的雜質佈植到區域50N中的露出的鰭片52中。然後可移除遮罩。n型雜質可為前文討論的任何n型雜質,並且p型雜質可為前文討論的任何p型雜質。 輕摻雜的源極/汲極區可具有約10
15cm
-3至約10
16cm
-3的雜質濃度。可使用退火來活化佈植的雜質。
第22A圖及第22B圖繪示了區域50P中的部件,並且第23A圖及第23B圖繪示了區域50N中的部件。在第22A圖至第23B圖中,沿著虛設閘極72及遮罩74的側壁在閘極密封間隔物80上形成閘極間隔物86。可通過共形地沉積絕緣材料並隨後非等向性地蝕刻絕緣材料來形成閘極間隔物86。閘極間隔物86的絕緣材料可為氮化矽(silicon nitride)、SiCN、其組合等。
第24A圖及第24B圖繪示了區域50P中的部件,並且第25A圖及第25B圖繪示了區域50N中的部件。在第24A圖至第25B圖中,磊晶源極/汲極區82形成在鰭片52中,以在相應的通道區58中施加應力,因此改善性能。磊晶源極/汲極區82形成在鰭片52中,使得每個虛設閘極72設置在相應的相鄰磊晶源極/汲極區82對之間。在一些實施例中,磊晶源極/汲極區82可延伸進鰭片52中。在一些實施例中,閘極間隔物86用於以適當的橫向距離間隔開磊晶源極/汲極區82與虛設閘極72,使得磊晶源極/汲極區82不會與所得之FinFETs隨後形成的閘極短路(short out)。
可通過遮蔽(masking)區域50P(例如PMOS區)並蝕刻區域50N中鰭片52的源極/汲極區以在鰭片52中形成凹槽來形成區域50N(例如NMOS區)中的磊晶源極/汲極區82。然後,在凹槽中磊晶成長區域50N中的磊晶源極/汲極區82。磊晶源極/汲極區82可包括任何可接受的材料,例如適用於n型FinFETs的材料。例如,如果鰭片52為矽,則區域50N中的磊晶源極/汲極區82可包括在通道區58中施加拉伸應變(tensile strain)的材料,例如矽、SiC、SiCP、SiP等。區域50N中的磊晶源極/汲極區82可具有從鰭片52的相應表面凸起的表面並且可具有晶面(facets)。
可通過遮蔽區域50N(例如NMOS區)並蝕刻區域50P中鰭片52的源極/汲極區以在鰭片52中形成凹槽來形成區域50P(例如PMOS區)中的磊晶源極/汲極區82。然後,在凹槽中磊晶成長區域50P中的磊晶源極/汲極區82。磊晶源極/汲極區82可包括任何可接受的材料,例如適用於p型FinFETs的材料。例如,區域50P中的磊晶源極/汲極區82可包括例如SiGe、SiB等材料。區域50P中的磊晶源極/汲極區82也可具有從鰭片52的相應表面凸起的表面並且可具有晶面。
可用與前文討論用於形成輕摻雜源極/汲極區相似的製程,用摻質來佈植磊晶源極/汲極區82及/或鰭片52,以形成磊晶源極/汲極區,隨後進行退火。源極/汲極區可具有介於約10
19cm
-3至約10
21cm
-3之間的雜質濃度。用於源極/汲極區的n型及/或p型雜質可為前文討論的任何雜質。在一些實施例中,可在成長期間原位摻雜磊晶源極/汲極區82。
作為用於在區域50P及區域50N中形成磊晶源極/汲極區82的磊晶製程的結果,磊晶源極/汲極區的上表面具有橫向擴展向外超過鰭片52側壁的晶面。在一些實施例中,這些晶面導致相同finFET的鄰近磊晶源極/汲極區82如第26A圖及第27A圖所示地合併。在其他實施例中,如第26B圖及第27B圖所示,在完成磊晶製程之後,鄰近的磊晶源極/汲極區82保持分離。
第28A圖及第28B圖繪示了區域50P中的部件,並且第29A圖及第29B圖繪示了區域50N中的部件。在第28A圖至第29B圖中,第一ILD 88沉積在第26A圖至第27B圖所示的結構上方。第一ILD 88可由介電材料所形成,並且可通過任何合適的方法沉積,例如CVD、電漿增強化學氣相沉積(plasma-enhanced CVD, PECVD)、或FCVD。介電材料可包括磷矽酸鹽玻璃(Phospho-Silicate Glass, PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass, BSG)、硼磷矽酸鹽玻璃(Boro-Doped Phospho-Silicate Glass, BPSG)、未摻雜的矽酸鹽玻璃(Undoped Silicate Glass, USG)等。可藉由使用任何可接受的製程形成其他絕緣材料。在一些實施例中,接觸蝕刻停止層(contact etch stop layer, CESL)87設置在第一ILD 88及磊晶源極/汲極區82、硬遮罩74、及閘極間隔物86之間。CESL 87可包括介電材料,例如如氮化矽、氧化矽、氮氧化矽等,具有與上方的第一ILD 88的材料不同的蝕刻速率。
第30A圖及第30B圖繪示了區域50P中的部件,並且第31A圖及第31B圖繪示了區域50N中的部件。在第30A圖至第31B圖中,可進行例如CMP的平坦化製程,以將第一ILD 88的頂表面與虛設閘極72的頂表面齊平(level)。平坦化製程也可移除位於虛設閘極72上的遮罩74、以及沿著遮罩74側壁之閘極密封間隔物80及閘極間隔物86的部分。在平坦化製程之後,虛設閘極72、閘極密封間隔物80、閘極間隔物86、及第一ILD 88的頂表面為齊平的。因此,虛設閘極72的頂表面藉由第一ILD 88露出。
第32A圖及第32B圖繪示了區域50P中的部件,並且第33A圖及第33B圖繪示了區域50N中的部件。在第32A圖至第33B圖中,在(多個)蝕刻步驟中移除虛設閘極72,因此形成凹槽90。也可移除凹槽90中虛設介電層60的部分。在一些實施例中,僅將虛設閘極72移除,且將虛設介電層60保留並被凹槽90所露出。在一些實施例中,從晶粒的第一區(例如,核心邏輯(core logic)區)中的凹槽90移除虛設介電層60,並保留在晶粒的第二區(例如,輸入/輸出區)中的凹槽90中。在一些實施例中,藉由非等向性乾式蝕刻製程來移除虛設閘極72。例如,蝕刻製程可包括使用(多種)反應氣體的乾式蝕刻製程,其選擇性地蝕刻虛設閘極72而不蝕刻第一ILD 88或閘極間隔物86。每個凹槽90露出相應鰭片52的通道區58。每個通道區58設置在相鄰的磊晶源極/汲極區82對之間。在移除製程中,當蝕刻虛設閘極72時,虛設介電層60可用作蝕刻停止層。然後可在移除虛設閘極72之後可選地移除虛設介電層60。
第34A圖及第34B圖繪示了區域50P中的部件,並且第35A圖及第35B圖繪示了區域50N中的部件。在第34A圖至第35B圖中,形成閘極介電層92及閘極電極94用於替代閘極。第35C圖繪示了第34B圖及第35B圖的區域89的詳細視圖。閘極介電層92共形地沉積在凹槽90中,例如在鰭片52的頂表面及側壁上以及閘極密封間隔物80/閘極間隔物86的側壁上。閘極介電層92也可形成在第一ILD 88的頂表面上。根據一些實施例,閘極介電層92包括氧化矽、氮化矽、或其多層。在一些實施例中,閘極介電層92為高k介電材料,並且在這些實施例中,閘極介電層92可具有大於約7.0的k值,並且可包括金屬氧化物或下列材料的矽酸鹽(silicate):Hf、Al、 Zr、La、Mg、Ba、Ti、Pb、及其組合。閘極介電層92的形成方法可包括分子束沉積(Molecular-Beam Deposition, MBD)、ALD、PECVD等。在部分的虛設閘極介電質60保留在凹槽90中的實施例中,閘極介電質層92包括虛設閘極介電質60的材料(例如,SiO)。
閘極電極94分別沉積在閘極介電層92上方,並填充凹槽90的剩餘部分。閘極電極94可為例如下列含金屬材料:TiN、TiO、TaN、TaC、Co、Ru、Al、W、其組合、或其多層。舉例而言,雖然第34B圖及第35B圖中繪示出單層閘極電極94,但是如第35C圖所示閘極電極94可包括任意數量的襯層94A、任意數量的功函數調諧層94B、及填充材料94C。在填充閘極電極94之後,可進行例如CMP的平坦化製程,以移除閘極介電層92的多餘部分及閘極電極94的材料,這些多餘部分位於ILD88的頂表面上方。閘極電極94及閘極介電層92的材料的剩餘部分因此形成所得之FinFETs的替代閘極。閘極電極94及閘極介電層92可統稱為“閘極堆疊”。閘極及閘極堆疊可沿著鰭片52的通道區58的側壁延伸。
區域50N及區域50P中的閘極介電層92的形成可同時發生,使得每個區域中的閘極介電層92是由相同的材料所形成,並且閘極電極94的形成可同時發生,使得每個區域中的閘極電極94是由相同的材料所形成。在一些實施例中,可藉由不同的製程來形成每個區域中的閘極介電層92,使得閘極介質層92可為不同的材料,及/或可藉由不同的製程來形成每個區域中的閘極電極94,使得閘極電極94可為不同的材料。當使用不同的製程時,可使用各種遮蔽步驟來遮蔽及露出適當的區域。
第36A圖及第36B圖繪示了區域50P中的部件,並且第37A圖及第37B圖繪示了區域50N中的部件。在第36A圖至第37B圖中,第二ILD 108沉積在第一ILD 88上方。在一實施例中,第二ILD 108是藉由流動式CVD方法形成的流動式膜(flowable film)。在一些實施例中,第二ILD 108是由例如PSG、BSG、BPSG、USG等的介電材料所形成,並且可通過例如CVD及PECVD的任何合適的方法來沉積。
第38A圖及第38B圖繪示了區域50P中的部件,並且第39A圖及第39B圖繪示了區域50N中的部件。在第38A圖至第39B圖中,根據一些實施例,穿過第二ILD 108及第一ILD 88形成閘極接觸件110及源極/汲極接觸件112。源極/汲極接觸件112的開口穿過第一ILD 88及第二ILD 108形成,且閘極接觸件110的開口穿過第二ILD 108形成。可使用可接受的光學微影及蝕刻技術來形成開口。襯層及導電材料形成在開口中,上述襯層例如擴散阻障層、黏著層等。襯層可包括鈦、氮化鈦、鉭、氮化鉭等。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、鎳等。可進行例如CMP的平坦化製程,以從ILD 108的表面移除多餘的材料。剩餘的襯層及導電材料形成開口中的源極/汲極接觸件112及閘極接觸件110。可進行退火製程以在磊晶源極/汲極區82及源極/汲極接觸件112之間的界面處形成矽化物(silicide)。源極/汲極接觸件112實體及電性耦合至磊晶源極/汲極區82,並且閘極接觸件110實體及電性耦合至閘極電極94。源極/汲極接觸件112及閘極接觸件110可在不同的製程中形成,或者可在相同的製程中形成。儘管將源極/汲極接觸件112及閘極接觸件110繪示為形成在相同的剖面中,但是應理解的是,每一個源極/汲極接觸件112及閘極接觸件110中可形成在不同的剖面中,這可避免接觸件的短路。
本揭露的實施例可達到多個優點。在對晶圓的第一磊晶層及第二磊晶層進行CMP製程之前移除硬遮罩層,允許了在CMP製程期間在第一磊晶層及第二磊晶層的頂表面上更平衡及均勻的負載效應,並且允許了在CMP製程期間使第一磊晶層的拋光速率更接近於第二磊晶層的拋光速率。硬遮罩層在CMP製程期間是潛在的划痕源,因此在CMP製程之前將其移除會導致在CMP製程之後第一磊晶層及第二磊晶層之頂表面上的表面划痕的數量減少。此外,本文揭露的實施例允許更容易地從對準標記溝槽的底部及從晶圓的表面移除在CMP製程期間所使用的CMP漿料。這將允許在隨後的圖案化製程期間減少隨後沉積在晶圓外周上的膜的剝離。在本文揭露的實施例也允許了晶圓的頂表面在CMP製程之後具有更均勻的形貌,以及允許了在進一步製程中晶圓的外周降低最小幾何部件的尺寸(臨界尺寸 CD)變異。在CMP製程之後,晶圓外周之拋光的頂表面的水平面實質上接近晶圓中心處之拋光的頂表面的水平面。再者,通過在CMP製程之前移除硬遮罩層結合在CMP製程期間使用CMP漿料,可降低CMP製程對拋光時間的敏感度。
根據一實施例,一種方法,包括:形成第一磊晶層於基板上方,以形成晶圓;沉積介電層於第一磊晶層上方;圖案化介電層以形成開口;透過開口蝕刻第一磊晶層,以形成凹槽;形成第二磊晶層於凹槽中;蝕刻介電層,以露出第一磊晶層的頂表面;及平坦化第一磊晶層的露出的頂表面及第二磊晶層的頂表面。在一實施例中,介電層包括氧化物或氮化物。在一實施例中,在蝕刻介電層之後,第二磊晶層的頂表面高於第一磊晶層的露出的頂表面。在一實施例中,蝕刻介電層的步驟包括使用稀氫氟酸(dilute hydrofluoric acid, dHF)的濕式蝕刻製程。在一實施例中,第一磊晶層包括第一材料且第二磊晶層包括第二材料,其中第一材料具有與第二材料不同的晶格常數。在一實施例中,平坦化第一磊晶層的露出的頂表面及第二磊晶層的頂表面的步驟包括對晶圓的頂表面進行化學機械平坦化(chemical mechanical planarization, CMP)製程。在一實施例中,在平坦化第一磊晶層的露出的頂表面及第二磊晶層的頂表面之後,晶圓的頂表面上的表面划痕的總數為4x10
1或更低。在一實施例中,方法更包括在平坦化第一磊晶層的露出的頂表面及第二磊晶層的頂表面之後的濕清潔製程,其中晶圓包括形成對準標記的多個溝槽,且其中在濕清潔製程之後,對準標記的該些溝槽的底部具有8xl0
2或更少的未移除的漿料顆粒。
根據又一實施例,一種方法,包括:形成第一摻雜區及第二摻雜區於基板的頂部;成長第一磊晶層於基板上方,其中第一磊晶層直接接觸第一摻雜區及第二摻雜區;沉積硬遮罩層於第一磊晶層上方;蝕刻硬遮罩層的第一部分中的開口,以露出第一磊晶層的第一頂表面;透過開口蝕刻第一磊晶層以形成凹槽,其中凹槽位於第一摻雜區正上方;成長第二磊晶層於凹槽中;移除硬遮罩層的多個剩餘部分以露出第一磊晶層的第二頂表面,其中第二磊晶層的頂表面高於第一磊晶層的露出的第二頂表面;及平坦化第二磊晶層的頂表面及第一磊晶層的露出的第二頂表面。在一實施例中,在移除硬遮罩層的該些剩餘部分之後,第二磊晶層的一部分直接接觸第一磊晶層的最頂表面。在一實施例中,在平坦化的步驟之後,第二磊晶層的頂表面以第一高度位於第一摻雜區的頂表面之上,且第一磊晶層的頂表面以第二高度位於第二摻雜區的頂表面之上,第一高度在約30nm至約80nm的範圍,第二高度在約30nm至約80nm的範圍。在一實施例中,第一高度與第二高度相同。在一實施例中,第一磊晶層包括矽且第二磊晶層包括矽鍺。在一實施例中,蝕刻硬遮罩層的第一部分中的開口的步驟包括電漿蝕刻製程。
根據又一實施例,一種方法,包括:形成第一磊晶層於基板上方;形成凹槽於第一磊晶層中;形成第二磊晶層於凹槽中;及平坦化第一磊晶層的頂表面及第二磊晶層的頂表面,其中平坦化第一磊晶層的頂表面及第二磊晶層的頂表面的步驟包括使用化學機械拋光(chemical mechanical polish, CMP)漿料,CMP漿料包括選擇性地降低第一磊晶層的移除速率的聚合物,其中漿料包括具有約0.5至約1.5重量百分比的範圍之濃度的磨料。在一實施例中,漿料包括增加材料移除的速率的酸。在一實施例中,酸包括乳酸、乙酸、甲酸、檸檬酸、或草酸。在一實施例中,酸的濃度在約5%至約35%的範圍。在一實施例中,磨料具有在約25nm至約45nm的範圍的平均尺寸。在一實施例中,聚合物包括聚乙二醇。
以上概述數個實施例之特徵,以使本發明所屬技術領域中具有通常知識者可更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解,可輕易地以本發明實施例為基礎,設計或修改其他製程及結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且可在不違背本發明之精神及範圍下,做各式各樣的改變、取代及替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
20:晶圓
30:對準標記
50:基板
50N:n型區
50P:p型區
52:鰭片
54:絕緣材料
56:淺溝槽隔離區
58:通道區
60:虛設介電層
62:虛設閘極層
64:遮罩層
72:虛設閘極
74:遮罩
80:閘極密封間隔物
82:磊晶源極/汲極區
86:閘極間隔物
87:接觸蝕刻停止層
88:第一ILD
89:區域
90:凹槽
92:閘極介電層
94:閘極電極
94A:襯層
94B:功函數調諧層
94C:填充材料
108:第二ILD
110:閘極接觸件
112:源極/汲極接觸件
140:軌跡
150:軌跡
210:介電層
300:光阻層
310:開口
320:n型區
350:開口
360:光阻層
400:p型區
410:半導體層
420:硬遮罩層
460:晶種層
500:凹槽
510:半導體區域
610:蝕刻製程
614:CMP製程
700:磊晶層
800:鰭片堆疊
810:半導體層
820:介電層
830:介電層
900:鰭片結構
910:鰭片結構
920:介電襯層
H1:高度
H2:高度
T1:厚度
W1:寬度
A-A:線
B-B:線
C-C:線
本揭露從以下詳細描述中配合附圖可最好地被理解。應強調的是,依據業界的標準做法,各種部件並未按照比例繪製且僅用於說明的目的。事實上,為了清楚討論,各種部件的尺寸可任意放大或縮小。
第1圖係根據一些實施例,以三維視圖繪示出FinFET的示例。
第2圖係根據一些實施例,繪示出晶圓的俯視圖。
第3圖、第4圖、第5圖、第6圖、第7圖、第8圖、第9圖、第10圖、第11A圖、第11B圖、第12圖、第13圖、第14圖、第15圖、第16圖、第17圖、第18圖、第19圖、第20A圖、第20B圖、第21A圖、第21B圖、第22A圖、第22B圖、第23A圖、第23B圖、第24A圖、第24B圖、第25A圖、第25B圖、第26A圖、第26B圖、第27A圖、第27B圖、第28A圖、第28B圖、第29A圖、第29B圖、第30A圖、第30B圖、第31A圖、第31B圖、第32A圖、第32B圖、第33A圖、第33B圖、第34A圖、第34B圖、第35A圖、第35B圖、第35C圖、第36A圖、第36B圖、第37A圖、第37B圖、第38A圖、第38B圖、第39A圖、及第39B圖係根據一些實施例,係FinFETs製造中的中間階段的剖面圖。
第11C圖係根據一些實施例,繪示出在CMP製程之後的形貌差異在晶圓半徑上的軌跡(trace)、以及在CMP製程之後最小幾何部件的尺寸差異在晶圓半徑上的軌跡。
320:n型區
400:p型區
410:半導體層
510:半導體區域
614:CMP製程
700:磊晶層
Claims (1)
- 一種半導體裝置的形成方法,包括: 形成一第一磊晶層於一基板上方,以形成一晶圓; 沉積一介電層於該第一磊晶層上方; 圖案化該介電層以形成一開口; 透過該開口蝕刻該第一磊晶層,以形成一凹槽; 形成一第二磊晶層於該凹槽中; 蝕刻該介電層,以露出該第一磊晶層的一頂表面;及 平坦化該第一磊晶層的該露出的頂表面及該第二磊晶層的一頂表面。
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US7691711B2 (en) * | 2008-01-31 | 2010-04-06 | General Electric Company | Method for fabricating silicon carbide vertical MOSFET devices |
US9236267B2 (en) | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US9171929B2 (en) | 2012-04-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device and method of making the strained structure |
US9093530B2 (en) | 2012-12-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
US9159824B2 (en) | 2013-02-27 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with strained well regions |
US9214555B2 (en) | 2013-03-12 | 2015-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer for FinFET channels |
US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
US9548303B2 (en) * | 2014-03-13 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with unique fin shape and the fabrication thereof |
US9608116B2 (en) | 2014-06-27 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFETs with wrap-around silicide and method forming the same |
US9553172B2 (en) * | 2015-02-11 | 2017-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for FinFET devices |
US9590102B2 (en) * | 2015-04-15 | 2017-03-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9564489B2 (en) | 2015-06-29 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple gate field-effect transistors having oxygen-scavenged gate stack |
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